JP2006339557A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high reliability-semiconductor device that prevents a substance in a film from badly affecting characteristics of the semiconductor device by allowing the substance to diffuse inside the semiconductor device after deposition, and to provide its manufacturing method. <P>SOLUTION: The semiconductor device has a semiconductor substrate 10 containing a CMOS element 12, an interlayer insulating layer 26 formed on the semiconductor substrate 10, and a plurality of contact plugs 34 formed by penetrating a part of the interlayer insulating layer 26. The interlayer insulating layer 26 contains a hydrogen barrier layer 30, and the hydrogen barrier layer 30 is configured by being formed in an intermediate layer of the interlayer insulating layer 26 so as not to contact the contact plugs 34. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  In this type of technical field, miniaturization of semiconductor devices is progressing due to high performance and high functionality of semiconductor devices. Such miniaturization is particularly remarkable in the technical field of semiconductor memory.

JP 2003-179212 A

  As miniaturization of semiconductor devices and thinning of films progress, new problems emerge. If the hydrogen in the film can be prevented from diffusing into the semiconductor device after film formation and adversely affecting the characteristics of the semiconductor device, the reliability of the semiconductor device can be improved.

  An object of the present invention is to provide a highly reliable semiconductor device and a method for manufacturing the same, preventing hydrogen in the film from diffusing into the semiconductor device after film formation and adversely affecting the characteristics of the semiconductor device. .

  (1) A semiconductor device according to the present invention includes a semiconductor substrate including a CMOS type element, an interlayer insulating layer formed on the semiconductor substrate, and a plurality of layers formed through part of the interlayer insulating layer. The interlayer insulating layer includes a hydrogen barrier layer, and the hydrogen barrier layer is formed in an intermediate layer of the interlayer insulating layer so as not to contact the contact plug. According to the present invention, since the hydrogen barrier layer is formed in the intermediate layer of the interlayer insulating layer, hydrogen that has entered the semiconductor device is blocked by the hydrogen barrier layer. Alternatively, it is absorbed by the hydrogen barrier layer. Therefore, it is possible to prevent hydrogen that has entered the semiconductor device from reaching the CMOS element. Therefore, the CMOS type element can be protected from the characteristic deterioration due to hydrogen without substantially affecting the final shape, and it is possible to prevent adversely affecting the characteristics of the semiconductor device.

  (2) The method for manufacturing a semiconductor device according to the present invention includes a first method for covering the CMOS type element and not exposing other portions on the surface of the semiconductor substrate including the CMOS type element on which the CMOS element is formed. Forming an interlayer insulating layer, forming a hydrogen barrier layer on the first interlayer insulating layer so as to expose a portion through which the contact plug of the first interlayer insulating layer passes; and Forming a second interlayer insulating layer on the first interlayer insulating layer and the hydrogen barrier layer. According to the present invention, by forming a hydrogen barrier layer between the first interlayer insulating layer and the second interlayer insulating layer, hydrogen that has entered the semiconductor device is blocked by the hydrogen barrier layer. Alternatively, it is absorbed by the hydrogen barrier layer. Therefore, it is possible to prevent hydrogen that has entered the semiconductor device from reaching the CMOS element. Therefore, the CMOS type element can be protected from the characteristic deterioration due to hydrogen without substantially affecting the final shape, and it is possible to prevent adversely affecting the characteristics of the semiconductor device.

Embodiments to which the present invention is applied will be described below with reference to the drawings. However, the present invention is not limited to the following embodiments.
(Structure of semiconductor device)
First, the structure of the semiconductor device according to this embodiment will be described. FIG. 1 is a diagram for explaining a semiconductor device according to an embodiment to which the present invention is applied.

  The semiconductor device according to the present embodiment includes a semiconductor substrate 10 as shown in FIG. The semiconductor substrate 10 is a silicon substrate, for example. The silicon substrate is made of, for example, single crystal silicon. A CMOS type element 12 is formed on the semiconductor substrate 10. The CMOS element 12 includes, for example, an N-channel insulated gate field effect transistor (NMOSFET) 12A and a P-channel insulated gate field effect transistor (PMOSFET) 12B. The NMOSFET 12A and the PMOSFET 12B are electrically isolated by element isolation regions 14 formed on the semiconductor substrate 10, respectively. The element isolation region 14 is formed by an STI (Shallow Trench Isolation) method or the like. Each MOSFET 12A, 12B has a structure in which gate electrodes 18A, 18B are formed on a semiconductor substrate 10 with a gate insulating film 16 interposed therebetween. The gate electrodes 18A and 18B are polysilicon gate electrodes made of polycrystalline silicon or metal gate electrodes made of a metal layer. A channel region (not shown) is provided in the semiconductor substrate 10 immediately below the gate insulating film 16. Impurity diffusion regions 20 and 22 constituting a source region or a drain region are provided in the semiconductor substrate 10 with the channel region interposed therebetween. Sidewall insulating layers 24 are formed on both side surfaces of the gate electrodes 18A and 18B. In the NMOSFET 12A, the impurity diffusion regions 20 and 22 are formed in an N type, and in the PMOSFET 12B, the impurity diffusion regions 20 and 22 are formed in a P type.

  The semiconductor device according to the present embodiment includes an interlayer insulating layer 26 as shown in FIG. The interlayer insulating layer 26 is formed on the surface of the semiconductor substrate 10 on which the MOSFETs 12A and 12B are formed so as to cover the MOSFETs 12A and 12B and not expose other portions. The upper surface of the interlayer insulating layer 26 is planarized by, for example, a CMP (Chemical Mechanical Polishing) method. The interlayer insulating layer 26 includes a first interlayer insulating layer 28, a hydrogen barrier layer 30, and a second interlayer insulating layer 32. A hydrogen barrier layer 30 is formed on the first interlayer insulating layer 28. A second interlayer insulating layer 32 is formed on the hydrogen barrier layer 30. The first interlayer insulating layer 28 and the second interlayer insulating layer 32 are formed of a material such as silicon oxide or silicon nitride by a film forming method such as PECVD. As the silicon oxide film at this time, a silicon oxide film using BPSG (boron or phosphorus-containing silicon oxide film) or TEOS (tetraethoxysilane) having high flatness as a film after formation may be used. The hydrogen barrier layer 30 is formed in an intermediate layer of the interlayer insulating layer 26 so as to absorb hydrogen moving through the interlayer insulating layer 26. The hydrogen barrier layer 30 is composed of a single film, for example, titanium nitride or silicon nitride. Alternatively, two or more films, for example, a titanium film is provided at the bottom, and this titanium film is followed by a titanium nitride film. Further, the material of the hydrogen barrier layer 30 may be hafnium, zirconium, or the like as long as it has a property of absorbing hydrogen. The hydrogen barrier layer 30 is deposited by conventional sputtering or CVD techniques. In the hydrogen barrier layer 30, a hole 36 is formed so as not to contact the contact plug 34.

  The semiconductor device according to the present embodiment includes a plurality of contact plugs 34 as shown in FIG. The plurality of contact holes 38 are formed through a part of the interlayer insulating layer 26 and are used for electrical connection with the MOSFETs 12 </ b> A and 12 </ b> B formed in the semiconductor substrate 10. The contact plug 34 is formed by, for example, filling tungsten in the contact hole 38. The contact plug 34 is formed so as not to contact the hydrogen barrier layer 30.

The semiconductor device according to the present embodiment is configured as described above. As described above, in the semiconductor device, the hydrogen barrier layer 30 is formed in the intermediate layer of the interlayer insulating layer 26. Thereby, hydrogen that has entered the semiconductor device is blocked by the hydrogen barrier layer 30. Alternatively, it is absorbed by the hydrogen barrier layer 30. Therefore, it is possible to prevent hydrogen that has entered the semiconductor device from reaching the gate insulating films 16 of the MOSFETs 12A and 12B. Therefore, the gate insulating film 16 of each of the MOSFETs 12A and 12B can be protected from the characteristic deterioration due to hydrogen with little influence on the final shape, and it is possible to prevent adverse effects on the characteristics of the semiconductor device. .
(Method for manufacturing semiconductor device)
A method for manufacturing a semiconductor device according to an embodiment to which the present invention is applied will be described below. 2 and 3 are diagrams for explaining a method of manufacturing a semiconductor device according to an embodiment to which the present invention is applied.

  The method for manufacturing a semiconductor device according to this embodiment may include preparing a semiconductor substrate 10 as shown in FIG. Any of the contents described above may be applied to the structure of the semiconductor substrate 10.

  First, as shown in FIG. 2A, a CMOS type element 12 (each MOSFET 12A, 12B) is formed on a semiconductor substrate 10 by a known method. Specifically, the element isolation region 14 is formed on the semiconductor substrate 10 by a known method. Next, the surface of the semiconductor substrate 10 is oxidized to form a gate insulating film 16. As the gate insulating film 16, for example, a silicon oxide layer is formed by a thermal oxidation method. Then, after a polysilicon layer is deposited on the entire surface by, for example, a CVD method, the polysilicon layer is patterned by a photolithography technique and an etching technique to form gate electrodes 18A and 18B made of polysilicon. The gate electrodes 18A and 18B are not particularly limited as long as they are materials that function as metal gate electrodes, and those having low resistance and being able to withstand heat treatment in later steps are preferable. For example, aluminum, molybdenum, tantalum, tungsten, titanium, or nitrides thereof can be given. Next, conductive impurity ions are implanted, and the implanted impurities are activated to form impurity diffusion regions 20 and 22 to be source / drain regions. Thereafter, the sidewall insulating layer 24 is formed by a known method, and the MOSFETs 12A and 12B are formed.

Next, as illustrated in FIG. 2B, a first interlayer insulating layer 28 is formed over the semiconductor substrate 10. Specifically, a first interlayer insulating layer 28 made of a silicon oxide film (SiO ₂ ) is formed on the semiconductor substrate 10 by, eg, thermal CVD (Chemical Vapor Deposition). At this time, for example, the formation of the first interlayer insulating layer 28 is stopped when the thickness is about half of the thickness of the finally formed interlayer insulating layer 26. For example, the thickness is about 200 to 700 nm.

  Next, as illustrated in FIG. 2C, the hydrogen barrier layer 30 is formed over the first interlayer insulating layer 28. Specifically, the hydrogen barrier layer 30 made of a thin film of titanium or titanium nitride is formed on the first interlayer insulating layer 28 by a method such as sputtering or CVD. For example, the film thickness is about 5 to 50 nm.

  Next, as shown in FIG. 3A, holes 36 are opened in the hydrogen barrier layer 30. Specifically, a resist film (not shown) is applied on the hydrogen barrier layer 30. Next, a resist pattern (not shown) for forming the holes 36 is formed. Thereafter, the formation position of the hole 36 in the hydrogen barrier layer 30 is removed by an etching process (for example, a dry etching process) using the resist pattern as a mask.

Next, as shown in FIG. 3B, a second interlayer insulating layer 32 is formed on the hydrogen barrier layer 30 and the first interlayer insulating layer 28. Specifically, a second interlayer insulating layer 32 made of a silicon oxide film (SiO ₂ ) is formed on the hydrogen barrier layer 30 and the first interlayer insulating layer 28 by, eg, thermal CVD (Chemical Vapor Deposition). Form. At this time, the thickness of the second interlayer insulating layer 32 is set to the final thickness of the interlayer insulating layer 26. Thereafter, flat processing such as a known CMP method may be performed.

  Next, contact plugs 34 are formed in the interlayer insulating layer 26 as shown in FIG. Specifically, a resist film (not shown) is applied on the interlayer insulating layer 26. Next, a resist pattern (not shown) for forming the contact hole 38 is formed. Next, using the resist pattern as a mask, the formation position of the contact hole 38 in the interlayer insulating layer 26 is removed by an etching process (for example, a dry etching process). Thereafter, a conductive member (for example, tungsten) is deposited in the contact hole 38 and on the interlayer insulating layer 26. Next, the conductive member deposited on the interlayer insulating layer 26 is removed. The conductive member is removed by, for example, a CMP method. As described above, the conductive member is filled only in the contact hole 38, and the contact plug 34 is completed. The diameter of the contact plug 34 is 0.4 μm, for example. Thereafter, the surface of the interlayer insulating layer 26 and the contact plug 34 is planarized by a known CMP method.

  Through the above steps, the semiconductor device of this embodiment can be formed. Thereafter, a wiring layer (not shown) is formed on the interlayer insulating layer 26 by using a photolithography technique and an etching technique. Thus, the MOSFETs 12A and 12B and the wiring layer (not shown) are electrically connected via the contact plug 34.

  A semiconductor device may be manufactured through the above steps. As described above, in the method for manufacturing a semiconductor device according to the present embodiment, the hydrogen barrier layer 30 is formed between the first interlayer insulating layer 28 and the second interlayer insulating layer 32. Thereby, hydrogen that has entered the semiconductor device cannot exceed the hydrogen barrier layer 30 or is absorbed by the hydrogen barrier layer 30. Therefore, it is possible to prevent hydrogen that has entered the semiconductor device from reaching the gate insulating films 16 of the MOSFETs 12A and 12B. Therefore, the gate insulating film 16 of each of the MOSFETs 12A and 12B can be protected from the characteristic deterioration due to hydrogen with little influence on the final shape, and it is possible to prevent adverse effects on the characteristics of the semiconductor device. .

  In addition, this invention is not limited to embodiment mentioned above, A various deformation | transformation is possible. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same purposes and results). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that achieves the same effect as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment. Furthermore, the present invention includes contents that exclude any of the technical matters described in the embodiments in a limited manner. Or this invention includes the content which excluded the well-known technique limitedly from embodiment mentioned above.

It is a figure for demonstrating the semiconductor device which concerns on embodiment to which this invention is applied. It is a figure for demonstrating the method to manufacture the semiconductor device which concerns on embodiment to which this invention is applied. It is a figure for demonstrating the method to manufacture the semiconductor device which concerns on embodiment to which this invention is applied.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate 12 ... CMOS type element 12A ... NMOSFET 12B ... PMOSFET 14 ... Element isolation region 16 ... Gate insulating film 18A, 18B ... Gate electrode 20, 22 ... Impurity diffusion region 24 ... Side wall insulating layer 26 ... Interlayer insulating layer 28 ... first interlayer insulating layer 30 ... hydrogen barrier layer 32 ... second interlayer insulating layer 34 ... contact plug 36 ... hole 38 ... contact hole.

Claims (2)

A semiconductor substrate including a CMOS type element;
An interlayer insulating layer formed on the semiconductor substrate;
A plurality of contact plugs formed through a part of the interlayer insulating layer;
Have
The interlayer insulating layer includes a hydrogen barrier layer,
The semiconductor device, wherein the hydrogen barrier layer is formed in an intermediate layer of the interlayer insulating layer so as not to contact the contact plug. Forming a first interlayer insulating layer on the surface of the semiconductor substrate including the CMOS type element on which the CMOS type element is formed so as to cover the CMOS type element and not to expose other portions;
Forming a hydrogen barrier layer on the first interlayer insulating layer so as to expose a portion through which the contact plug of the first interlayer insulating layer passes; and
Forming a second interlayer insulating layer on the first interlayer insulating layer and the hydrogen barrier layer;
A method of manufacturing a semiconductor device including:

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