JP2006339439A - Chip, fault countermeasure system, and fault countermeasure method for chip - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a fault countermeasure system for reducing a time and costs required for countermeasures against faults caused by a power supply. <P>SOLUTION: The fault countermeasure system is composed so that the fault countermeasures are implemented on a chip which is placed on a lead frame having a power supply terminal and a grounding terminal, and also provided with an internal circuit, a main power supply pad connected to the power supply terminal and the internal circuit, a main grounding pad connected to the grounding terminal and the internal circuit, a standby power supply pad arranged adjacently to the main power supply pad, and a standby grounding pad arranged adjacently to the main grounding pad. The system is provided with an inspection part 4 for inspecting electrical characteristics of the chip by supplying power supply potential and grounding potential to the power supply terminal and the grounding terminal, respectively, a fault determination means 101 for determining the presence or the absence of faults in the chip on the basis of the inspection results, and a bonding device 301 for bonding the standby power supply pad with the power supply terminal and the standby grounding pad with the grounding terminal when it is determined that the faults are present. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a chip, a defect countermeasure system, and a chip defect countermeasure method.

  In recent years, in chip manufacturing, the degree of integration has been improved by miniaturization of processes and multilayering of wiring layers, and problems due to power sources tend to occur easily due to system mounting.

  For example, an ESD protection circuit (hereinafter simply referred to as “protection circuit”) is provided between a power supply terminal and a ground terminal in order to prevent electrostatic breakdown (ESD). However, there are cases where the internal circuit cannot be protected due to an increase in wiring resistance resulting from the miniaturization of the process. Further, since the number of necessary signal terminals is increased due to the system mounting, the number of power supply terminals and ground terminals tends to be reduced to a necessary minimum, and a voltage drop tends to occur at the center of the chip. Also, in order to reduce the number of power supply terminals and ground terminals, the power supply terminals and ground terminals are shared by multiple internal circuits such as output circuits. And cause deterioration of performance.

When a problem caused by the power source occurs as described above, the cause of the problem is identified and a countermeasure plan is devised, and the design is changed (see, for example, Patent Document 1). However, in the simulation after the design change, the improvement effect due to the design change is difficult to see, so in order to confirm the effect of the countermeasure against the defect, the photomask was corrected and manufactured, and the inspection was performed after the chip was remade. For this reason, it takes time and money to take measures against a malfunction caused by the power source.
JP 2000-252360 A

  An object of the present invention is to provide a chip, a trouble countermeasure system, and a chip trouble countermeasure method that can reduce the time and cost required for the trouble caused by a power source.

  According to one aspect of the present invention, the internal circuit, the main power pad connected to the power terminal and the internal circuit, and the ground terminal and the internal circuit are mounted on the lead frame having the power terminal and the ground terminal. A failure countermeasure system for taking a countermeasure against a chip comprising a main ground pad, a spare power pad disposed adjacent to the main power pad, and a spare ground pad disposed adjacent to the main ground pad. (B) An inspection unit that inspects the electrical characteristics of the chip by supplying a power supply potential and a ground potential to the power supply terminal and the ground terminal, and (b) a defect determination that determines whether there is a chip defect based on the result of the inspection. And (c) a failure provided with a spare power supply pad and a power supply terminal and a bonding device for bonding the spare grounding pad and the grounding terminal when it is determined that there is a failure. Bet system is provided.

  According to another aspect of the present invention, (a) an internal circuit, a main power pad and a main ground pad respectively connected to the internal circuit, a spare power pad disposed adjacent to the main power pad, and a main ground pad (B) a step of mounting the chip on a lead frame having a power supply terminal and a ground terminal; and (c) a main power supply pad and a power supply terminal. The step of bonding the main ground pad and the ground terminal, (d) the step of supplying the power supply potential and the ground potential to the power supply terminal and the ground terminal to inspect the electrical characteristics of the chip, and (e) the result of the inspection. A step of determining whether or not there is a defect in the chip, and (f) if it is determined that there is a defect, bonding the spare power pad and the power terminal, and the spare ground pad and the ground terminal. Corrective measures method of chip and a step is provided.

  According to another aspect of the present invention, there is provided a chip mounted on a lead frame having a power supply terminal and a ground terminal, wherein (a) an internal circuit and (b) a main power supply connected to the power supply terminal and the internal circuit. A pad, (c) a main ground pad connected to the ground terminal and the internal circuit, (d) a main protection circuit connected between the main power pad and the main ground pad, and (e) adjacent to the main power pad. A spare power pad connected to the power terminal, (f) a spare ground pad placed adjacent to the main ground pad and connected to the ground terminal, and (g) a spare power pad and a spare ground pad. A chip is provided comprising a pre-protection circuit connected in between.

  ADVANTAGE OF THE INVENTION According to this invention, the chip | tip, the malfunction countermeasure system, and the malfunction countermeasure method of a chip which can reduce the time and expense which are required for the countermeasure against the malfunction resulting from a power supply can be provided.

  Next, with reference to the drawings, embodiments of the present invention and modifications thereof will be described. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic. Further, the embodiment described below exemplifies an apparatus and a method for embodying the technical idea of the present invention, and the technical idea of the present invention is the material, shape, structure, The layout is not specified as follows. The technical idea of the present invention can be variously modified within the scope of the claims.

  As shown in FIG. 1, a semiconductor manufacturing system (fault countermeasure system) according to an embodiment of the present invention is mounted on a lead frame having a power supply terminal and a ground terminal, and is connected to the internal circuit, the power supply terminal, and the internal circuit. A main power pad, a main ground pad connected to the ground terminal and the internal circuit, a spare power pad disposed adjacent to the main power pad, and a spare ground pad disposed adjacent to the main ground pad If there is a defect, the inspection unit 4 for inspecting electrical characteristics, the defect determination means 101 for determining the presence or absence of a chip defect based on the result of the inspection, If determined, a spare power supply pad and a power supply terminal, and a manufacturing section 3 for bonding the spare ground pad and the ground terminal are provided.

  Here, the “failure” means a failure caused by the power source such as ESD, voltage drop, and power supply noise. In the embodiment of the present invention, an example in which ESD countermeasures are taken as “fault countermeasures” will be described.

  The defect determination unit 101 is included in the defect countermeasure unit 10. The defect countermeasure unit 10, the manufacturing unit 3, and the inspection unit 4 are included in the semiconductor manufacturing system shown in FIG. The semiconductor manufacturing system further includes a design unit 1, a mask production unit 2, an inspection result storage device 5, a main storage device 6, a program storage device 7, an input device 8, and an output device 9.

  As the design unit 1, a computer-aided design (CAD) device or the like for performing layout design can be used. The design unit 1 performs layout design by determining functions and specifications of a circuit of a desired semiconductor device.

  The mask preparation unit 2 includes, for example, a pattern generator (PG) and a developing device. The mask production unit 2 converts the design data from the design unit 1 into drawing data. Further, the mask preparation unit 2 draws a mask pattern on the resist film on the mask substrate based on the drawing data, and develops the resist film, thereby producing a photomask (reticle).

The manufacturing unit 3 manufactures a chip using the photomask manufactured by the mask manufacturing unit 2. The manufacturing unit 3 includes a manufacturing line in which various semiconductor manufacturing apparatuses 301, 302, 303,..., 30n are arranged (n is a natural number). The semiconductor manufacturing apparatuses 301, 302, 303,..., 30n include, for example, an ion implantation apparatus, an impurity diffusion apparatus, a thermal oxidation apparatus for forming a silicon oxide film (SiO ₂ film), an SiO ₂ film, and a phosphor glass. Chemical vapor deposition (CVD) apparatus for depositing (PSG) film, boron glass (BSG) film, boron phosphorous glass (BPSG) film, silicon nitride film (Si ₃ N ₄ film), polysilicon film, etc., PSG film , Heat treatment apparatus for reflowing (melting) BSG film, BPSG film, etc., heat treatment apparatus for densification such as CVD oxide film, heat treatment apparatus for forming silicide film, sputtering apparatus for depositing metal wiring layer, vacuum evaporation apparatus, and metal Plating processing equipment that forms wiring layers by plating, chemical and mechanical polishing (CMP) equipment that polishes the surface of a semiconductor substrate, and semiconductor substrate surface Dry or wet etching apparatus for etching, cleaning apparatus for resist removal or cleaning with a solution, spin coating apparatus (spinner) related to photolithography processing, exposure apparatus such as a stepper, dicing apparatus, dicing chip-shaped semiconductor device electrode Various semiconductor manufacturing apparatuses such as a bonding apparatus for connecting (pad) to a lead frame are included. Furthermore, ancillary facilities such as a pure water production apparatus and a gas purification apparatus may be included. These semiconductor manufacturing apparatuses can be either batch type apparatuses or single wafer type apparatuses. The batch type apparatus or the single wafer type apparatus may be similarly applied to all the embodiments described later.

  The manufacturing unit 3 manufactures a chip 10a as shown in FIG. 2, for example, as an ESD countermeasure chip. The chip 10 a is a chip 10 a that can be placed on a lead frame 20 having power terminals 22, 24, 26, 28 and ground terminals 21, 23, 25, 27, and includes internal circuits 11 to 14, power terminals 22, Main power supply pads 32, 34, 36, and 38 connected to 24, 26, and 28 and internal circuits 11 to 14, and ground terminals 21, 23, 25, and 27, and internal circuits 11 to 14, respectively. The main ground pads 31, 33, 35, 37, and the protection circuits connected between the main power pads 32, 34, 36, 38 and the main ground pads 31, 33, 35, 37 (hereinafter referred to as "main protection circuit"). ) 60a-60p, standby power supply pads 42, 44, 46, 48 disposed adjacent to the main power supply pads 32, 34, 36, 38, respectively, and the main ground pad 31, 3, 35, 37 are connected between spare ground pads 41, 43, 45, 47 and spare power supply pads 42, 44, 46, 48 and spare ground pads 41, 43, 45, 47, respectively. Protection circuits (hereinafter referred to as “preliminary protection circuits”) 61a to 61l.

  Each of the main power supply pads 32, 34, 36, and 38 includes any one of the main power supply wirings 51, 53, 55, and 57, any of the main protection circuits 60a to 60p, and any of the main ground wirings 52, 54, 56, and 58, respectively. Are connected to the main ground pads 31, 33, 35, and 37, respectively. For example, the main power supply pad 32 and the main ground pad 31 are connected via the main power supply wiring 57, the protection circuit 60a, and the main ground wiring 58. The main power supply pad 32 and the main ground pad 33 are connected via a main power supply wiring 57, a protection circuit 60 h and a main ground wiring 56. The main power supply pad 32 and the main ground pad 35 are connected via the main power supply wiring 57, the protection circuit 60 i and the main ground wiring 54. The main power supply pad 32 and the main ground pad 37 are connected via a main power supply wiring 57, a protection circuit 60m, and a main ground wiring 52. Each of the spare power pads 42, 44, 46, and 48 is connected to the spare ground pads 41, 43, 45, and 47 via the spare power wiring 81, the spare protection circuits 61a to 61l, and the spare ground wiring 82. .

  As the main protection circuits 60a to 60p and the spare protection circuits 61a to 61l, there are protection circuits composed of a single element or a plurality of elements. For example, a MOS field effect transistor (MOSFET) as shown in FIG. 3 may be used. When the surge current (ESD current) flows, the main protection circuits 60a to 60p and the auxiliary protection circuits 61a to 61l absorb the surge current from the drain side and release it to the source side.

  The power supply potentials VDD1 to VDD4 are supplied from the power supply terminals 22, 24, 26, and 28, respectively, and the ground potentials VSS1 to VSS4 are supplied from the ground terminals 21, 23, 25, and 27, respectively. For example, when the power supply potential VDD1 is applied to the power supply terminal 22 with reference to the ground potential VSS3 of the ground terminal 25, it is discharged to the ground terminal 25 via the main protection circuit 60i inserted between the power supply terminal 22 and the ground terminal 25. Current path exists. At this time, if a surge current flows from the power supply terminal 22, as shown in FIG. 4, the internal circuit 11 before the main protection circuit 60i is destroyed due to the influence of the wiring resistance from the power supply terminal 22 to the main protection circuit 60i. Destruction may occur.

  The inspection unit 4 shown in FIG. 1 has functions such as the function of a chip to be inspected, such as the chip 10a, leakage current, analog characteristics, DC characteristics, etc., electrical characteristics, lead shape / dimension state, reliability, etc. A tester group for inspection is provided. The inspection unit 4 supplies, for example, power supply potentials VDD1 to VDD4 to the power supply terminals 22, 24, 26, and 28, and supplies ground potentials VSS1 to VSS4 to the ground terminals 21, 23, 25, and 27, respectively. Inspect the occurrence of defects such as voltage drop or power supply noise. The inspection result by the inspection unit 4 is stored in the inspection result storage device 5. In the case where the chip 10a is an inspection chip, countermeasures for defects described below are performed on a product chip different from the chip 10a. On the other hand, when the chip 10a is a product chip, countermeasures against defects are taken for the chip 10a.

  The defect countermeasure unit 10 is composed of, for example, a central processing unit (CPU). The defect countermeasure unit 10 includes a defect determination unit 101, a defect countermeasure unit 102, an improvement confirmation unit 103, and a correction method determination unit 104. The defect determination means 101 reads out the inspection result by the inspection unit 4 from the inspection result storage device 5 and determines whether there is a defect in the chip 10a.

  The defect countermeasure means 102 determines whether the defect of the chip 10a is due to ESD based on the inspection result. If the problem is due to ESD, a signal for performing ESD countermeasures is output to the bonding apparatus (for example, the semiconductor manufacturing apparatus 301). For example, when ESD due to a surge current from the power supply terminal 22 becomes a problem, the bonding apparatus (for example, the semiconductor manufacturing apparatus 301), for example, between the spare power supply pad 42 and the power supply terminal 22, as shown in FIG. The preliminary ground pad 45 and the ground terminal 25 are bonded with bonding wires 99a and 99b, respectively. As a result, it is possible to use a current path (shown by a thick line) from the standby power supply pad 42 to the backup ground pad 45 via the backup power supply wiring 81, the backup protection circuits 61a to 61l and the backup ground wiring 82.

  In the chip 10 a shown in FIG. 5, the surge current flowing from the power supply terminal 22 has a current path through the main protection circuit 60 i between the power supply terminal 22 and the ground terminal 25 and a current path through the spare protection circuits 61 a to 61 l. Via the ground terminal 25. Therefore, the preliminary protection circuits 61a to 61l can be used and the wiring resistance is reduced, so that the ESD of the internal circuit 11 can be prevented.

  The improvement confirmation means 103 shown in FIG. 1 compares the inspection result for the chip 10a before ESD countermeasure shown in FIG. 2 with the inspection result for the chip 10a after ESD countermeasure shown in FIG. Check if the problem is improved. The correction method determination unit 104 determines to modify the design data when the improvement confirmation unit 103 determines that the defect has not been improved, and determines whether to modify the wiring layer or the diffusion layer of the design data. . It should be noted that the criteria for determining whether to modify the wiring layer or the diffusion layer may be stored in, for example, the storage device of the design unit 1.

  The main storage device 6 functions as a temporary data memory or the like that temporarily stores data or the like used during the program execution process in the defect countermeasure unit 1 or the like, or is used as a work area. As the main storage device 6, for example, a semiconductor memory, a magnetic disk, an optical disk, a magneto-optical disk, a magnetic tape, or the like can be used. As the input device 5, for example, a recognition device such as a keyboard, a mouse, and an OCR, a graphic input device such as an image scanner, and a special input device such as a voice input device can be used. As the output device 6, a display device such as a liquid crystal display or a CRT display, or a printing device such as an ink jet printer or a laser printer can be used.

  Next, a chip (LSI) manufacturing method and a defect countermeasure method according to an embodiment of the present invention will be described with reference to the flowchart of FIG. The chip manufacturing method described below is merely an example, and it is needless to say that the present invention can be realized by various other manufacturing methods including this modification.

  (A) First, in step S101, the design unit 1 shown in FIG. 1 obtains electrical characteristics by process mask simulation or device simulation. LSI circuit simulation is performed using the electrical characteristics. Here, on the layout of the CAD device, the internal circuits 11 to 14 shown in FIG. 2 are arranged, and the main power supply pads 32, 34, 36 and 38 and the main ground pads 31 and 33 connected to the internal circuits 11 to 14. , 35, 37, and main protection circuits 60a-60p connected between the main power pads 32, 34, 36, 38 and the main ground pads 31, 33, 35, 37 are arranged, and the main power pads 32, 34, 36, 38 and the main ground pads 31, 33, 35, 37 are arranged adjacent to the spare power supply pads 42, 44, 46, 48 and the spare ground pads 41, 43, 45, 47, respectively. Spare protection circuits 61a to 61l connected between 42, 44, 46 and 48 and spare ground pads 41, 43, 45 and 47 are arranged. As a result, design data of the chip 10a is created.

  (B) Next, in step S102, the mask making unit 2 converts the design data created in step S101 into drawing data. A mask pattern is drawn on the resist film on the transparent substrate by the pattern generator, and the resist film is developed by the developing device to produce a photomask. A photomask for each layer corresponding to each stage of the LSI manufacturing process is manufactured, and a set of photomasks is prepared.

  (C) The chip manufacturing process in step S103 is performed, for example, according to the procedure shown in FIG. In the front-end process in step S302, the oxidation process in step S310, the resist coating process in step S311, the photolithography process in step S312, the ion implantation process in step S313, the heat treatment process in step S314, and the like are repeatedly performed. When the series of processes is completed, the process proceeds to step S303. In the back-end process in step S303, a chemical vapor deposition (CVD) process in step S315, a resist coating process in step S316, a photolithography process in step S317, an etching process in step S318, a metal deposition process in step S319, and the like are repeatedly performed. Is done. When the multilayer wiring structure is completed through a series of processes, the process proceeds to the subsequent process of step S320, and the wafer is divided into a predetermined chip size by dicing. Then, it is mounted on a lead frame 20 made of metal or ceramics. Further, as shown in FIG. 2, main power pads 32, 34, 36, and 38 and main ground pads 31, 33, 35, and 37 on the chip 10a, and power terminals 22, 24, 26, and 28 of the lead frame 20 and The ground terminals 21, 23, 25, and 27 are bonded by bonding wires 91 to 98 such as gold wires.

  (D) In step S110 of FIG. 6, the electrical characteristics of the chip 10a are inspected using the inspection unit 4 shown in FIG. The inspection result is stored in the inspection result storage device 5. The defect determination means 101 reads the inspection result from the inspection result storage device 5 and determines whether there is a defect in the chip 10a. If it is determined that there is no defect, the process proceeds to step S104. On the other hand, if it is determined that there is a defect, the process proceeds to step S120, and the defect countermeasure unit 102 determines whether the defect is due to ESD or another defect based on the inspection result. In the case of ESD, the process proceeds to step S130 to take a countermeasure against the problem. As shown in FIG. 5, the bonding apparatus (for example, the semiconductor manufacturing apparatus 301) includes a spare power supply pad 42 adjacent to the main power supply pad 32 and the power supply terminal 22 and a spare ground pad 45 adjacent to the main ground pad 35 and the ground terminal. 25, bonding is performed with bonding wires 99a and 99b.

  (E) In step S140, the inspection unit 4 inspects the electrical characteristics of the chip 10a after the ESD countermeasure shown in FIG. The improvement confirmation means 103 compares the inspection result for the chip 10a before the ESD countermeasure shown in FIG. 2 with the inspection result for the chip 10a after the ESD countermeasure shown in FIG. 5, and confirms whether the defect has been improved by the ESD countermeasure. To do. If the problem is improved, the process proceeds to step S104. On the other hand, if the problem has not been improved, the process proceeds to step S150.

  (F) In step S150, the correction method determination unit 104 determines whether to correct the wiring layer of the design data or the diffusion layer based on the inspection result and the design data. If it is determined that the wiring layer is to be corrected, the process proceeds to step S161. In step S161, the design unit 1 corrects the wiring layer, and in step S162, it is verified by simulation whether the correction is satisfactory. In step S163, a mask with a corrected wiring layer is produced. Returning to the procedure of step S103, the manufacturing unit 3 recreates the chip using the mask whose wiring layer is corrected.

  (G) On the other hand, if it is determined in step S150 that the diffusion layer is to be corrected, the process proceeds to step S171. In step S171, the design unit 1 corrects the diffusion layer of the design data, and in step S172, it is verified by simulation whether there is no problem in the correction. In step S173, the mask making unit 2 makes a photomask with a modified diffusion layer. Returning to the procedure of step S102, the manufacturing unit 3 remakes a chip using a photomask having a modified diffusion layer.

  (H) In step S104, a required package assembly process such as resin sealing is performed. The chip is completed through predetermined inspections such as a characteristic inspection regarding the performance and function of the chip, a lead shape / dimension state, and a reliability test. In step S105, the chips that have cleared the above steps are packaged for protection from moisture, static electricity, etc., and shipped.

  As described above, according to the embodiment of the present invention, only the bonding in step S130 is performed before the wiring is modified in steps S161 to S163 and the diffusion layer in steps S171 to S173 is modified to remake the chip. , It is possible to take countermeasures against defects (ESD countermeasures). Therefore, the wiring correction time, the verification work time, the mask manufacturing time, and the chip manufacturing time associated with the mask correction are not required, and the cost of the above work can be suppressed. Furthermore, since it is possible to confirm the improvement effect by the countermeasure against the malfunction (ESD countermeasure) without re-creating the chip in step S140, the evaluation time can be shortened.

  The series of procedures shown in FIG. 6 can be executed by controlling the semiconductor manufacturing system shown in FIG. 1 by an algorithm program equivalent to FIG. This program may be stored in the program storage device 7. In addition, the program can be stored in a computer-readable recording medium, and the recording medium can be read into the program storage device 7 to execute a series of procedures of the present invention. Here, the “computer-readable recording medium” means a medium capable of recording a program such as an external memory device of a computer, a semiconductor memory, a magnetic disk, an optical disk, a magneto-optical disk, and a magnetic tape. To do. Specifically, a “flexible disk, CD-ROM, MO disk, cassette tape, open reel tape, etc.” are included in the “computer-readable recording medium”. For example, the semiconductor manufacturing system can be configured to incorporate or externally connect a flexible disk device (flexible disk drive) and an optical disk device (optical disk drive).

(First modification)
In the first modification of the embodiment of the present invention, an example in which a voltage drop countermeasure is taken as a countermeasure against a failure will be described. In the chip malfunction countermeasure method according to the first modified example, in step S103 in FIG. 6, the manufacturing unit 3 illustrated in FIG. 1 manufactures a chip 10b as illustrated in FIG. 8 as a chip for voltage drop countermeasures. . The chip 10b is different from the chip 10a shown in FIG. 2 in that there are no spare protection circuits 61a to 61l, spare power wiring 81 and spare ground wiring 82, spare power pads 42, 44, 46 and 48, and spare ground pad 41. , 43, 45, 47 are connected to the internal circuits 11-14.

  In step S110 of FIG. 6, for example, the power supply potentials VDD1 to VDD4 are supplied to the power supply terminals 22, 24, 26, and 28 using the inspection unit 4 shown in FIG. Are supplied with ground potentials VSS1 to VSS4, respectively, to inspect the electrical characteristics of the chip 10b. The inspection result is stored in the inspection result storage device 5. The defect determination unit 101 reads out the inspection result from the inspection result storage device 5 and determines whether there is a defect in the chip 10b. If it is determined that there is no defect, the process proceeds to step S104. On the other hand, if it is determined that there is a defect, the process proceeds to step S120, and the defect countermeasure unit 102 determines whether the defect is a voltage drop or another defect based on the inspection result. If the failure is due to a voltage drop, the process proceeds to step S130.

  In step S130, voltage drop countermeasures are taken. For example, when a voltage drop between the power supply terminal 22 and the ground terminal 21 and the internal circuit 11 shown in FIG. 8 becomes a problem, the bonding apparatus (for example, the semiconductor manufacturing apparatus 301) may connect the standby power supply pad 42 and the power supply terminal 42 as shown in FIG. Bonding is performed between the power supply terminals 22 and between the auxiliary ground pad 45 and the ground terminal 25. As a result, the bonding wires 99c and 99d, the spare power supply pad 42 and the spare ground pad 45, and the wiring layer (shown in bold lines) that conducts the internal circuit 11 are connected to the power supply terminal 22, the ground terminal 25, and the internal circuit 11. The wiring resistance component between the two can be reduced, and a voltage drop can be prevented.

  According to the first modification of the embodiment of the present invention, only the bonding in step S130 is performed before the chip 10b is remade by correcting the wiring in steps S161 to S163 or the diffusion layer in steps S171 to S173. Therefore, it is possible to take countermeasures (voltage drop countermeasures). Therefore, the wiring correction time, the verification work time, the mask manufacturing time, and the chip manufacturing time associated with the mask correction are not required, and the cost of the above work can be suppressed. Furthermore, since it is possible to confirm the improvement effect by the countermeasure against the malfunction (voltage drop countermeasure) without re-creating the chip 10b in step S140, the evaluation time can be shortened.

  If necessary, between the auxiliary power pads 44, 46, 48 and the power terminals 24, 26, 28 shown in FIG. 6, and between the auxiliary ground pads 41, 43, 47 and the ground terminals 21, 23, 27. Bonding may be applied.

(Second modification)
In the second modification of the embodiment of the present invention, an example in which power supply noise countermeasures are taken as a countermeasure against defects will be described. In the chip manufacturing method according to the second modified example, in step S103 of FIG. 5, the manufacturing unit 3 shown in FIG. 1 manufactures a chip 10c as shown in FIG. 10 as a power supply noise countermeasure chip. The chip 10c is different from the chip 10a shown in FIG. 2 in that the first circuit 111 and the second circuit 112 in the internal circuit 11 are separated from each other, the main ground pad 31 and the standby power supply pad 42 are The difference is that the main power pad 32 and the spare ground pad 41 are connected to the second circuit 112, connected to the first circuit 111.

  In step S110 of FIG. 5, for example, the power supply potentials VDD1 to VDD4 are supplied to the power supply terminals 22, 24, 26, and 28 using the inspection unit 4 shown in FIG. Are supplied with ground potentials VSS1 to VSS4, respectively, to inspect the electrical characteristics of the chip 10a. The inspection result is stored in the inspection result storage device 5. The defect determination means 101 reads the inspection result from the inspection result storage device 5 and determines whether there is a defect in the chip 10a. If it is determined that there is no defect, the process proceeds to step S104. On the other hand, if it is determined that there is a defect, the process proceeds to step S120, and the defect countermeasure unit 102 determines whether the defect is a power supply noise or another defect based on the inspection result. If the problem is power supply noise, the process proceeds to step S130.

  In step S130, power supply noise countermeasures are taken. For example, when the power supply noise between each of the power supply terminal 22 and the ground terminal 21 and the internal circuit 11 becomes a problem, the bonding apparatus (for example, the semiconductor manufacturing apparatus 301) is connected to the standby power supply pad 42 as shown in FIG. Bonding is performed between the power supply terminals 22 and between the auxiliary ground pad 41 and the ground terminal 21. As a result, the power supply can be separated from the bonding wires 91 and 99e and the bonding wires 92 and 99f with respect to the first circuit 111 and the second circuit 112, and power supply noise can be reduced. Although processing such as cutting of the wiring layer may be necessary in order to perform power source separation like the first circuit 111 and the second circuit 112 in the internal circuit 11 shown in FIG. It is effective as a possible countermeasure.

  According to the second modification of the embodiment of the present invention, only the bonding in step S130 is performed before the chip 10b is remade by correcting the wiring in steps S161 to S163 or the diffusion layer in steps S171 to S173. This makes it possible to take measures against malfunctions (measures against power supply noise). Therefore, the wiring correction time, the verification work time, the mask manufacturing time, and the chip manufacturing time associated with the mask correction are not required, and the cost of the above work can be suppressed. Furthermore, since it is possible to confirm the improvement effect by countermeasures against defects (measures against power supply noise) without recreating the chip 10b in step S140, the evaluation time can be shortened.

(Third Modification)
In the third modification of the embodiment of the present invention, ESD countermeasures, voltage drop countermeasures, and power supply noise countermeasures are taken as countermeasures against the problems. A chip manufacturing method according to the third modification will be described with reference to the flowchart of FIG. In step S101, at least one or more of the ESD countermeasure chip 10b shown in FIG. 2, the voltage drop countermeasure chip 10b shown in FIG. 8, and the power supply noise countermeasure chip 10b shown in FIG. Manufacture types.

  In step S110, the electrical characteristics of the chip are inspected. The defect determination unit 101 determines whether there is a defect based on the inspection result. If there is no defect, the process proceeds to step S104. On the other hand, if there is a problem, the process proceeds to step S120.

  In step S120, the defect countermeasure unit 102 classifies the type of defect according to the inspection result. If the defect type is classified as ESD, the process proceeds to step S121, and the presence / absence of the ESD countermeasure chip 10a is determined. If there is an ESD countermeasure chip 10a, the bonding apparatus performs the ESD countermeasure by performing bonding as shown in FIG.

  If the type of failure is classified as a voltage drop in step S120, the process proceeds to step S122, and the presence / absence of the chip 10b for voltage drop is determined. If there is a chip 10b for voltage drop countermeasures, the bonding apparatus takes measures for voltage drop by performing bonding as shown in FIG.

  If the type of failure is classified as power supply noise in step S120, the presence or absence of the power supply noise countermeasure chip 10b is determined in step S. If there is a voltage drop countermeasure chip 10b, the bonding apparatus As shown in FIG. 11, power supply noise countermeasures are taken by bonding.

  In step S <b> 140, the inspection unit 4 inspects the electrical characteristics of the chip after countermeasures against defects. The improvement confirmation unit 103 confirms whether the problem has been improved by the countermeasure based on the inspection result. If the problem is improved, the process proceeds to step S104. On the other hand, if the problem has not been improved, the process proceeds to step S150. Since other procedures are substantially the same as those of the embodiment of the present invention, the duplicate description is omitted.

  According to the third modified example of the embodiment of the present invention, it is possible to dynamically take countermeasures according to the type of defect. In addition, although the example which performs an ESD countermeasure, a voltage drop countermeasure, and a power supply noise countermeasure was demonstrated as a countermeasure against a malfunction, a malfunction countermeasure is not specifically limited. It is also possible to manufacture a chip capable of taking various countermeasures against external noise, EMI noise, etc., and take countermeasures against defects.

(Other embodiments)
As described above, the present invention has been described according to the embodiment. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art. For example, the ground terminal 23 and the spare ground pad 43 may be further connected to the chip 10a shown in FIG. 2 as shown in FIG. By connecting the ground terminal 23 and the spare ground pad 43, the ground terminal 23 and the ground terminal 25 are shared. As a result, since the wiring resistance is lowered, the current path can be further strengthened.

  Further, instead of the chip 10b shown in FIG. 4, for example, a plurality (two) of spare power supply wirings 81 and 83 and a plurality (two) of spare ground wirings 82, like a chip 10d shown in FIG. 84 may be arranged. Protection circuits 61 a, 61 c, 61 e, 61 f, 61 i, 61 j are connected to the backup power supply wiring 81 and the backup ground wiring 82. The protection circuits 61b, 61d, 61g, 61h, 61k, and 61l are connected to the standby power supply wiring 83 and the standby ground wiring 84. The power terminals 22 and 24 and the spare power pads 42 and 44 are connected by bonding wires 99h and 99i, and the ground terminals 25 and 27 and the spare ground pads 35 and 37 are connected by bonding wires 99j and 99k. According to the chip 10 d shown in FIG. 14, the current path can be further strengthened by using the plurality of spare power supply wires 81 and 83 and the spare ground wires 82 and 84.

  In addition, the chips 10a to 10c including the four power supply terminals 22, 24, 26, and 28 and the ground terminals 21, 23, 25, and 27 have been described. Power terminal, ground terminal and signal terminal. As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

It is a block diagram showing an example of a semiconductor manufacturing system concerning an embodiment of the invention. It is a block diagram which shows an example of the chip | tip before ESD countermeasure which concerns on embodiment of this invention. It is a block diagram which shows an example of the electrostatic breakdown protection circuit which concerns on embodiment of this invention. It is a block diagram explaining ESD generation of the chip before ESD countermeasure according to the embodiment of the present invention. It is a block diagram which shows an example of the chip | tip after ESD countermeasures concerning embodiment of this invention. It is a flowchart for demonstrating an example of the malfunction countermeasure method of the chip | tip which concerns on embodiment of this invention. It is a flowchart for demonstrating an example of the chip manufacturing process which concerns on embodiment of this invention. It is a block diagram which shows an example of the chip | tip before the ESD countermeasure which concerns on the 1st modification of embodiment of this invention. It is a block diagram which shows an example of the chip | tip after ESD countermeasures concerning the 1st modification of embodiment of this invention. It is a block diagram which shows an example of the chip | tip before the ESD countermeasure which concerns on the 2nd modification of embodiment of this invention. It is a block diagram which shows an example of the chip | tip after ESD countermeasures concerning the 2nd modification of embodiment of this invention. It is a flowchart for demonstrating an example of the malfunction countermeasure method of the chip | tip which concerns on the 3rd modification of embodiment of this invention. It is a block diagram which shows an example of the chip | tip after ESD countermeasure which concerns on other embodiment of this invention. It is a block diagram which shows another example of the chip | tip after ESD countermeasure which concerns on other embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Design part 2 ... Mask production part 3 ... Manufacturing part 4 ... Inspection part 5 ... Inspection result memory | storage device 6 ... Main memory 7 ... Program memory | storage device 8 ... Input device 9 ... Output device 10 ... Defect countermeasure part 10a-10d ... Chips 11-14 ... Internal circuit 20 ... Lead frame 21, 23, 25, 27 ... Ground terminals 22, 24, 26, 28 ... Power supply terminals 31, 33, 35, 37 ... Main ground pads 32, 34, 36, 38 ... Main power pad 35 ... Main ground pad 41 ... Spare ground pad 41,43,45,47 ... Spare ground pad 42 ... Spare power pad 42,44,46,48 ... Spare power pad 43 ... Spare ground pad 45 ... Spare ground pad 60a to 60p ... main protection circuit 61a to 61l ... preliminary protection circuit 101 ... failure determination means 102 ... failure countermeasure means 103 ... improvement confirmation means 104 ... correction Law determining means 111: first circuit 112: second circuit

Claims (5)

An internal circuit; a main power pad connected to the power terminal and the internal circuit; a main ground pad connected to the ground terminal and the internal circuit; A malfunction countermeasure system for performing malfunction countermeasures on a chip including a spare power supply pad disposed adjacent to the main power pad and a spare ground pad disposed adjacent to the main ground pad;
An inspection unit for inspecting the electrical characteristics of the chip by supplying a power supply potential and a ground potential to the power supply terminal and the ground terminal;
Failure determination means for determining the presence or absence of a failure of the chip based on the result of the inspection;
A failure countermeasure system comprising: a bonding device that bonds the spare power pad and the power terminal, and the spare ground pad and the ground terminal when it is determined that there is the malfunction.   The defect countermeasure system according to claim 1, further comprising an improvement confirmation unit that confirms whether or not the defect is improved by bonding by the bonding apparatus.   The chip further includes a main protection circuit connected between the main power pad and the main ground pad, and a spare protection circuit connected between the spare power pad and the spare ground pad. The malfunction countermeasure system according to claim 1 or 2. An internal circuit, a main power pad and a main ground pad connected to the internal circuit, a spare power pad disposed adjacent to the main power pad, and a spare ground pad disposed adjacent to the main ground pad A step of manufacturing a chip comprising:
Mounting the chip on a lead frame having a power terminal and a ground terminal;
Bonding the main power pad and the power terminal, and the main ground pad and the ground terminal;
Supplying a power supply potential and a ground potential to the power supply terminal and the ground terminal to inspect electrical characteristics of the chip;
Determining the presence or absence of defects of the chip based on the result of the inspection;
If it is determined that there is a defect, a chip defect countermeasure method including the step of bonding the spare power pad and the power terminal, and the spare ground pad and the ground terminal. A chip mounted on a lead frame having a power terminal and a ground terminal,
Internal circuitry,
A main power pad connected to the power terminal and the internal circuit;
A main ground pad connected to the ground terminal and the internal circuit;
A main protection circuit connected between the main power pad and the main ground pad;
A spare power pad disposed adjacent to the main power pad and connected to the power terminal;
A spare ground pad disposed adjacent to the main ground pad and connected to the ground terminal;
A chip comprising: a backup protection circuit connected between the backup power pad and the backup ground pad.

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