JP2006323695A - Computer device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a computer device for reducing a delay time in the processing system of an instruction code whose reading from a built-in memory is required at a high speed when realizing an ECC function for reading the instruction code from the memory. <P>SOLUTION: General data having 16 bit length and a high speed non-requirement instruction code are added with parity 5 bits, and a high speed requirement instruction code having 12 bit length is added with parity 9 bits in the form of "4+parity 3 bits"×3, and stored in a built-in memory 2. A conventional type ECC circuit 4 which is generally used is applied to the bit string of "16+parity 5 bits", and an error correction/decoder 14 in which the number of passing stages is reduced is applied to the bit string of "4+parity 3 bits"×3 by sharing error correction and decoding as post-correction processing. Thus, it is possible to read the high speed requirement instruction code from the built-in memory by reducing a delay time. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a computer apparatus, and more particularly to a computer apparatus that realizes an ECC (Error Check and Correct) function when reading from a built-in memory.

  In order to realize the ECC function at the time of reading from the built-in memory, the parity bit is added to the built-in memory and the error correction encoded data is stored. For example, in Patent Document 1, the parity bit is added. Thus, a semiconductor memory device with an ECC function is disclosed which has a function of writing error correction encoded data into a memory cell array and a function of correcting data read from the memory cell array when there is an error.

JP 2005-85357 A

  By the way, in addition to general data, an instruction code is also stored in the built-in memory used by the computer device. The instruction code includes an instruction code that needs to be read from the memory as soon as possible (for example, an instruction code that takes time for processing such as an addition instruction), while the general data that is executed following the reading of the instruction code, An instruction code with a short processing time (for example, a logical operation instruction code) does not need to be read out quickly.

  However, in the technique described in the above document, since all data read from the memory is subjected to error correction processing by the same ECC circuit (error correction circuit), the technique described in the above document is read from the built-in memory. Sometimes applied to a computer device that realizes the ECC function, error codes are processed by the same ECC circuit without distinguishing between general data and instruction codes, so that instruction codes that need to be read out quickly are output with the same delay time as general data Will be. In this case, the ECC circuit is composed of a multi-stage logic circuit including an exclusive OR circuit as shown in the above-mentioned document, so that it is difficult to shorten the delay time.

  Therefore, in a computer device that realizes the ECC function when reading from the built-in memory, error correction processing performed when reading from the built-in memory is performed separately for general data and instruction codes, and error correction processing on the instruction code side is performed using general data. It is necessary to make the error correction process faster than the error correction process on the side, but how to implement the error correction process on the instruction code side with a short delay time is a problem.

  The present invention has been made in view of the above, and aims to reduce a delay time in a processing system of an instruction code that needs to be read from the memory at a high speed when the ECC function is realized at the time of reading from the built-in memory. An object is to obtain a computer apparatus.

  To achieve the above object, the present invention provides a first bit length plus a first parity bit to which a first parity bit for the entire data bit string having the first bit length is added. 1 bit string and a second bit string obtained by adding a second parity bit to a second instruction code having a second bit length shorter than the first bit length, wherein the second bit length is A built-in memory for storing a unit bit length obtained by adding the second parity bit for each unit bit length divided into a plurality of units + a second bit string having a predetermined number of second parity bits as a set; An error correction circuit that performs error correction on the first bit string read from the built-in memory, and a decoding that is a process after error correction and correction for the second bit string read from the built-in memory. Characterized by comprising an error correction decoder for performing in parallel and.

  According to the present invention, the built-in memory includes a data bit string having a first bit length (mainly general data) and an instruction code (mainly high-speed instruction code) in the form of error correction encoding. Are stored differently, a commonly used error correction circuit is applied to the first bit string including the data bit string, and error correction and correction are applied to the second bit string including the instruction code. An error correction / decoder with a reduced number of via stages is used in common with the decoding process. As a result, instruction codes can be obtained in the process of error correction with a small number of transit stages without going through multiple stages of logic gates, so that instruction codes that require high-speed reading can be read from the built-in memory with a short delay time. Can do.

  According to the present invention, when the ECC function is realized at the time of reading from the built-in memory, it is possible to obtain a computer device that can reduce the delay time in the processing system of the instruction code that needs to be read from the memory at high speed. Play.

  Exemplary embodiments of a computer apparatus according to the present invention will be described below in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a computer apparatus according to an embodiment of the present invention. In FIG. 1, a CPU 1 that is a main element of a computer apparatus includes a general-purpose register 11 and an ALU (arithmetic unit) 12. A high-speed unnecessary instruction decoder 13 that decodes an instruction code that does not require high-speed reading (hereinafter referred to as “high-speed unnecessary”), an ECC / decoder 14, and a selector 15 are added to the CPU 1.

  The built-in memory 2 used by the CPU 1 is a memory capable of writing and reading in units of 21 bits, for example. The built-in memory 2 includes an address bus / control signal port 2a to which an address bus / control signal line of the CPU 1 is connected, a data input port 2b for performing 21-bit data input / output, and a data output port 2c.

  A parity generation circuit 3 and a conventional ECC circuit 4 are provided between the CPU 1 and the built-in memory 2. The write data string output by the CPU 1 is input to the data input port 2 b and the parity generation circuit 3 of the built-in memory 2. The parity generation circuit 3 performs a logical operation of adding a parity bit to the write data string output from the CPU 1 and outputs the determined number of parity bits to the data input port 2 b of the built-in memory 2.

  The write data string output from the CPU 1 to the built-in memory 2 is the contents of the general-purpose register 11. In this embodiment, the write data string is composed of a 16-bit configuration and a 12-bit configuration. The 16-bit data string is applied to general data and an instruction code not requiring high speed. The 12-bit data string is applied to an instruction code that requires high-speed reading (hereinafter referred to as “high-speed required”).

  In this embodiment, the CPU 1 writes the instruction code in the built-in memory 2. However, depending on the nature of the built-in memory 2 such as using a mask ROM or EEPROM in the built-in memory 2, the instruction code is directly written from the outside. Sometimes it is.

  When the write data string output from the CPU 1 has a 16-bit configuration, the parity generation circuit 3 calculates 5 bits of parity for the entire 16 bits, and uses the 5 bits of parity for the data input port 2b of the built-in memory 2 Output to. When the write data string output by the CPU 1 has a 12-bit configuration, 9 bits of parity calculated by a method described later is output to the data input port 2 b of the built-in memory 2.

  In short, the built-in memory 2 stores in a 21-bit configuration in which parity is added to the write data sequence, but in this embodiment, the data sequence output by the CPU 1 has a 16-bit configuration and 5 bits of parity is added to it. The high-speed unnecessary instruction code is stored in the format of data bit 16 + parity 5 bits, whereas the high-speed instruction code in which the data string has a 12-bit configuration and a parity of 9 bits is added to “data 4 bits”. It is stored in the format of 7 bits × 3 of “+ parity 3 bits”.

  The conventional ECC circuit 4 is a commonly used ECC circuit (error correction circuit). For example, an ECC circuit disclosed in Patent Document 1 can also be used. Of the 21-bit data string output from the data output port 2b of the built-in memory 2, the conventional ECC circuit 4 receives a data string of data 16 bits + parity 5 bits (see FIG. 2 (1)). ). That is, general data and a high-speed unnecessary instruction code are input to the conventional ECC circuit 4. The 16-bit general data error-corrected by the conventional ECC circuit 4 is output to the general-purpose register 11, and the error-corrected 16-bit high-speed unnecessary instruction code is input to the high-speed unnecessary instruction decoder 13.

  The high-speed unnecessary instruction decoder 13 performs two systems of decoding output for selecting the general-purpose register 11 and the ALU 12. In FIG. 1, 32 bits (16 bits + 16 bits) are output to the selector 15 and 2 bits are output to the ALU 12.

  On the other hand, in the ECC decoder 14, among the 21-bit data string output from the data output port 2 b of the internal memory 2, data 12 bits + parity 9 bits (“data 4 bits + parity 3 bits” 7 bits × 3) (see FIG. 2 (2)) is input. That is, the ECC / decoder 14 is inputted with a high-speed instruction code.

  The ECC / decoder 14 is an integrated configuration of a circuit portion for error correction (high-speed ECC circuit 14a) and a decoder (high-speed instruction decoder 14b) which is a part of the corrected data processing circuit. In FIG. 1, for ease of understanding, the high-speed ECC circuit 14a corresponding to the conventional ECC circuit 4 and the high-speed instruction decoder 14b corresponding to the high-speed unnecessary instruction decoder 13 are shown in blocks. In fact, they cannot be distinguished (see FIGS. 3 to 6).

  The ECC / decoder 14 performs decoding output of two systems for selecting the general-purpose register 11 and the ALU 12. In FIG. 1, 32 bits (16 bits + 16 bits) are output to the selector, 15 bits are output to the ALU 12, and 1 bit is output to the selector 15.

  The selector 15 uses 1 bit from the ECC decoder 14 as a selection command, 32 bits (16 bits + 16 bits) to the general register 11 output from the ECC decoder 14, and the general register 11 output from the high-speed unnecessary instruction decoder 13. One of 32 bits (16 bits + 16 bits) is selected and given to the general-purpose register 11.

  Next, with reference to FIG. 2, the bit configuration of the high-speed unnecessary instruction code and the high-speed required instruction code written to and read from the internal memory 2 will be described. This is also a diagram for explaining the operation of the parity generation circuit 3.

  FIG. 2A is a diagram showing a configuration example of input bits to the high-speed unnecessary instruction decoder. When the parity generation circuit 3 receives the output notification of the high-speed unnecessary instruction code from the CPU 1, the parity generation circuit 3 performs a logical operation on all the 16 bits (D0 to D15) output from the CPU 1 and sets the 5-bit parity bits D16 to D20. Generate. In this case, in the 16-bit high-speed unnecessary instruction code output from the CPU 1, a logical value for setting the parity 5 bits to zero is set in the bits D4 to D6, D11, and D12. That is, in the 21-bit high-speed unnecessary instruction code input from the built-in memory 2 to the conventional ECC circuit 4, all the bits D16 to D20 are “0”.

  When the high-speed unnecessary instruction decoder 13 receives the 16-bit (bits D0 to D15) high-speed unnecessary instruction code shown in FIG. 2 (1) after error correction from the conventional ECC circuit 4, the high-speed unnecessary instruction decoder 13 receives 5 bits of bits D7 to D10. Are used for general purpose register (source 1) selection, 4 bits D0 to D3 are used for general purpose register (source 2 / destination) selection, and bit D13 is used for instruction selection.

  FIG. 2 (2) is a diagram showing a configuration example of input bits to the ECC / decoder 14. Since the ECC / decoder 14 performs a processing operation in units of 7 bits as will be described later, the parity generation circuit 3 receives the output notification of the high-speed instruction code from the CPU 1 and converts the 12-bit data output by the CPU 1 to “ D4 to D3, D7 to D10, and D14 to D17 are divided in 4-bit units, and logical operations are performed on each 4-bit data bit to generate 3-bit parity bits “D4 to D6” and “D11 to D13”. “D18 to D20” are generated. As a result, the ECC / decoder 14 receives a 21-bit high-speed instruction code from the built-in memory 2 in a combination of “D0 to D6”, “D7 to D13”, and “D14 to D20”.

  In this case, the parity generation circuit 3 obtains each 3 bits of parity bits for a 12-bit high-speed instruction code as follows. In other words, if “^” is an exclusive OR symbol, “D4 to D6” performs an operation of D4 = D0 ^ D1 ^ D3, D5 = D0 ^ D2 ^ D3, and D6 = D1 ^ D2 ^ D3. To generate. “D11 to D13” are generated by performing an operation of D11 = D7 ^ D8 ^ D10, D12 = D7 ^ D9 ^ D10, and D6 = D8 ^ D9 ^ D10. “D18 to D20” are generated by performing an operation of D18 = D14 ^ D15 ^ D17, D19 = D14 ^ D16 ^ D17, and D20 = D15 ^ D16 ^ D17.

  The ECC decoder 14 uses 7 bits of bits D0 to D6 for selecting a general purpose register (source 2 / destination), 7 bits of bits D7 to D13 are used for selecting a general purpose register (source 1), and bits D14 to The 7 bits of D21 are used for instruction selection. Then, 1 bit out of 16 bits obtained by decoding 7 bits (bits D14 to D21) for instruction selection is output to the selector 15. When bits D17 to D14 are all “0”, bits D20 to D18 are all “0”. In this case, the output of the high-speed unnecessary instruction decoder 13 is selected and applied to the general-purpose register 11. In other cases, the output of the ECC decoder 14 is selected and applied to the general-purpose register 11.

  FIG. 3 is a diagram for explaining a functional configuration of the ECC / decoder 14 shown in FIG. As can be understood from the bit configuration shown in FIG. 2 (2), the ECC decoder 14 is functionally composed of three 7 to 16 decoders 31, 32, and 33 that decode 7 bits of 4 bits of data + 3 bits of parity into 16 bits. It consists of a decoder.

  In the 7to16 decoder 31, bits D14 to D21 are input as data bits D0 to D3 and parity bits P0 to P2 as A to G inputs, and 16 bits Y00 to Y15 are output as an instruction selection signal. Of these, 15 bits are provided to the ALU 12 and 1 bit is provided to the selector 15.

  The 7 to 16 decoder 32 receives bits D7 to D13 as data bits D0 to D3 and parity bits P0 to P2 as A to G inputs, and 16 bits Y00 to Y15 to the selector 15 as a general-purpose register selection signal (source 1). Is output.

  The 7to16 decoder 33 receives bits D0 to D6 as data bits D0 to D3 and parity bits P0 to P2 as A to G inputs, and 16 bits Y00 to Y15 as a general-purpose register selection signal (source 2 / destination). It is output to the selector 15.

  FIG. 4A is a diagram illustrating a 3to8 decoder that constitutes an input stage of the 7to16 decoder illustrated in FIG. 3. FIG. 4B is a diagram of an R decoder constituting the output stage of the 7to16 decoder shown in FIG.

The three 7to16 decoders 31, 32, and 33 shown in FIG. 3 are integrally configured, and the input stage is composed of seven 3to8 decoders 41a to 41g as shown in FIG. As shown in FIG. 4B, it is composed of 16 R decoders 42 _{00 to} 42 ₁₅ .

  4A, among the 7-bit signals A to G, 3 bits of EFG are applied to the input terminals X1, X2, and X3 of the 3to8 decoder 41a, and 8 bits of EFG0 to EFG7 decoded from the output terminals Y0 to Y7. A signal is output. The 3 bits of AFG are applied to the input terminals X1, X2, and X3 of the 3to8 decoder 41b, and decoded 8-bit signals of AFG0 to AFG7 are output from the output terminals Y0 to Y7. The 3 bits of ABG are applied to the input terminals X1, X2, and X3 of the 3to8 decoder 41c, and decoded 8-bit signals of ABG0 to ABG7 are output from the output terminals Y0 to Y7. The 3 bits of ABC are applied to the input terminals X1, X2, and X3 of the 3to8 decoder 41d, and decoded 8-bit signals of ABC0 to ABC7 are output from the output terminals Y0 to Y7. The 3 bits of BCD are applied to the input terminals X1, X2, and X3 of the 3to8 decoder 41e, and decoded 8-bit signals of BCD0 to BCD7 are output from the output terminals Y0 to Y7. The 3 bits of CDE are applied to the input terminals X1, X2, and X3 of the 3to8 decoder 41f, and decoded 8-bit signals of CDE0 to CDE7 are output from the output terminals Y0 to Y7. The 3 bits of DEF are applied to the input terminals X1, X2, and X3 of the 3to8 decoder 41g, and decoded 8-bit signals of DEF0 to DEF7 are output from the output terminals Y0 to Y7.

In FIG. 4B, the 16 R decoders 42 _{00 to} 42 ₁₅ have 14 input terminals “A0, A1, B0, B1, C0, C1, D0, D1, E0, E1, F0, F1, G0, G1 ”and one output end Y. At the 14 input terminals, the output bits excluding the A bit signal among the output bits of the seven 3to8 decoders 41a to 41g are input to the input terminals “A0, A1”, and the output bits excluding the B bit signal. The bits are input to the input terminals “B0, B1”, the output bits excluding the C bit signal are input to the input terminals “C0, C1”, and the output bits excluding the D bit signal are input to the input terminals “D0, D1”. Input, output bits excluding the E bit signal are input to the input terminals “E0, E1”, output bits excluding the F bit signal are input to the input terminals “F0, F1”, and the output excluding the G bit signal Bits are input to the input terminals “G0, G1”.

  Next, the seven 3to8 decoders 41a to 41g shown in FIG. 4A are configured as shown in FIG. 5, for example. In FIG. 5, the data bit applied to the input terminal X1 is inverted by the inverter circuit 52 to become one input of the NAND circuits 57 and 59, and further inverted by the inverter circuit 55 to be one of the NAND circuits 56 and 58. Input. The data bit applied to the input terminal X2 is inverted by the inverter circuit 51 and becomes the other input of the NAND circuits 58 and 59, and further inverted by the inverter circuit 54 and becomes the other input of the NAND circuits 56 and 57. .

  The output of the NAND circuit 59 is applied to one input terminal of AND circuits 63 and 67 with inverters operating as a NOR circuit. The output of the NAND circuit 58 is applied to one input terminal of AND circuits 62 and 66 with inverters that operate as a NOR circuit. The output of the NAND circuit 57 is applied to one input terminal of AND circuits 61 and 65 with inverters that operate as a NOR circuit. The output of the NAND circuit 56 is applied to one input terminal of AND circuits 60 and 64 with inverters that operate as a NOR circuit.

  The data bit applied to the input terminal X3 is inverted by the inverter circuit 50 and applied to the other input terminal of the AND circuits 60, 61, 62, 63 with inverter, and further inverted by the inverter circuit 53 with the inverter. It is applied to the other input terminal of the AND circuits 64, 65, 66 and 67. As a result, 3-bit input decoding results (Y0 to Y7) are obtained at the outputs of the eight AND circuits 67 to 60 with inverters.

Next, the 16 R decoders 42 _{00 to} 42 ₁₅ shown in FIG. 4B are configured as shown in FIG. 6, for example. In FIG. 6, the 2-bit data applied to the input terminals A0 and A1 becomes one input of the NOR circuit 78 via the AND circuit 70, and the 2-bit data applied to the input terminals B0 and B1 is the AND circuit 71. And the other input of the NOR circuit 78. The 2-bit data applied to the input terminals C0 and C1 becomes one input of the NOR circuit 79 via the AND circuit 72, and the 2-bit data applied to the input terminals D0 and D1 is NORed via the AND circuit 73. This is the other input of the circuit 79. The outputs of the NOR circuits 78 and 79 become one input of the NOR 84 via an OR circuit 81 with an inverter that operates as a NAND circuit.

  The 2-bit data applied to the input terminals E0 and E1 becomes one input of the NOR circuit 80 via the AND circuit 74, and the 2-bit data applied to the input terminals F0 and F1 is NORed via the AND circuit 75. This is the other input of the circuit 80. The output of the NOR circuit 80 is input to the inverter terminal of the OR circuit 83. The bit data applied to the input terminal G0 is inverted by the inverter circuit 76 and becomes one input of an AND circuit 82 with an inverter that operates as a NOR circuit. The bit data applied to the input terminal G1 is inverted by the inverter circuit 77 and becomes the other input of the AND circuit 82 with the inverter. The output of the AND circuit 82 with the inverter is input to the non-inverter terminal of the OR circuit 83. The output of the OR circuit 83 becomes the other input of the NOR 84. As a result, one bit data Y selected from the 14 input bit data is obtained at the output of the NOR 84.

  Next, the operation will be described. In the conventional ECC circuit 4, error correction is performed on 21-bit data composed of 16 bits of data and 5 bits of parity, which is read from the built-in memory 2, and data bits D20 to D16 (parity 5 bits) in FIG. Data bits D15 to D0 when all are "0" are given to the high-speed unnecessary instruction decoder 13, and 16 bits of general data whose data bits D20 to D16 (parity 5 bits) are all other than "0" are general purpose registers 11. Given to.

  The high-speed unnecessary instruction decoder 13 outputs “16 bits + 16 bits” in the selection of the general-purpose register 11 in FIG. 1, but the high-speed unnecessary instruction code is the data bit D15 = D14 = “0” in FIG. ”And the data bits D12, D11, D6 to D4 marked“ x ”are special data bits. Therefore, the high-speed unnecessary instruction decoder 13 actually decodes 4 bits of data bits D10 to D7 and outputs an 8-bit general-purpose register selection signal (source 1), and decodes 4 bits of data bits D3 to D0. Then, an 8-bit general-purpose register selection signal (source 2 / destination) is output. Then, a 2-bit instruction selection signal obtained by decoding the data bit D13 is output to the ALU 12.

  On the other hand, the ECC / decoder 14 enables the error correction for the 12-bit instruction code requiring high speed and the decoding, which is the data processing after the correction, to be performed in parallel by the above-described configuration, thereby reducing the delay time. It is possible. This will be specifically described below.

As described in FIG. 2B, among the inputs A to G of the three decoders 7 to 16 decoders 31 to 33 shown in FIG. 3, the inputs E to G are arbitrary data bits A to D (D0 to D0). D3) are parity bits P0 to P2 generated by performing an operation of E = A ^ B ^ D, F = A ^ C ^ D, and G = B ^ C ^ D. Therefore, in this example, 2 ⁴ = 16 types of instruction codes without error can be created in total. In this way, the 1-bit error instruction code does not match the other 15 types of error-free instruction codes and the 1-bit error instruction codes. The original error-free instruction code can be identified from a certain instruction code.

  The ECC / decoder 14 performs 7 to 16 decoding in units of 7 bits of such data 4 bits + parity 3 bits. In general, for example, in a 4to16 decoding, a configuration is adopted in which 4 bits of data are input as they are to 16 4-input AND circuits or 4 bits of inverted data are input and their outputs are ORed.

  If 7 to 16 decoding by the ECC decoder 14 is performed with the same configuration, the output is not enabled when one of the inputs A to G has an error. Therefore, for example, assuming that there is an error in input A, a configuration is adopted in which 6 inputs (B to G) ignoring input A are input to the AND circuit as they are or after being inverted. The same applies to the inputs B to G.

  In short, in the 7 to 16 decoding by the ECC decoder 14, an AND is applied to seven types of six inputs ignoring one input of the inputs A to G (or inverted A to G) so that any of these cases can be handled. It takes a configuration that takes a 7-input OR. In addition, the number of gate stages is reduced.

  Specifically, the 6-input AND is composed of two 3-input ANDs (FIG. 5) and one 2-input AND shown in the input stage of FIG. 80, 81 to 84. Then, combinations of two three-input ANDs (FIG. 5) are combined so that seven types of six-input ANDs ignoring one input of inputs A to G (or inverted A to G) can be configured. As shown in 3 inputs in 1, it is determined not to overlap.

As a result, decode signals ignoring 1-bit errors of the inputs A to G are output to the outputs Y00 to Y15 of the 16 R decoders 42 _{00 to} 42 ₁₅ shown in FIG. Will be output.

  In the conventional ECC circuit 4 and the high-speed unnecessary instruction decoder 13, as shown in, for example, Patent Document 1, gates of 10 stages or more are provided from when the read data of the built-in memory 2 is input to when a decoded output is obtained. Need to pass.

  On the other hand, in the ECC / decoder 14 according to this embodiment, the read data of the built-in memory 2 is inputted and the decode output is obtained. Since it passes through NOR stages 60 to 67 and the R decoder (FIG. 5) passes through one composite gate stage of 70 and 78, one NAND stage of 81 and one NOR stage of 84, for convenience, only five gate stages are required, and delay. Time can be saved.

  As described above, according to this embodiment, when the ECC function is realized at the time of reading from the built-in memory, an instruction code that requires high-speed reading and an instruction code that does not require high-speed reading are mistaken in the built-in memory. For instruction codes that need to be stored in different correction encoding formats and require high-speed reading, error correction and subsequent decoding, which is part of the processing system, are shared, reducing delay time. You can plan.

  In this embodiment, the case where the instruction code not requiring high-speed reading is stored together with the general data in the built-in memory has been described. However, the instruction code not requiring high-speed reading may not exist. In that case, the high-speed unnecessary instruction decoder and the selector may be unnecessary.

  The general-purpose register selection signal (source 2 / destination) may be divided into a general-purpose register selection signal (source 2) and a general-purpose register selection signal (destination). Therefore, the present invention can be applied.

  As described above, the computer apparatus according to the present invention is useful for reducing the delay time in the ECC processing of the instruction code that requires high-speed reading when the ECC function is realized at the time of reading from the built-in memory. .

It is a block diagram which shows the structure of the computer apparatus by one embodiment of this invention. It is a figure explaining the structural example of each input bit of the high-speed unnecessary instruction decoder and ECC decoder shown in FIG. It is a figure explaining the functional structure of the ECC decoder shown in FIG. It is a figure which shows the 3to8 decoder which comprises the input stage of the 7to16 decoder shown in FIG. It is a figure which shows R decoder which comprises the output stage of 7 to 16 decoder shown in FIG. FIG. 4 is a diagram showing a circuit configuration of a 3to8 decoder shown in FIG. FIG. 4 is a diagram showing a circuit configuration of an R decoder shown in FIG. 4-2.

Explanation of symbols

1 CPU (computer device)
2 Built-in memory 3 Parity generation circuit 4 Conventional ECC circuit 11 General-purpose register 12 ALU (arithmetic unit)
13 Fast unnecessary instruction decoder 14 ECC · decoder 14a fast type ECC circuit 14b fast main instruction decoder 15 selectors 31 to 33 7To16 decoder 41 a to 41 g 3-to-8 decoder 42 ₀₀ through 42 ₁₅ R decoder 50～55,76,77 inverter circuit 56-59 NAND circuit 60 to 67, 82 AND circuit with inverter (NOR circuit)
70 to 76 AND circuit 78 to 80, 84 NOR circuit 81 OR circuit with inverter (NAND circuit)
83 OR circuit with single-ended inverter

Claims (5)

A first bit string consisting of a first bit length plus a first parity bit to which a first parity bit for the entire data bit string having the first bit length is added, and a length greater than the first bit length. A second bit string in which a second parity bit is added to an instruction code having a short second bit length, and the second parity bit for each unit bit length obtained by dividing the second bit length into a plurality of unit bits A built-in memory for storing a unit bit length added with a second bit string consisting of a predetermined number of second parity bits as a set;
An error correction circuit that performs error correction on the first bit string read from the internal memory;
An error correction / decoder that performs error correction and decoding, which is processing after correction, in parallel with respect to the second bit string read from the internal memory;
A computer apparatus comprising: The first bit length plus the first parity bit obtained by adding the first parity bit for the entire first bit length to the general data having the first bit length and the first instruction code. 1 bit string and a second bit string obtained by adding a second parity bit to a second instruction code having a second bit length shorter than the first bit length, wherein the second bit length is A built-in memory for storing a unit bit length obtained by adding the second parity bit for each unit bit length divided into a plurality of units + a second bit string having a predetermined number of second parity bits as a set;
An error correction circuit that performs error correction on the first bit string read from the internal memory;
An instruction decoder for decoding the first instruction code corrected by the error correction circuit;
An error correction / decoder that performs error correction and decoding, which is processing after correction, in parallel with respect to the second bit string read from the internal memory;
A selector that selects one of the general-purpose register selection signal output from the instruction decoder and the general-purpose register selection signal output from the error correction / decoder and supplies the general-purpose register;
A computer apparatus comprising: The error correction decoder is
For each of the set in the second bit string, there is provided a circuit that performs an OR of bit data excluding one of the set of input bits or an inverted bit data of the bit data. ,
The computer apparatus according to claim 1, wherein the computer apparatus is configured as a circuit that decodes each set of bit lengths to the first bit length using a circuit that takes an OR of the ANDs.   4. The computer apparatus according to claim 3, wherein the error correction / decoder outputs an instruction selection signal and a general-purpose register selection signal that are decoded in accordance with the assignment of the second bit string to each set. 5. The computer apparatus according to claim 4, wherein the selector performs a selection operation using a part of the instruction selection signal output from the error correction / decoder.

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