JP2006320194A - Power-supply circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power-supply circuit with a high efficiency using charge pump circuit as in the case that a DC power source is a battery, even if a supply voltage decreases gradually as it is consumed, capable of obtaining a substantially constant output voltage, and eliminating loss caused by a forward voltage of a blocking diode, and capable of preventing a reactive current caused by a parasitic diode of a MOS transistor, even if ICs are increasingly adopted, and preventing the generation of latch-up. <P>SOLUTION: A power-supply circuit includes a charge pump circuit 3 for performing three modes of boosting operations, i.e. a first operation mode for performing one-fold boosting, a second operation mode for performing 1.5 times boosting and a third operation mode for performing twice boosting, in relation to an output voltage Vo from a constant voltage circuit 2. The charge pump circuit 3 is designed to perform operation, in one of the first operation mode, the second operation mode, or the third operation mode, depending on the voltage value of a supply voltage VDD. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a power supply circuit using a charge pump circuit, and more particularly to a power supply circuit that can supply power efficiently to a load that requires a voltage slightly higher than a power supply voltage.

  Conventionally, when a voltage higher than the power supply voltage is required, a DC-DC converter mainly using an inductance is used as a power supply circuit. The DC-DC converter can generate an arbitrary voltage, and can efficiently supply power to a load with large current consumption, and thus is used in many applications. However, since the DC-DC converter requires components such as a transformer and a coil, it is difficult to reduce the size, and the DC-DC converter cannot be integrated in a semiconductor integrated circuit.

  Therefore, when power is supplied to a load having a relatively small current consumption, a charge pump circuit that can be reduced in size and is highly efficient is used for the power supply circuit. However, since the charge pump circuit adds and boosts the voltage of the capacitor charged with the power supply voltage from the DC power supply, the output voltage can only be obtained as an integer multiple of the power supply voltage, and the power supply voltage and load are required. Depending on the voltage relationship, an unnecessarily high voltage may be supplied to the load, resulting in an increase in power consumption of the load and a significant reduction in efficiency.

  In view of this, a charge pump circuit has been disclosed in which the disadvantage of such a charge pump circuit, in which only an output voltage that is an integral multiple of the power supply voltage is obtained, has been improved (see, for example, Patent Document 1). In the charge pump circuit, two capacitors having the same capacity are used as capacitors closest to the power supply, and the two capacitors are connected in series and charged with the power supply voltage. Charged to a voltage of / 2.

The voltage obtained by connecting the two capacitors charged in parallel in this way is added to the voltage of the other capacitor or the power supply voltage charged to the same voltage as the power supply voltage, so that (N + 0 .5) A double voltage is obtained. N is an integer of N> 0. Furthermore, a circuit is disclosed in which the output voltage can be set for each 1/4 step of the power supply voltage by adding four capacitors that are closest to the power supply and adding the voltages of the four capacitors connected in parallel as described above. (For example, refer to Patent Document 1).
JP 2001-169537 A

  However, although the output voltage can be boosted with a fineness of 1/4 step of the power supply voltage, the boosting ratio cannot be changed with respect to the power supply voltage. For this reason, for example, when the power supply voltage fluctuates greatly, it is necessary to set the boosting ratio with respect to the lowest power supply voltage, and there is a problem that the efficiency is low at the highest power supply voltage. In addition, since a diode is used to prevent backflow from the high voltage side, there is a problem that a loss due to the forward voltage of the diode occurs.

  Further, an N-channel MOS transistor having a back gate connected to the source is used as a switching element in which flyback capacitors are connected in series. Therefore, when these circuits are integrated, if the source voltage of the N-channel MOS transistor becomes higher than the drain voltage during the boosting operation by the charge pump circuit, the forward direction is applied to the parasitic diode of the N-channel MOS transistor. Current flows. As a result, a reactive current flows between the power supply voltage and the ground voltage, and in the worst case, a latch-up phenomenon occurs and the IC generates heat, which may cause a malfunction.

  The present invention has been made to solve such a problem. Even when the power supply voltage gradually decreases with use, as in the case where the DC power supply is a battery, the output is almost constant. A voltage is obtained, loss due to the forward voltage of the diode for preventing backflow is eliminated, and generation of reactive current due to the parasitic diode of the MOS transistor can be prevented and latch-up can be prevented even if it is made into an IC. An object is to obtain a highly efficient power supply circuit using a charge pump circuit.

  The power supply circuit according to the present invention includes a constant voltage circuit that generates and outputs a predetermined constant voltage Va from a power supply voltage supplied from a DC power supply, and a constant corresponding to the voltage value of the power supply voltage. A charge pump circuit that boosts the output voltage and supplies it as a power source for a load, wherein the charge pump circuit performs voltage detection of the power supply voltage and increases the boosting factor in response to a decrease in the power supply voltage value. It boosts the output voltage of the constant voltage circuit.

  In this case, the charge pump circuit outputs a first operation mode for outputting the output voltage of the constant voltage circuit as it is, a second operation mode for boosting and outputting the output voltage of the constant voltage circuit by a predetermined value α, And a third operation mode for boosting and outputting the output voltage of the constant voltage circuit to a predetermined value β times larger than the α times, and the first operation mode and the second operation according to the voltage of the power supply voltage. The operation may be performed in any one of the mode and the third operation mode.

  Specifically, the charge pump circuit operates in the first operation mode when the power supply voltage exceeds a predetermined value V1, and the power supply voltage exceeds a predetermined value V2 smaller than the predetermined value V1. When the power supply voltage is less than or equal to the predetermined value V2, the operation is performed in the third operation mode.

  The charge pump circuit operates in a first operation mode when the power supply voltage exceeds a predetermined value V1, and operates in a third operation mode when the power supply voltage is less than the predetermined value V1. May be.

  The charge pump circuit operates in a first operation mode when the power supply voltage exceeds a predetermined value V1, and operates in a second operation mode when the power supply voltage is less than the predetermined value V1. May be.

  The charge pump circuit operates in the second operation mode when the power supply voltage exceeds the predetermined value V3, and operates in the third operation mode when the power supply voltage is less than the predetermined value V3. May be.

  Specifically, when the charge pump circuit operates in the first operation mode, the constant voltage circuit outputs a power supply voltage as an output voltage.

  According to the power supply circuit of the present invention, the charge pump circuit increases the step-up factor in response to a decrease in the power supply voltage to boost the output voltage of the constant voltage circuit. Specifically, the boosting factor of the charge pump circuit is selected from one, α, or β times with respect to the input voltage in accordance with the power supply voltage. Therefore, even when a DC power supply whose voltage gradually decreases like a battery is used, a substantially constant voltage can be supplied as a load power supply, and power efficiency can be improved.

  In addition, a constant voltage circuit with a mode for outputting the power supply voltage as it is is provided in the front stage of the charge pump circuit, so that the output voltage from the charge pump circuit can be stabilized with respect to a wide range of power supply voltages, and power efficiency Can be further improved.

  In addition, since a MOS transistor forming a switching element is used in place of the conventionally used backflow prevention diode, loss due to the forward voltage of the diode can be reduced, and power efficiency can be further improved. .

  Further, by finely controlling the switching timing of each switch element of the charge pump circuit, it is possible to prevent the through current and the back flow of the current to the constant voltage circuit.

  Further, the substrate gate of the MOS transistor is appropriately connected to either the drain side or the source side, and the substrate gate of the switch element is appropriately switched to either the drain side or the source side during the boosting operation by the changeover switch. Accordingly, the reactive current flowing through the parasitic diode of the switch element can be eliminated, the power efficiency can be improved, and the latch-up that causes the malfunction of the IC can be prevented.

Next, the present invention will be described in detail based on the embodiments shown in the drawings.
First embodiment.
FIG. 1 is a circuit diagram showing an example of a power supply circuit according to the first embodiment of the present invention. FIG. 1 shows an example of a three-mode charge pump circuit capable of boosting at three different magnifications.
A power supply circuit 1 in FIG. 1 includes a constant voltage circuit 2 that generates a predetermined constant voltage Va from a power supply voltage VDD input from a DC power supply (not shown) such as a battery, and outputs the constant voltage Va as an output voltage Vo. The charge pump circuit 3 boosts the voltage Vo input to the input terminal CPIN from the voltage circuit 2 and outputs it from the output terminal CPOUT. A load circuit 11 is connected to the output terminal CPOUT of the charge pump circuit 3.

  The constant voltage circuit 2 includes an output control transistor 21 including a P-channel MOS transistor (hereinafter referred to as a PMOS transistor) that controls a current output from an output terminal according to a gate voltage, and a control signal input to a gate. And an error amplifier 23 for controlling the operation of the output control transistor 21. The N-channel MOS transistor (hereinafter referred to as NMOS transistor) 22 controls the gate voltage of the output control transistor 21 according to the above. .

  Furthermore, the constant voltage circuit 2 includes a reference voltage generation circuit 24 that generates and outputs a predetermined reference voltage Vr, a series circuit of a resistor 25 and a resistor 26 that divides the output voltage Vo, and a capacitor 27. The error amplifier 23 amplifies and outputs an error with respect to the reference voltage Vr of the voltage obtained by dividing the output voltage Vo by the resistors 25 and 26 to control the operation of the output control transistor 21. The drain voltage of the output control transistor 21 is stabilized by the capacitor 27, and the output voltage Vo of the constant voltage Va is output from the output terminal.

  The charge pump circuit 3 includes a three-mode charge pump circuit unit 31 that boosts and outputs the voltage Vo input from the constant voltage circuit 2 by 1, 1.5, or 2 times, and a predetermined frequency (100 kHz to 1 MHz). ) And a control for controlling the boosting operation of the charge pump circuit unit 31 based on the clock signal CLK input from the clock signal generation circuit 32. And a circuit unit 33. Further, the charge pump circuit 3 includes a voltage detection circuit unit 34 that detects the power supply voltage VDD and outputs the detection result to the control circuit unit 33. Note that 1.5 times is α times and 2 times is β times.

  The charge pump circuit unit 31 includes two capacitors (hereinafter referred to as flyback capacitors) FC1 and FC2 having the same capacity, and capacitors (hereinafter referred to as catch-up capacitors) that stabilize the output voltage of the charge pump circuit unit 31. C1, and a first switch element SW1, a second switch element SW2, a third switch element SW3, a fourth switch element SW4, a fifth switch element SW5, a sixth switch element SW6, and a seventh switch element SW7 made of PMOS transistors. I have. Further, the charge pump circuit unit 31 includes an eighth switch element SW8 and a ninth switch element SW9 made of NMOS transistors, and changeover switches SW10 and SW11 that are switched according to the input control signal.

  The first switch element SW1 and the sixth switch element SW6 each constitute a first switch element, the second switch element SW2 and the fifth switch element SW5 each constitute a second switch element, and the third switch element SW3 It constitutes a third switch element. The fourth switch element SW4 is the fourth switch element, the seventh switch element SW7 is the sixth switch element, the eighth switch element SW8 is the fifth switch element, and the ninth switch element SW9 is the seventh switch element. Each switch element is formed. The changeover switch SW10 is a first changeover switch, the changeover switch SW11 is a second changeover switch, the flyback capacitors FC1 and FC2 are first capacitors, and the catch-up capacitor C1 is a second capacitor. Make each.

  Control signals S1 to S9 from the control circuit unit 33 are input to the gates of the first to ninth switch elements SW1 to SW9 correspondingly. In addition, control signals S10 and S11 from the control circuit unit 33 are input to the changeover switches SW10 and SW11, correspondingly. Further, the control signal S0 from the control circuit unit 33 is input to the gate of the NMOS transistor 22 and the enable signal input terminal of the error amplifier 23 in the constant voltage circuit 2, respectively.

  The charge pump circuit unit 31 boosts the input voltage Vo to 1 time, 1.5 times, or 2 times according to the control signals S0 to S11 input from the control circuit unit 33, and outputs the output terminal CPOUT. Output from. In the charge pump circuit 3, the operation of boosting the input voltage Vo by 1 time, that is, the operation of outputting the output voltage of the constant voltage circuit 2 as it is is set as the first operation mode and boosted by 1.5 times. The operation is the second operation mode, and the operation of boosting twice is the third operation mode.

  In the charge pump circuit unit 31, the fourth switch element SW4, the flyback capacitor FC1, the third voltage are connected between the input terminal CPIN to which the output voltage Vo of the constant voltage circuit 2 is input and the ground voltage forming the negative power supply voltage. The switch element SW3, the flyback capacitor FC2, and the eighth switch element SW8 are connected in series. Here, a connection portion between the fourth switch element SW4 and the flyback capacitor FC1 is P1, and a connection portion between the flyback capacitor FC1 and the third switch element SW3 is P2. Further, a connection portion between the third switch element SW3 and the flyback capacitor FC2 is P3, and a connection portion between the flyback capacitor FC2 and the eighth switch element SW8 is P4.

  The first switch element SW1 is between the input terminal CPIN and the connection part P2, the seventh switch element SW7 is between the input terminal CPIN and the connection part P3, and between the input terminal CPIN and the connection part P4. The sixth switch element SW6 is connected to each other. The second switch element SW2 is connected between the connection part P1 and the output terminal CPOUT, and the fifth switch element SW5 is connected between the connection part P3 and the output terminal CPOUT. The ninth switch element SW9 is connected between the two.

  The changeover switch SW10 is provided corresponding to the third switch element SW3, and switches the connection of the source or drain to the substrate gate (back gate) of the third switch element SW3 in accordance with the input control signal S10. I do. Similarly, the changeover switch SW11 is provided corresponding to the seventh switch element SW7, and switches the connection of the seventh switch element SW7 to the source or drain with respect to the substrate gate in accordance with the input control signal S11. Do.

  A catch-up capacitor C1 and a load circuit 11 are connected in parallel with the output terminal CPOUT between the ground voltage. The load circuit 11 is formed by a series circuit of an LED 12, a constant current circuit 13, and a resistor 14, for example. In FIG. 1, the case where one LED 12 is provided as the load circuit 11 is shown as an example. However, the same applies to the case where a plurality of LEDs are provided. In this case, in FIG. In between, a plurality of load circuits 11 are connected in parallel.

  In FIG. 1, the output control transistor 21, the NMOS transistor 22, the error amplifier 23, the reference voltage generation circuit 24 and the resistors 25 and 26 in the constant voltage circuit 2, and the clock signal generation circuit unit 32 in the charge pump circuit 3 are controlled. The switch elements SW1 to SW11 of the circuit unit 33, the voltage detection circuit unit 34, and the charge pump circuit unit 31 may be integrated in one IC, and further, one IC including the constant current circuit 13 of the load circuit 11 is included. You may make it accumulate in. In the case of integration as described above, the changeover switches SW10 and SW11 are not switches having mechanical contacts, but are switches composed of electronic circuits.

Here, an example of operation control of the charge pump circuit unit 31 by the control circuit unit 33 will be described with reference to the flowchart of FIG.
In FIG. 2, the control circuit unit 33 first checks whether or not the power supply voltage VDD detected by the voltage detection circuit unit 34 exceeds a predetermined value V1, for example, 4.0V (step ST1). When the voltage exceeds 0 V (YES), the control signal S0 is set to the high level to turn on the NMOS transistor 22 in the constant voltage circuit 2 and stop the operation of the error amplifier 23, and the constant voltage circuit 2 supplies the power as the output voltage Vo. At the same time that the voltage VDD is output, the charge pump circuit unit 31 is operated in the first operation mode (step ST2), and then the process returns to step ST1.

  In step ST1, when it is 4.0 V or less (NO), the control circuit unit 33 causes the power supply voltage VDD detected by the voltage detection circuit unit 34 to exceed a predetermined value V2, for example, 3.2 V, which is smaller than the predetermined value V1. It is checked whether or not (step ST3). When the voltage exceeds 3.2 V in step ST3 (YES), the control circuit unit 33 sets the control signal S0 to a low level to turn off the NMOS transistor 22 in the constant voltage circuit 2 and simultaneously operate the error amplifier 23. Then, the charge pump circuit unit 31 is operated in the second operation mode (step ST4), and it is checked whether or not the power supply voltage VDD detected by the voltage detection circuit unit 34 exceeds 4.1V (step ST5). In step ST5, when it exceeds 4.1V (YES), the process proceeds to step ST2, and when it is 4.1V or less (NO), the process returns to step ST3.

  Next, in step ST3, when it is 3.2 V or less (NO), the control circuit unit 33 sets the control signal S0 to a low level to turn off the NMOS transistor 22 in the constant voltage circuit 2 and to operate the error amplifier 23. At the same time, the charge pump circuit unit 31 is operated in the third operation mode (step ST6), and thereafter, it is checked whether or not the power supply voltage VDD detected by the voltage detection circuit unit 34 exceeds 3.3V. (Step ST7). In step ST7, when it exceeds 3.3V (YES), it progresses to step ST4, and when it is 3.3V or less (NO), it returns to step ST6. In this way, the control circuit unit 33 causes the charge pump circuit unit 31 to perform the operation in the three modes according to the detection result from the voltage detection circuit unit 34.

  Next, FIG. 2 illustrates the case where the control circuit unit 33 causes the charge pump circuit unit 31 to operate in the three modes according to the detection result from the voltage detection circuit unit 34. 33 may be configured to perform the operation in the two modes according to the detection result from the voltage detection circuit unit 34, and an operation control example of the charge pump circuit unit 31 by the control circuit unit 33 in such a case. Will be described with reference to the flowchart of FIG. Note that FIG. 3 shows a case where the operation is performed in two modes of the first operation mode and the third operation mode, and the flow for performing the same processing as in FIG. 2 is denoted by the same reference numeral, and the description thereof is omitted here.

  In FIG. 3, the control circuit unit 33 first performs the process of step ST1 of FIG. 2, and if it exceeds 4.0 V in step ST1 (YES), after performing the operation of step ST2 of FIG. Return to step ST1. Further, when the voltage does not exceed 4.0 V in step ST1 (NO), the control circuit unit 33 performs the process of step ST5 of FIG. 2 after performing the operation of step ST6 of FIG. In step ST5, if it exceeds 4.1V (YES), the process proceeds to step ST2, and if it is 4.1V or less (NO), the process returns to step ST6.

Next, FIG. 4 shows an operation example of the control circuit unit 33 in the case where the operation in the first operation mode and the second operation mode is performed. In FIG. 4, the flow for performing the same processing as FIG. The same reference numerals are used, and the description thereof is omitted here.
In FIG. 4, the control circuit unit 33 first performs the process of step ST1 of FIG. 2, and if it exceeds 4.0 V in step ST1 (YES), after performing the operation of step ST2 of FIG. Return to step ST1. Further, when the voltage is 4.0 V or less in step ST1 (NO), the control circuit unit 33 performs the process of step ST5 of FIG. 2 after performing the operation of step ST4 of FIG. In step ST5, if it exceeds 4.1V (YES), the process proceeds to step ST2, and if it is 4.1V or less (NO), the process returns to step ST4.

FIG. 5 shows an operation example of the control circuit unit 33 in the case where the operation in the second operation mode and the third operation mode is performed. In FIG. 5, the flow for performing the same processing as in FIG. The description is omitted here.
In FIG. 5, the control circuit unit 33 first checks whether or not the power supply voltage VDD detected by the voltage detection circuit unit 34 exceeds a predetermined value V3, for example, 3.5 V (step ST11). If the voltage exceeds 5 V (YES), the operation returns to step ST11 after performing the operation of step ST4 in FIG.

  Further, when the control circuit section 33 is 3.5 V or less in step ST11 (NO), the power supply voltage VDD detected by the voltage detection circuit section 34 after the operation of step ST6 in FIG. It is checked whether or not it exceeds 7V (step ST12). In step ST12, when it is over 3.7V (YES), it progresses to step ST4, and when it is 3.7V or less (NO), it returns to step ST6.

Next, operations of the control circuit unit 33 and the charge pump circuit unit 31 in each operation mode will be described in a little more detail.
FIG. 6 is an equivalent circuit diagram showing the state of each switch element of the charge pump circuit unit 31 in the first operation mode. The operation in the first operation mode in the charge pump circuit 3 will be described with reference to FIG.

  As can be seen from FIG. 6, in the first operation mode, the first switch element SW1, the second switch element SW2, the third switch element SW3, the fourth switch element SW4, the fifth switch element SW5 and the seventh switch element SW7 are respectively The sixth switch element SW6, the eighth switch element SW8, and the ninth switch element SW9 are turned off and are in a cut-off state. Further, the changeover switch SW10 connects the substrate gate of the third switch element SW3 to the source, and the changeover switch SW11 connects the substrate gate of the seventh switch element SW7 to the source.

  Thus, in the first operation mode, the output voltage Vo of the constant voltage circuit 2 is output as it is from the output terminal CPOUT of the charge pump circuit 3. In the third switch element SW3 and the seventh switch element SW7, since the voltage difference between the source and the drain is 0V, each substrate gate may be connected on either the drain side or the source side, but current flows. Since the direction is flowing from the source to the drain, in FIG. 6, each substrate gate is connected to the source.

Next, the second operation mode will be described. FIG. 7 is a timing chart showing an example of each control signal S1 to S11 in the second operation mode, and FIGS. 8 to 13 show an operation example of the charge pump circuit unit 31 with respect to the state of each control signal in FIG. It is the equivalent circuit diagram shown. The operation of the second operation mode in the charge pump circuit 3 will be described with reference to FIGS.
The control circuit unit 33 sets the control signals S1, S2, S5 to S8, S10, and S11 to the high level and sets the control signals S3, S4, and S9 to the low level in the state a where the clock signal CLK is at the high level. (Low) level.

  In such a state a, as shown in FIG. 8, the first switch element SW1, the second switch element SW2, the fifth switch element SW5, the sixth switch element SW6, the seventh switch element SW7, and the ninth switch element SW9 are Each of the third switch element SW3, the fourth switch element SW4, and the eighth switch element SW8 is turned on to be in a conductive state. Furthermore, the changeover switches SW10 and SW11 connect the substrate gates to the sources in the corresponding third switch element SW3 and seventh switch element SW7, respectively. In the state a, the flyback capacitors FC1 and FC2 connected in series are charged with the input voltage Vo, so that each flyback capacitor FC1 and FC2 is charged to a voltage half of the voltage Vo.

  Next, as soon as the clock signal CLK falls to the low level, the control circuit unit 33 raises the control signals S3 and S4 to the high level and lowers the control signals S8 and S10 to the low level. Transition to state b. When the state a transitions to the state b, as shown in FIG. 9, the third switch element SW3, the fourth switch element SW4, and the eighth switch element SW8 are turned off to be in a cut-off state. At the same time, the changeover switch SW10 connects the substrate gate of the third switch element SW3 to the drain. In the state b, since all the switch elements are turned off and are in the cut-off state, the flyback capacitors FC1 and FC2 remain charged to a voltage that is ½ of the voltage Vo.

  Next, after a predetermined time t1 after the clock signal CLK falls to the low level, the control circuit unit 33 causes the control signals S2, S5, and S11 to fall to the low level and transition to the state c in FIG. When the state b is changed to the state c, as shown in FIG. 10, the second switch element SW2 and the fifth switch element SW5 are turned on and become conductive. In the state c, the second switch element SW2 and the fifth switch element SW5 are turned on, the other switch elements are turned off, and the high potential sides of the flyback capacitors FC1 and FC2 are connected to the output terminal CPOUT.

  At this time, when the voltage of the catch-up capacitor C1 is higher than the voltage Vo, the drain voltage of the fourth switch element SW4 is higher than the source voltage, but the substrate gate of the fourth switch element SW4 is connected to the drain side. Therefore, no current flows through the parasitic diode of the fourth switch element SW4. Similarly, although the drain voltage of the seventh switch element SW7 is larger than the source voltage, the substrate gate of the seventh switch element SW7 is connected to the drain side by the changeover switch SW11. No current flows through the diode.

  In the third switch element SW3, the drain voltage is equal to the voltage of the catch-up capacitor C1, and the source voltage is a voltage that is Vo / 2 lower than the voltage of the catch-up capacitor C1. Therefore, in the third switch element SW3, the drain voltage is larger than the source voltage. However, since the substrate gate of the third switch element SW3 is connected to the drain side by the changeover switch SW10, the third switch element SW3. No current flows through the parasitic diode.

  Next, the control circuit unit 33 lowers the control signals S1 and S6 to a low level after a predetermined time t2 from the transition to the state c, and transitions to the state d in FIG. When transitioning from the state c to the state d, as shown in FIG. 11, the first switch element SW1 and the sixth switch element SW6 are turned on and become conductive. In the state d, the first switch element SW1, the second switch element SW2, the fifth switch element SW5, and the sixth switch element SW6 are turned on, and the third switch element SW3, the fourth switch element SW4, the seventh switch element SW7, The eighth switch element SW8 and the ninth switch element SW9 are each turned off.

  For this reason, the low potential side of each flyback capacitor FC1 and FC2 is connected to the input terminal CPIN. From this, the voltages on the high potential side of the flyback capacitors FC1 and FC2 are 1.5 times the voltage Vo, respectively. The catch-up capacitor C1 is charged with the voltage, and the voltage of the catch-up capacitor C1 also rises to 1.5 times the voltage Vo.

  Next, when the clock signal CLK rises to a high level, the control circuit unit 33 immediately raises the control signals S1, S2, S5, and S6 to a high level and makes a transition to the state e in FIG. When the state d is changed to the state e, as shown in FIG. 12, the first switch element SW1, the second switch element SW2, the fifth switch element SW5, and the sixth switch element SW6 are turned off to be in a cut-off state. In the state e, all the switch elements are turned off, and the flyback capacitors FC1 and FC2 supply charges to the catch-up capacitor C1, so that the charging voltage is lower than the voltage Vo / 2.

  Next, the control circuit unit 33 lowers the control signal S4 to the low level after a predetermined time t3 after the clock signal CLK rises to the high level, and raises the control signals S8, S10, and S11 to the high level, respectively. Transition to the state f in FIG. When the state e changes to the state f, as shown in FIG. 13, the fourth switch element SW4 and the eighth switch element SW8 are turned on and become conductive. The changeover switches SW10 and SW11 connect the substrate gates of the corresponding third switch element SW3 and seventh switch element SW7 to the source side.

  In the state f, when the fourth switch element SW4 and the eighth switch element SW8 are turned on, the high voltage side of the flyback capacitor FC1 becomes the same voltage as the voltage Vo, and conversely, the low voltage side of the flyback capacitor FC1. Becomes a voltage slightly higher than Vo / 2. Further, since the flyback capacitor FC2 has a ground voltage on the low voltage side, the voltage on the high voltage side is slightly lower than Vo / 2. For this reason, the source voltage of the third switch element SW3 is higher than the drain voltage. For this reason, the substrate gate of the third switch element SW3 is switched and connected from the drain side to the source side by the corresponding changeover switch SW10 to prevent the generation of reactive current due to the parasitic diode of the third switch element SW3. Generation of reactive current flowing through a parasitic transistor based on a straight gate is prevented.

  Similarly, the source voltage of the seventh switch element SW7 is higher than the drain voltage. For this reason, the substrate gate of the seventh switch element SW7 is switched and connected from the drain side to the source side by the corresponding changeover switch SW11 to prevent generation of reactive current due to the parasitic diode of the seventh switch element SW7. Generation of reactive current flowing through a parasitic transistor based on a straight gate is prevented.

  Further, the control circuit unit 33 lowers the control signal S3 to a low level after a predetermined time t4 from the transition to the state f, and transitions to the state a in FIG. When the state f is changed to the state a, the third switch element SW3 is turned on and becomes conductive as shown in FIG. In this way, in the second operation mode, the seventh switch element SW7 and the ninth switch element SW9 are not used, but are turned off and remain in the cutoff state.

Here, after the clock signal CLK falls to the low level, the timing for turning on the first switch element SW1 and the sixth switch element SW6 and the timing for turning on the second switch element SW2 and the fifth switch element SW5, respectively. The reason for shifting will be described.
Since the voltage on the high voltage side of the catch-up capacitor C1 is usually larger than the voltage Vo, when the flyback capacitors FC1 and FC2 are charged in the state a, the second switch element SW2 and the fifth switch element SW5 The drain voltage becomes larger than the source voltage.

  For this reason, when the substrate gate is connected to the source side in the second switch element SW2 and the fifth switch element SW5, a forward current flows through the parasitic diode of the MOS transistor, and a reactive current is generated. Therefore, in the second switch element SW2 and the fifth switch element SW5, when the substrate gate is connected to the drain side and the flyback capacitors FC1 and FC2 are charged, the parasitic diode of the MOS transistor is in the reverse direction. This prevents a reactive current from flowing.

  When the first switch element SW1 and the sixth switch element SW6 are turned on before the second switch element SW2 and the fifth switch element SW5 during the transition from the state b to the state c, the heights of the flyback capacitors FC1 and FC2 are increased. The voltage on the potential side increases to 1.5 times the voltage Vo. Then, in the second switch element SW2 and the fifth switch element SW5, since the substrate gate is connected to the drain side, the source side voltage becomes larger than the drain side voltage. Each reactive current flows. Therefore, when the transition from the state b to the state c is performed, the second switch element SW2 and the fifth switch element SW5 are turned on before the first switch element SW1 and the sixth switch element SW6, thereby enabling such a reactive current. Can be prevented.

Next, the timing at which the fourth switch element SW4 and the eighth switch element SW8 are turned on and the timing at which the third switch element SW3 is turned on are when transitioning from the state e to the state f and when transitioning from the state f to the state a. The reason for the shift is explained.
In the state d, in the third switch element SW3, the gate voltage is substantially the voltage Vo and the drain voltage is approximately 1.5 times the voltage Vo. It is charged with a voltage that is ½ of Vo, and the polarity is negative on the gate side with respect to the drain. Such a state is the same in state e.

  If the timing at which the eighth switch element SW8 and the third switch element SW3 are turned on at the time of transition from the state e to the state f is the same, the flyback capacitor FC2 and the third switch are turned on by turning on the eighth switch element SW8. The voltage at the connection with the drain of the element SW3 is reduced to about ½ of the voltage Vo. For this reason, in the third switch element SW3, the gate voltage tends to decrease due to the influence of the electric charge charged in the junction capacitance between the gate and the drain.

  At this time, when the control signal S3 changing from the high level to the low level is input to the gate of the third switch element SW3 in order to turn on the third switch element SW3, the junction capacitance between the gate and the drain is charged. Overdrive occurs due to the influence of the charged electric charge, and the gate voltage of the third switch element SW3 instantaneously becomes a negative voltage.

  Then, since the output circuit of the control circuit unit 33 that drives the gate of the third switch element SW3 has a normal CMOS configuration, a reactive current flows through the base substrate of the NMOS transistor that constitutes the output circuit, and the NMOS circuit The parasitic transistor of the transistor is turned on, causing a latch-up. In order to prevent the occurrence of the latch-up, the control circuit unit 33 turns on the third switch element SW3 after a predetermined time t4 has elapsed after the eighth switch element SW8 is turned on.

Next, the third operation mode will be described. FIG. 14 is a timing chart showing an example of each control signal S1 to S11 in the third operation mode. FIGS. 15 to 19 show an operation example of the charge pump circuit unit 31 with respect to the state of each control signal in FIG. It is the equivalent circuit diagram shown. The operation in the third operation mode in the charge pump circuit 3 will be described with reference to FIGS.
In the state a in which the clock signal CLK is at the high level, the control circuit unit 33 sets the control signals S1, S2, S5, S6, S8, S9, and S11 to the high level, and sets the control signals S3, S4, S7, and S10, respectively. Low level.

  In such a state a, as shown in FIG. 15, the first switch element SW1, the second switch element SW2, the third switch element SW3, the fifth switch element SW5 and the sixth switch element SW6 are turned off and cut off. The fourth switch element SW4, the seventh switch element SW7, the eighth switch element SW8, and the ninth switch element SW9 are turned on and are in a conductive state. Further, the changeover switch SW10 connects the substrate gate to the drain in the third switch element SW3, and the changeover switch SW11 connects the substrate gate to the source in the seventh switch element SW7. In the state a, the two flyback capacitors FC1 and FC2 are charged with the output voltage Vo of the constant voltage circuit 2, respectively.

  Next, when the clock signal CLK falls to the low level, the control circuit unit 33 immediately raises the control signals S4 and S7 to the high level and lowers the control signals S8 and S10 to the low level, as shown in FIG. Transition to state b. When the state a changes to the state b, as shown in FIG. 16, the fourth switch element SW4, the seventh switch element SW7, the eighth switch element SW8, and the ninth switch element SW9 are turned off to be in the cut-off state. In the state b, all the switch elements are turned off to be in the cut-off state, the changeover switch SW10 connects the substrate gate to the drain in the third switch element SW3, and the changeover switch SW11 is in the seventh switch element SW7. The gate remains connected to the source. For these reasons, the flyback capacitors FC1 and FC2 are still charged to the voltage Vo.

  Next, after a predetermined time t5 after the clock signal CLK falls to the low level, the control circuit unit 33 causes the control signals S2, S5, and S11 to fall to the low level and transition to the state c in FIG. When the state b transitions to the state c, as shown in FIG. 17, the second switch element SW2 and the fifth switch element SW5 are turned on and become conductive, and the changeover switch SW11 is connected to the sub-switch in the seventh switch element SW7. Connect the straight gate to the drain. In the state c, the second switch element SW2 and the fifth switch element SW5 are turned on, the other switch elements are turned off, and the high potential sides of the flyback capacitors FC1 and FC2 are connected to the output terminal CPOUT.

  At this time, in the third switch element SW3, the drain voltage becomes equal to the voltage of the catch-up capacitor C1, and the source voltage becomes a voltage lower than the voltage of the catch-up capacitor C1 by the voltage Vo. Therefore, in the third switch element SW3, the drain voltage becomes larger than the source voltage. However, since the substrate gate of the third switch element SW3 is connected to the drain side by the changeover switch SW10, the third switch element SW3. No current flows through the parasitic diode.

  Similarly, in the seventh switch element SW7, the drain voltage becomes equal to the voltage of the catch-up capacitor C1, and the source voltage becomes the voltage Vo. Therefore, in the seventh switch element SW7, the drain voltage becomes larger than the source voltage. However, since the substrate gate of the seventh switch element SW7 is connected to the drain side by the changeover switch SW10, the seventh switch element SW7. No current flows through the parasitic diode.

  Next, after a predetermined time t6 from the transition to the state c, the control circuit unit 33 causes the control signals S1 and S6 to fall to the low level and transition to the state d in FIG. When transitioning from the state c to the state d, as shown in FIG. 18, the first switch element SW1 and the sixth switch element SW6 are turned on and become conductive. In the state d, the first switch element SW1, the second switch element SW2, the fifth switch element SW5, and the sixth switch element SW6 are turned on, and the third switch element SW3, the fourth switch element SW4, the seventh switch element SW7, The eighth switch element SW8 and the ninth switch element SW9 are each turned off.

  For this reason, the low potential side of each flyback capacitor FC1 and FC2 is connected to the input terminal CPIN. From this, the voltage on the high potential side of each of the flyback capacitors FC1 and FC2 is twice the voltage Vo. The catch-up capacitor C1 is charged with the voltage, and the voltage of the catch-up capacitor C1 also rises to a voltage twice the voltage Vo.

  Next, when the clock signal CLK rises to a high level, the control circuit unit 33 immediately raises the control signals S1, S2, S5, and S6 to a high level and makes a transition to the state e in FIG. When the state d changes to the state e, as shown in FIG. 19, the first switch element SW1, the second switch element SW2, the fifth switch element SW5, and the sixth switch element SW6 are turned off to be in a cut-off state. In the state e, all the switch elements are turned off, and the flyback capacitors FC1 and FC2 supply charges to the catch-up capacitor C1, so that the charging voltage is lower than the voltage Vo.

  Further, the control circuit unit 33 lowers the control signals S4 and S7 to a low level and raises the control signals S8 and S9 to a high level after a predetermined time t7 from the transition to the state e, respectively. Transition to a. When the state e transitions to the state a, as shown in FIG. 15, the fourth switch element SW4, the seventh switch element SW7, the eighth switch element SW8, and the ninth switch element SW9 are turned on and become conductive.

  As described above, in the third operation mode, the third switch element SW3 is turned off and remains in the cut-off state. Accordingly, the tenth switch element SW10 brings the substrate gate of the third switch element SW3 to the source side. There is no change from the connected state. In addition, after the clock signal CLK falls to the low level, the timing for turning on the first switch element SW1 and the sixth switch element SW6 is shifted from the timing for turning on the second switch element SW2 and the fifth switch element SW5, respectively. The reason for this is the same as in the second operation mode.

  As described above, the power supply circuit according to the first embodiment uses the output voltage Vo from the constant voltage circuit 2 as the input voltage, and the first operation mode in which the voltage Vo is boosted by 1 time. The charge pump circuit 3 is configured to perform a three-mode boost operation of a second operation mode in which the voltage is boosted five times and a third operation mode in which the voltage is boosted twice. The charge pump circuit 3 corresponds to the voltage value of the power supply voltage VDD. Any one of the first operation mode, the second operation mode, and the third operation mode is performed. Therefore, even when a DC power supply whose voltage gradually decreases, such as a battery, an approximately constant voltage can be output to the load circuit, and the output voltage from the charge pump circuit over a wide range of input voltages. Can be stabilized and the power efficiency can be improved.

  In addition, a fourth switch element SW4 having a substrate gate connected to the drain is provided so that current does not flow backward from the high voltage side of the flyback capacitors FC1 and FC2 connected in series to the input terminal CPIN, and a catch-up capacitor is provided. A second switch element SW2 having a substrate gate connected to the drain is provided so that current does not flow backward from the high voltage side of C1 to the flyback capacitors FC1 and FC2 connected in series. From this, it is possible to prevent the current from flowing backward from the high voltage side of the capacitor without using a diode, and it is possible to eliminate a voltage drop due to the forward voltage of the diode when the diode is used.

  Further, when the series circuit of the flyback capacitors FC1 and FC2 is charged with the voltage Vo, the third switch element SW3 is turned on after the fourth switch element SW4 and the eighth switch element SW8 are turned on. Therefore, it is possible to prevent the reactive current from flowing through the base substrate of the NMOS transistor that constitutes the output circuit of the control circuit unit 33 that drives the gate of the third switch element SW3, and the parasitic transistor of the NMOS transistor. Can be turned on and latch-up can be prevented from occurring.

  When the voltages charged in the flyback capacitors FC1 and FC2 are output to the output terminal CPOUT, the substrate switch of the third switch element SW3 is connected to the drain side by the changeover switch SW10, and then the second switch element SW2 and The first switch element SW1 and the sixth switch element SW6 are turned on after the fifth switch element SW5 is turned on. Thus, the reactive current can be prevented from flowing through the parasitic diode in the third switch element SW3, and the source side voltage is higher than the drain side voltage in the second switch element SW2 and the fifth switch element SW5. The reactive current can be prevented from flowing through the substrate gate.

It is a circuit diagram showing an example of a power supply circuit in a 1st embodiment of the present invention. 5 is a flowchart showing an example of operation control of the charge pump circuit unit 31 by the control circuit unit 33. 5 is a flowchart showing another example of operation control of the charge pump circuit unit 31 by the control circuit unit 33. 5 is a flowchart showing another example of operation control of the charge pump circuit unit 31 by the control circuit unit 33. 5 is a flowchart showing another example of operation control of the charge pump circuit unit 31 by the control circuit unit 33. FIG. 6 is an equivalent circuit diagram illustrating a state of each switch element of the charge pump circuit unit 31 in the first operation mode. It is the timing chart which showed the example of each control signal S1-S11 of Figure 1 in 2nd operation mode. FIG. 8 is an equivalent circuit diagram illustrating an operation example of the charge pump circuit unit 31 with respect to the state a in FIG. 7. FIG. 8 is an equivalent circuit diagram illustrating an operation example of the charge pump circuit unit 31 with respect to the state b in FIG. 7. FIG. 8 is an equivalent circuit diagram illustrating an operation example of the charge pump circuit unit 31 with respect to the state c in FIG. 7. FIG. 8 is an equivalent circuit diagram illustrating an operation example of the charge pump circuit unit 31 with respect to the state d in FIG. 7. FIG. 8 is an equivalent circuit diagram illustrating an operation example of the charge pump circuit unit 31 for the state e in FIG. 7. FIG. 8 is an equivalent circuit diagram illustrating an operation example of the charge pump circuit unit 31 with respect to the state f in FIG. 7. 6 is a timing chart showing an example of each control signal S1 to S11 of FIG. 1 in a third operation mode. FIG. 15 is an equivalent circuit diagram illustrating an operation example of the charge pump circuit unit 31 with respect to the state a in FIG. 14. FIG. 15 is an equivalent circuit diagram illustrating an operation example of the charge pump circuit unit 31 with respect to the state b in FIG. 14. FIG. 15 is an equivalent circuit diagram illustrating an operation example of the charge pump circuit unit 31 with respect to the state c in FIG. 14. FIG. 15 is an equivalent circuit diagram illustrating an operation example of the charge pump circuit unit 31 with respect to the state d in FIG. 14. FIG. 15 is an equivalent circuit diagram illustrating an operation example of the charge pump circuit unit 31 with respect to the state e in FIG. 14.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Power supply circuit 2 Constant voltage circuit 3 Charge pump circuit 11 Load circuit 31 Charge pump circuit part 32 Clock signal generation circuit part 33 Control circuit part 34 Voltage detection circuit part SW1 1st switch element SW2 2nd switch element SW3 3rd switch element SW4 4th switch element SW5 5th switch element SW6 6th switch element SW7 7th switch element SW8 8th switch element SW9 9th switch element SW10, SW11 changeover switch FC1, FC2 Flyback capacitor C1 Catch-up capacitor

Claims (7)

A constant voltage circuit that generates and outputs a predetermined constant voltage Va from a power supply voltage supplied from a DC power supply;
A charge pump circuit that boosts the output voltage of the constant voltage circuit at a magnification according to the voltage value of the power supply voltage and supplies the boosted voltage as a load power supply;
With
The power supply circuit, wherein the charge pump circuit detects a voltage of the power supply voltage, and boosts the output voltage of the constant voltage circuit by increasing a boosting factor in response to a decrease in the power supply voltage value.   The charge pump circuit includes a first operation mode for outputting the output voltage of the constant voltage circuit as it is, a second operation mode for boosting and outputting the output voltage of the constant voltage circuit by a predetermined value α, and the constant voltage And a third operation mode in which the output voltage of the circuit is boosted to β times larger than the α times and output, and the first operation mode, the second operation mode, and the third operation according to the voltage of the power supply voltage. 2. The power supply circuit according to claim 1, wherein the power supply circuit operates in any one of the operation modes.   The charge pump circuit operates in a first operation mode when the power supply voltage exceeds a predetermined value V1, and operates in a second operation when the power supply voltage exceeds a predetermined value V2 smaller than the predetermined value V1. 3. The power supply circuit according to claim 2, wherein the power supply circuit operates in a third operation mode when the power supply voltage is less than or equal to the predetermined value V2.   The charge pump circuit operates in a first operation mode when the power supply voltage exceeds a predetermined value V1, and operates in a third operation mode when the power supply voltage is lower than the predetermined value V1. The power supply circuit according to claim 2.   The charge pump circuit operates in a first operation mode when the power supply voltage exceeds a predetermined value V1, and operates in a second operation mode when the power supply voltage is equal to or lower than the predetermined value V1. The power supply circuit according to claim 2.   The charge pump circuit operates in a second operation mode when the power supply voltage exceeds a predetermined value V3, and operates in a third operation mode when the power supply voltage is less than or equal to the predetermined value V3. The power supply circuit according to claim 2.   7. The charge pump circuit according to claim 1, wherein when the charge pump circuit operates in the first operation mode, the power supply voltage is output as an output voltage to the constant voltage circuit. Power supply circuit.

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