JP2002058237A - Charge pump circuit and its control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform charge operation normally, by preventing a parasitic diode from being biased reversely in a charge pump circuit which performs boosting with a small step of Vdd or under in power supply voltage. SOLUTION: This charge pump circuit is provided with a means for biasing the substrate potential of a MOS transistor M2 for control so that a forward current may not flow substantially to a parasitic diode DP1 throughout the all process of charge operation. Specifically, the substrate of the MOS transistor M2 for control is biased with the voltage of a junction between the MOS transistor M2 for control and a capacitor 1, in case that the MOS transistor M2 for control is of p-channel type.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge pump circuit for outputting a boosted voltage in steps equal to or lower than a power supply voltage Vdd and a control method thereof, and more particularly, to a normal charge pump by removing the influence of a parasitic diode associated with a charge transfer element. The present invention relates to a control method of a charge pump circuit that enables an operation.

[0002]

2. Description of the Related Art A charge-pump circuit developed by Dicson connects a plurality of pumping packets in series and boosts the voltage of each pumping packet.
), a voltage higher than the power supply voltage Vdd of the LSI chip is generated. For example, program / erase (program / er
ase) is used to generate the voltage.

[0005] However, the conventional charge pump circuit boosts the voltage in steps of the power supply voltage Vdd, and there has not been proposed any charge pump circuit capable of raising the voltage in a smaller voltage step. The present inventor has already proposed a charge pump circuit capable of increasing the voltage step smaller than Vdd and improving the circuit efficiency η (Japanese Patent Application No. 11-348475).

[0004] The outline is as follows. 17 and 18 are circuit diagrams showing the configuration and operation of the -0.5 Vdd boost charge pump circuit. This charge pump circuit is -0.5 with respect to the ground voltage (0 V).
This is for creating a boosted voltage of Vdd.

In FIG. 17, diodes D1 and D2 are connected in series as charge transfer elements. The ground voltage (0 V) is supplied to the cathode of the diode D1. The diodes D1 and D2 are generally constituted by charge transfer MOS transistors for integration in an LSI.

The switches S1, S2 and S3 connect the two capacitors 1 and 2 to the connection point of the diodes D1 and D2 by switching them in parallel or in series. These switches S
1, S2 and S3 can be constituted by MOS transistors. Thereby, the switches S1, S2, S
ON / OFF of 3 corresponds to ON / OFF of the MOS transistor. The clock driver 3 supplies a clock CLK to the capacitor 2. The output voltage output from the diode D2 is applied to the load 4.

Hereinafter, an outline of a control method of the charge pump circuit will be described. Now, the power supply voltage Vdd of the clock driver 3 is 5V. Also, a diode D1,
By providing D2 and switches S1, S2, S3,
Actually, a voltage drop (Voltage Drop) occurs in that portion, but here, this is ignored and the voltage drop is set to 0V.

When the input clock of the clock driver 3 is at a high level (CLK = High), S1 = OFF, S1 = OFF
If 2 = ON and S3 = OFF, the two capacitors 1
2 are connected in series, and each node voltage is VL1 ≒ 0V,
VA = VB = 2.5V and VC = 5V.

VL1 is the voltage at the connection node (pumping node) between the diode D1 and the capacitor 1, VA is the voltage at the connection node between the capacitor C1 and the switch S2, VB is the voltage at the connection node between the switch S2 and the capacitor 2, and VC is the clock driver. 3 is the voltage of the connection node between the output of the capacitor 3 and the capacitor 2.

That is, assuming that the capacitance values of the capacitors 1 and 2 are equal, the electric charge is equally distributed to the capacitors 1 and 2 so that
It is charged to a voltage of dd / 2 (see FIG. 17).

Next, when the input clock CLK is shifted to a low level (CLK = Low) from the parallel connection state, the capacitors 1 and 2 are coupled to the pumping node.
Each node voltage is VL1 ≒ −2.5V, VA = 0V, V
B = −2.5 V and VC = 5 V (see FIG. 18).

As described above, by repeatedly switching the capacitors 1 and 2 alternately in series and parallel according to the input clock CLK, -2.5 V is applied from the diode D2.
The output voltage of (= − ／ Vdd) is supplied to the load 4.

[0013]

In order to integrate the above-structured charge pump circuit into an LSI, the switches S1, S2, and S3 are provided with switches as shown in FIGS.
Control MOS transistors M1, M2 and M3. The control clock / CLKs is applied to the gate of the control MOS transistor M2. Also, control MO
The control clock / CLK is applied to the gate of the S transistor M3.
p is applied. When the control clock / CLKs is at a low level, the control MOS transistor M2 is turned on, and the capacitors 1 and 2 are connected in series.

When the control clock / CLKp is at a low level, the control MOS transistors M1 and M3 are turned on, and the capacitors 1 and 2 are connected in parallel. Here, the control MO
It is assumed that the substrates of the S transistors M1 and M2 are biased by the potential of the node B in the figure. It is also assumed that the substrate of the control MOS transistor M3 is biased by the output of the clock driver 3.

As shown in FIG. 19, the input clock CLK from the clock driver 3 is at a high level (CLK = H
i) When the control clock / CLKs is at a low level and the control clock / CLKp is at a high level,
The control MOS transistors M1 and M3 are turned off, and the control MOS transistor M2 is turned on. That is, the capacitors 1 and 2 are connected in series. At this time, the control MO
Parasitic PN junction diode associated with S transistor M2
Focusing on Dp, there is no problem because the parasitic PN diode Dp is not forward biased.

The parasitic PN junction diode Dp is formed between the P-type drain (node A in the figure) of the control MOS transistor M2 and the N-type substrate.

However, as shown in FIG. 20, when the input clock CLK is at a low level (CLK = Low), the control clock / CLKs is at a high level, and the control clock / CLKp is at a low level, the control MOS transistors M1, M3 Turns on, and the control MOS transistor M2 turns off. That is, the capacitors 1 and 2 are connected in parallel. At this time, paying attention to the parasitic PN diode Dp associated with the control MOS transistor M2, a problem occurs that the parasitic PN diode Dp is forward-biased.

The drain voltage Vdrain of the control MOS transistor M2 = VA = 0V. Control MOS
Source voltage Vsource of transistor M2 = VB = −2.
It becomes 5V. That is, the drain potential becomes 2.5 V higher than the substrate potential. Then, the parasitic PN junction diode Dp1 composed of the drain of the control MOS transistor M2 and the substrate is forward biased.

That is, the relationship of drain voltage Vdrain−substrate voltage Vbody> VF is established. Here, VF is a forward threshold voltage of the diode. As a result, an unnecessary forward current of the diode flows, causing a problem that the charge pump circuit malfunctions and current consumption increases.

An object of the present invention is to provide a charge pump circuit for boosting a voltage step smaller than Vdd in a boosting operation of the charge pump circuit.
An object of the present invention is to substantially prevent a forward current from flowing through an N-junction diode, enable the charge pump circuit to operate normally, and prevent an increase in current consumption.

[0021]

A charge pump circuit according to the present invention comprises at least a first and a second charge transfer element connected in series, a first and a second capacitor, and one end of the second capacitor. A clock supply unit for outputting a clock, and a capacitor connected between the first and second capacitors, for connecting the first and second capacitors in series to a connection point of the first and second charge transfer elements. First switch means, and second switch means for connecting the first and second capacitors in parallel to a connection point of the first and second charge transfer MOS transistors, and at least the first switch means. The switch means includes a control MOS transistor, and controls the control MOS transistor so that substantially no forward current flows through a parasitic diode associated with the control MOS transistor. Means for biasing the substrate of the data, is characterized in that it comprises a.

The present inventor has studied in detail the operation of a charge pump circuit for boosting a voltage step smaller than Vdd by alternately connecting a capacitor to a pumping node in series and in parallel.
This charge pump circuit is originally useful for improving the power efficiency of the circuit.

As a result, the present inventor has realized that when the switching means used for such switching is constituted by a control MOS transistor, a parasitic diode associated with the control MOS transistor is forward-biased in the course of a charge pump operation. I found a new problem.

Therefore, the problem is solved by providing means for biasing the substrate potential of the control MOS transistor so that substantially no forward current flows through the parasitic diode throughout the charge pump operation. succeeded in.

Preferred embodiments of such a substrate biasing means are as follows.

First, the control MOS transistor is a P-channel type, and the substrate of the control MOS transistor is biased with the voltage at the connection point between the control MOS transistor and the first capacitor.

Second, the control MOS transistor is of a P-channel type, and the substrate of the control MOS transistor is biased by the output voltage of the clock supply means.

Third, the control MOS transistor is N
A channel type, wherein a substrate of the control MOS transistor is biased with a voltage at a connection point between the control MOS transistor and the second capacitor.

Fourth, the control MOS transistor is an N-channel type, and a substrate of the control MOS transistor is biased by a voltage at a connection point between the first and second charge transfer elements.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to the drawings.

FIGS. 1 to 6 are circuit diagrams showing the configuration of a charge pump circuit that outputs a boosted voltage of -0.5 Vdd. This charge pump circuit generates a boosted voltage of -0.5 Vdd with respect to the ground voltage (0 V).

Diodes D1 and D2 as charge transfer elements
Are connected in series. For integration in an LSI, the charge transfer element is formed by a MOS transistor. MOS
Although there is no particular limitation on the transistor, for example, a gate and a source are connected, and the transistor is formed as a kind of diode.

Control MOS transistors M1, M2, M
Reference numeral 3 connects two capacitors 1 and 2 to a connection point (pumping node) of the diodes D1 and D2 by switching between parallel and series. In the present embodiment, the control MOS transistors M1, M2, M3 are of the P-channel type. The control clock / CLKs (an inverted clock of CLKs) is applied to the gate of the control MOS transistor M2. A control clock / CLKp (an inverted clock of CLKp) is applied to the gates of the control MOS transistors M1 and M3.
Is applied.

That is, when the control clock / CLKs becomes low level and the transistor M2 (first switch means) is turned on, the capacitors 1 and 2 are connected in series. When the control clock / CLKp becomes low level and the transistors (M1, M3) (second switch means) are turned on, the capacitors 1 and 2 are connected in parallel.

As will be described later, the transistor M2 and the transistors (M1, M3) are generally controlled to alternately turn on and off.

Focusing on the control MOS transistor M2, the connection point (point A in the figure) of the capacitor 1 and the control MOS transistor M2 is connected to the substrate. Therefore, the substrate is composed of a capacitor 1 and a control MOS.
It is biased by the voltage at the connection point of the transistor M2. Thereby, as described later, the control MOS transistor M
Substantially prevents a forward current from flowing through the parasitic PN junction diode Dp1 associated with 2.

The clock driver 3 supplies a clock CLK to the capacitor 2. The clock driver 3 is not particularly limited, but may be a CMO supplied with the power supply voltage Vdd.
It consists of an S-type inverter. And the diode D
The output voltage output from 2 is applied to the load 4.

In the following, referring to FIGS. 1 to 7,
A control method of the charge pump circuit having the above configuration will be described. FIG. 7 is a timing chart for explaining a control method of the charge pump circuit.

Although not particularly limited, the power supply voltage Vdd of the clock driver 3 is set to 5 V, and
2 have the same capacitance value. Also, charge transfer diodes D1 and D2 and control MOS transistors M1 and M
2, the voltage drop due to M3 is also described as 0V.

(1) First Control Step At time t1, the control MOS transistors M1 and M3 are turned off, so that M1, M2 and M3 are all turned off. The input clock CLK of the clock driver 3 is at a low level (CLK = Low). That is, this is the state shown in FIG. In this state, each node voltage is VL1 ≒
-2.5V, VA = 0V, VB = -2.5V, VC = 0
V. Therefore, the control MOS transistor M2
The parasitic PN junction diode Dp1 associated with is reverse-biased.

VL1 is the voltage at the connection node (pumping node) between the diodes D1 and D2 and the capacitor 1, VA is the voltage at the connection node between the capacitor 1 and the transistor M2, and VB is the voltage at the connection node between the transistor M2 and the capacitor 2. Voltage and VC are the voltage of the connection node between the output of the clock driver 3 and the capacitor 2 (FIGS. 1 and 7).
reference).

(2) Second Control Step Next, the control MOS transistors M1, M2 and M3 are
At the time t2 in which all of them are off, the clock CLK is changed from low level to high level. Then, VC is 5
V, and VB changes to 2.5 V due to the effect of capacitor coupling. Pumping node voltage VL1
Does not change because the transistors M1, M2, and M3 are all off (see FIGS. 2 and 7). That is,
This is the state shown in FIG.

In this state, the control MOS transistor M
Although the parasitic PN junction diode Dp1 associated with 2 is forward-biased, the transistors M2 and M3 are off, so that the node A in the drawing is in a floating state. Therefore, substantially no forward current flows.

(3) Third Control Step Thereafter, a time t3 when the input clock of the clock driver 3 maintains the high level (CLK = High) state
Then, the control transistor M2 is turned on. Thereby, the two capacitors 1 and 2 are connected in series to the pumping node.

As a result, the capacitors 1 and 2 are connected to Vdd
/ 2, and each node voltage is VL1 ≒ 0
V, VA = VB = 2.5V, and VC = 5V. That is, the average output current Iout flows through the MOS transistor M1, and the average output current Iout is also output from the clock driver 3.
out flows (see FIGS. 3 and 7). That is, in FIG.
It is a state of. In this state, since the voltage difference between both ends of the parasitic PN junction diode Dp1 attached to the control MOS transistor M2 becomes 0 V, no forward current flows.

(4) Fourth Control Step Next, at time t4 when the clock CLK = High,
The control transistor M2 is turned off. As a result, all of the transistors M1, M2, and M3 are turned off again. The voltage of each node is maintained as it is (see FIGS. 4 and 7). That is, the state shown in FIG. In this state, the voltage difference between both ends of the parasitic PN junction diode Dp1 associated with the control MOS transistor is maintained at 0 V, so that no forward current flows.

(5) Fifth Control Step Next, at time t5 when all of the transistors M1, M2 and M3 are off, the input clock CLK of the clock driver 3 is changed to low level (CLK = Low).
Then, due to the effect of the capacitor coupling, each node voltage is VL1 ≒ 0 V, VA = 2.5 V, VB = −2.
5V and VC = 0V. (See FIGS. 5 and 7). That is, the state shown in FIG. Therefore, the control MO
Parasitic PN junction diode associated with S transistor M2
Since Dp1 is reverse-biased, no forward current flows.

(6) Sixth Control Step Next, at time t6 when the input clock CLK is maintained at the low level, the transistors M1 and M3 are turned on. Thereby, capacitors 1 and 2 are connected in parallel to the pumping node. Therefore, each node voltage is V
L1 = −2.5V, VA = 0V, VB = −2.5V, V
C = 0V (see FIGS. 6 and 7). That is, FIG.
It is in the state of medium. In this control step, the control M
The parasitic PN junction diode Dp1 associated with the OS transistor M2 is reverse-biased, so that no forward current flows.

Thereafter, the process returns to the first control step, and the first to sixth control steps are repeated. As a result, a voltage of -2.5 V is stably obtained from the diode D2.

According to the control method described above, the control MOS
Parasitic PN junction diode Dp associated with transistor M2
1, the forward current is substantially prevented from flowing through the entire process of the circuit operation, so that the charge pump operation is performed normally and the increase in current consumption due to the flow of unnecessary current is prevented. .

Next, a second embodiment of the present invention will be described with reference to the drawings.

FIGS. 8 to 13 are circuit diagrams showing the configuration of a charge pump circuit for outputting a boosted voltage of -0.5 Vdd. This charge pump circuit is -0.5 Vdd with respect to the ground voltage (0 V) similarly to the circuit of the first embodiment.
To generate a boosted voltage.

This embodiment is different from the first embodiment in that the control MOS transistors M1, M2 and M3 are of the N-channel type. The control clock CLKs is applied to the gate of the control MOS transistor M2. A control clock CLKp is applied to the gates of the control MOS transistors M1 and M3.

That is, the control clock CLKs becomes high level, and the transistor M2 (first switch means)
Is turned on, the capacitors 1 and 2 are connected in series. When the control clock CLKp becomes high level and the transistors (M1, M3) (second switch means) are turned on, the capacitors 1 and 2 are connected in parallel.

As will be described later, the transistor M2 and the transistors (M1, M3) are generally controlled to alternately turn on and off.

Focusing on the control MOS transistor M2, the connection point (point B in the figure) of the capacitor 2 and the control MOS transistor M2 is connected to the substrate. Therefore, the substrate is composed of the capacitor 2 and the control MOS.
It is biased by the voltage at the connection point of the transistor M2. Thereby, as described later, the control MOS transistor M
2 prevents substantially the forward current from flowing through the parasitic PN junction diode Dp2 associated with 2.

Hereinafter, a method of controlling the charge pump circuit having the above-described configuration will be described with reference to FIGS. FIG. 14 is a timing chart for explaining a control method of the charge pump circuit.

Note that, although not particularly limited, the power supply voltage Vdd of the clock driver 3 is set to 5 V,
2 have the same capacitance value. Also, charge transfer diodes D1 and D2 and control MOS transistors M1 and M
2, the voltage drop due to M3 is also described as 0V.

(1) First control step At time t1, the control MOS transistors M1 and M3 are turned off, so that M1, M2 and M3 are all turned off. The input clock CLK of the clock driver 3 is at a low level (CLK = Low). That is, FIG.
It is in the state of medium. In this state, each node voltage is V
L1 ≒ −2.5V, VA = 0V, VB = −2.5V, V
C = 0V. Therefore, the parasitic PN junction diode Dp2 associated with the control MOS transistor M2 is reverse-biased.

VL1 is the voltage at the connection node (pumping node) between the diodes D1 and D2 and the capacitor 1,
VA is the voltage at the connection node between the capacitor 1 and the transistor M2, VB is the voltage at the connection node between the transistor M2 and the capacitor 2, and VC is the voltage at the connection node between the output of the clock driver 3 and the capacitor 2 (see FIGS. 8 and 14). ).

(2) Second control step Next, the control MOS transistors M1, M2 and M3 are
At the time t2 in which all of them are off, the clock CLK is changed from low level to high level. Then, VC is 5
V, and VB changes to 2.5 V due to the effect of capacitor coupling. Pumping node voltage VL1
Does not change because the transistors M1, M2, and M3 are all off (see FIGS. 9 and 14). That is, the state shown in FIG.

In this state, the control MOS transistor M
Although the parasitic PN junction diode Dp2 associated with 2 is forward-biased, the transistors M2 and M3 are off, so that the node A in the drawing is in a floating state. Therefore, substantially no forward current flows.

(3) Third Control Step Thereafter, a time t3 when the input clock of the clock driver 3 maintains the high level (CLK = High) state
Then, the control transistor M2 is turned on. Thereby, the two capacitors 1 and 2 are connected in series to the pumping node.

As a result, the capacitors 1 and 2 are connected to Vdd
/ 2, and each node voltage is VL1 ≒ 0
V, VA = VB = 2.5V, and VC = 5V. That is, the average output current Iout flows through the MOS transistor M1, and the average output current Iout is also output from the clock driver 3.
out flows (see FIGS. 10 and 14). That is, FIG.
4 is the state of FIG. In this state, since the voltage difference between both ends of the parasitic PN junction diode Dp2 associated with the control MOS transistor M2 becomes 0 V, no forward current flows.

(4) Fourth Control Step Next, at time t4 when the clock CLK = High,
The control transistor M2 is turned off. As a result, all of the transistors M1, M2, and M3 are turned off again. The voltage of each node is maintained as it is (FIG. 11,
See FIG. 14). That is, the state shown in FIG.
In this state, since the voltage difference between both ends of the parasitic PN junction diode Dp2 associated with the control MOS transistor M2 is maintained at 0 V, no forward current flows.

(5) Fifth Control Step Next, at time t5 when all of the transistors M1, M2 and M3 are off, the input clock CLK of the clock driver 3 is changed to low level (CLK = Low).
Then, due to the effect of the capacitor coupling, each node voltage is VL1 ≒ 0 V, VA = 2.5 V, VB = −2.
5V and VC = 0V. (See FIGS. 12 and 14). That is, the state shown in FIG. Therefore, the parasitic PN junction diode Dp2 associated with the control MOS transistor M2 is reverse-biased, so that no forward current flows.

(6) Sixth Control Step Next, at time t6 when the input clock CLK is maintained at the low level, the transistors M1 and M3 are turned on. Thereby, capacitors 1 and 2 are connected in parallel to the pumping node. Therefore, each node voltage is V
L1 = −2.5V, VA = 0V, VB = −2.5V, V
C = 0V (see FIGS. 13 and 14). That is, the state shown in FIG. Even in this control step, the parasitic PN junction diode Dp2 associated with the control MOS transistor M2 is reverse-biased, so that no forward current flows.

Thereafter, the process returns to the first control step, and the first to sixth control steps are repeated. As a result, a voltage of -2.5 V is stably obtained from the diode D2.

According to the control method described above, the control MOS
Parasitic PN junction diode Dp associated with transistor M2
2 prevents the forward current from flowing substantially throughout the entire circuit operation, so that the charge pump operation is performed normally and the increase in current consumption due to the flow of unnecessary current is prevented. .

Next, a third embodiment of the present invention will be described with reference to the drawings.

FIG. 15 is a circuit diagram showing a configuration of a charge pump circuit which outputs a boosted voltage of -0.5 Vdd. This charge pump circuit generates a boosted voltage of -0.5 Vdd with respect to the ground voltage (0 V), similarly to the circuit of the first embodiment.

In the present embodiment, similarly to the first embodiment, the control MOS transistors M1, M2 and M3 are of a P-channel type. The control clock / CLKs is applied to the gate of the control MOS transistor M2. The control clock / CLKp is applied to the gates of the control MOS transistors M1 and M3.

That is, when the control clock / CLKs becomes low level and the transistor M2 (first switch means) is turned on, the capacitors 1 and 2 are connected in series. When the control clock / CLKp becomes low level and the transistors (M1, M3) (second switch means) are turned on, the capacitors 1 and 2 are connected in parallel.

Here, focusing on the control MOS transistor M2, the feature of this embodiment is that the capacitor 2 and the output of the clock driver 3 (point C in the figure) are connected to the substrate. There, the substrate is biased with the output voltage of clock driver 3. As a result, similarly to the first embodiment, substantially no forward current flows through the parasitic PN junction diode associated with the control MOS transistor M2.

The control method of the charge pump circuit of the present embodiment is exactly the same as that of the first embodiment, and the description is omitted.

Next, a fourth embodiment of the present invention will be described with reference to the drawings.

FIG. 16 is a circuit diagram showing a configuration of a charge pump circuit for outputting a boosted voltage of -0.5 Vdd. This charge pump circuit generates a boosted voltage of -0.5 Vdd with respect to the ground voltage (0 V), similarly to the circuit of the first embodiment.

In the present embodiment, similarly to the second embodiment, the control MOS transistors M1, M2, M3 are of the N-channel type. The control clock CLKs is applied to the gate of the control MOS transistor M2. A control clock CLKp is applied to the gates of the control MOS transistors M1 and M3.

That is, the control clock CLKs becomes high level, and the transistor M2 (first switch means)
Is turned on, the capacitors 1 and 2 are connected in series. When the control clock CLKp becomes high level and the transistors (M1, M3) (second switch means) are turned on, the capacitors 1 and 2 are connected in parallel.

Here, focusing on the control MOS transistor M2, the charge transfer diode D1,
This embodiment is characterized in that the connection point (pumping node) of D2 is connected. There, the substrate is biased with the voltage of the pumping node. This substantially prevents a forward current from flowing through the parasitic PN junction diode associated with the control MOS transistor M2.

The control method of the charge pump circuit according to the present embodiment is exactly the same as that of the second embodiment, and the description is omitted.

In the first to fourth embodiments, the control MOS transistors M1, M2, and M3 are all formed of the same channel type (N-channel type or P-channel type). It is within the scope of the present invention to mix the N-channel type and the P-channel type. For example, the transistor M2 may be configured as a P-channel type, and the transistors M1 and M3 may be configured as an N-channel type.

In the case where the charge transfer MOS transistors M1 and M2 are diode-connected in place of the diodes D1 and D2, a voltage loss corresponding to the threshold voltage of the MOS transistor occurs. The present invention is not limited to this. The charge transfer MOS transistors M1 and M2 are alternately turned on and off in response to the clock CLK.
1, when the M2 is turned on, the present invention can also be applied to a charge pump circuit configured to supply a boosted voltage (for example, 2 Vdd in absolute value) to those gates.

In this case, M1 is turned on and M2 is turned off during the period when the capacitors 1 and 2 are connected in series, and M1 is turned off and M2 is turned on during the period when the capacitors 1 and 2 are connected in parallel. These gate voltages are controlled so that

As a result, voltage loss of the threshold voltage of the MOS transistor can be eliminated, and
Since the on-resistance of the transistors M1 and M2 is reduced, a charge pump circuit with high efficiency and large output current can be realized.

A MOS transistor for charge transfer is a P-channel type MOS transistor, an N-channel type MOS transistor.
Any of transistors may be used.

In each of the embodiments, an example in which the present invention is applied to a single-stage charge pump circuit that outputs a boosted voltage of -0.5 Vdd has been described. However, the present invention increases the number of charge pump stages by -1. The present invention can also be applied to a two-stage charge pump circuit that outputs a boosted voltage of 0.5 Vdd.

In general, the present invention can be applied to a multi-stage charge pump circuit incorporating the charge pump circuit of the present embodiment as a core. In such a multi-stage charge pump circuit, for example, a voltage of -0.5 Vdd is output in the first stage, and a general Dickson-type charge pump circuit is formed in the second and higher stages.

The charge pump circuit of each embodiment is of a type in which the two capacitors 1 and 2 are switched in series and parallel to perform a voltage step-up of -0.5 Vdd, but two or more capacitors are connected in series. By switching in parallel, the voltage can be boosted in even smaller voltage steps. The present invention can be applied to such a charge pump circuit.

In each of the embodiments, the charge pump circuit that outputs a negative boosted voltage has been described.
The same can be applied to a charge pump circuit having a step of +0.5 Vdd.

[0091]

According to the charge pump circuit and the control method of the present invention, the charge pump circuit for boosting the voltage at a step lower than the power supply voltage by repeatedly switching and connecting the capacitor to the pumping node in series and in parallel is repeated. In this case, the parasitic diode associated with the control MOS transistor is prevented from being forward-biased, so that such a charge pump operation can be performed normally and an increase in current consumption can be prevented.

Further, this makes it possible to integrate the charge pump circuit on a single chip.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a charge pump circuit and a control method thereof according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a charge pump circuit and a control method thereof according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram illustrating a charge pump circuit and a control method thereof according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram illustrating a charge pump circuit and a control method thereof according to the first embodiment of the present invention.

FIG. 5 is a circuit diagram showing a charge pump circuit and a control method thereof according to the first embodiment of the present invention.

FIG. 6 is a circuit diagram showing a charge pump circuit and a control method thereof according to the first embodiment of the present invention.

FIG. 7 is a timing chart showing a charge pump circuit and a control method thereof according to the first embodiment of the present invention.

FIG. 8 is a circuit diagram illustrating a charge pump circuit and a control method thereof according to a second embodiment of the present invention.

FIG. 9 is a circuit diagram illustrating a charge pump circuit and a control method thereof according to a second embodiment of the present invention.

FIG. 10 is a circuit diagram illustrating a charge pump circuit and a control method thereof according to a second embodiment of the present invention.

FIG. 11 is a circuit diagram illustrating a charge pump circuit and a control method thereof according to a second embodiment of the present invention.

FIG. 12 is a circuit diagram illustrating a charge pump circuit and a control method thereof according to a second embodiment of the present invention.

FIG. 13 is a circuit diagram showing a charge pump circuit and a control method thereof according to a second embodiment of the present invention.

FIG. 14 is a timing chart showing a charge pump circuit and a control method thereof according to a second embodiment of the present invention.

FIG. 15 is a circuit diagram showing a charge pump circuit and a control method thereof according to a third embodiment of the present invention.

FIG. 16 is a circuit diagram showing a charge pump circuit and a control method thereof according to a fourth embodiment of the present invention.

FIG. 17 is a circuit diagram showing a conventional charge pump circuit and a control method thereof.

FIG. 18 is a circuit diagram showing a conventional charge pump circuit and a control method thereof.

FIG. 19 is a circuit diagram showing a conventional charge pump circuit and a control method thereof.

FIG. 20 is a circuit diagram showing a conventional charge pump circuit and a control method thereof.

[Description of Signs] 1, 2 Capacitor 3 Clock Driver 4 Load D1, D2 Diode Dp1, Dp2 Parasitic PN Junction Diode M1-M3 Control MOS Transistors S1-S3 Switches

Claims (8)

[Claims] A first and a second capacitor connected in series; a first and a second capacitor; a clock supply unit for outputting a clock to one end of the second capacitor; And first switching means connected between the first and second capacitors, the first and second capacitors being connected in series to a connection point between the first and second charge transfer elements. Second switch means for connecting a second capacitor in parallel to a connection point between the first and second charge transfer MOS transistors; and at least the first switch means comprises a control MOS transistor. Means for biasing the substrate of the control MOS transistor so that substantially no forward current flows through a parasitic diode associated with the control MOS transistor. The charge pump circuit according to claim. 2. The control MOS transistor is of a P-channel type, and a substrate of the control MOS transistor is biased with a voltage at a connection point between the control MOS transistor and the first capacitor. The charge pump circuit according to claim 1, wherein 3. The charge pump circuit according to claim 1, wherein said control MOS transistor is a P-channel type, and a substrate of said control MOS transistor is biased by an output of said clock supply means. . 4. The control MOS transistor is an N-channel type, and a substrate of the control MOS transistor is biased with a voltage at a connection point between the control MOS transistor and the second capacitor. The charge pump circuit according to claim 1, wherein 5. The control MOS transistor is of an N-channel type, and a substrate of the control MOS transistor is biased by a voltage at a connection point of the first and second charge transfer elements. The charge pump circuit according to claim 1. 6. The charge pump circuit according to claim 1, wherein said charge transfer element is constituted by a charge transfer MOS transistor. 7. At least first and second charge transfer elements connected in series; first and second capacitors; clock supply means for outputting a clock to one end of the second capacitor; And first switching means connected between the first and second capacitors, the first and second capacitors being connected in series to a connection point between the first and second charge transfer elements. Second switch means for connecting a second capacitor in parallel to a connection point between the first and second charge transfer MOS transistors; and at least the first switch means comprises a control MOS transistor. Means for biasing the substrate of the control MOS transistor so that substantially no forward current flows through the parasitic diode associated with the control MOS transistor. A method of controlling Jiponpu circuit, after said first and second switching means is turned off, the control method of the charge pump circuit, characterized in that so as to change the state of the clock by the clock supply means. 8. A first step of turning off the first and second switch means, a second step of changing the clock from a first state to a second state by the clock supply means, By turning on the first switch means,
And a third step of connecting the second capacitor in series, a fourth step of turning off the first switch means, and changing the clock from a second state to a first state by the clock supply means. A fifth step of turning on the second switch means,
And a sixth step of connecting a second capacitor in parallel, wherein the first to sixth steps are repeated, and the control method of the charge pump circuit according to claim 7, wherein