JP2006318552A - Semiconductor memory device and testing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of securing the freedom of expected values in a function evaluation test and incorporating a self-diagnosis function capable of simplifying a device configuration. <P>SOLUTION: The semiconductor memory device 1 having an internal diagnosis function for the reading operation of data stored in a memory cell array 15 is provided with a data holding circuit 17 for holding data Φ simultaneously output from the memory cell array 15 by address inputting for the period of a certain clock cycle, and a determination circuit 18 for comparing the output data Φ15 with held data Φ16 outputted from the data holding circuit to determine coincidence/noncoincidence. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and more particularly to a test method for a semiconductor memory device.

  In recent years, with an increase in the speed of a microprocessor or the like, there has been a demand for an increase in operation speed in a semiconductor memory device. Accordingly, a semiconductor memory device (SDRAM) having a synchronous burst mode in which normal random access is speeded up and the external bus interface operates at high speed in synchronization with a clock signal has been developed. In the semiconductor memory device, the reading speed can be increased in a burst mode in which data of a fixed length is transferred every clock in synchronization with the system clock. In recent years, with an increase in the system clock speed, the operation clock of a semiconductor memory device having a burst mode has also been speeded up. For this reason, an LSI tester that performs a function evaluation test for guaranteeing product specifications is also increasing in speed. Note that an LSI tester for performing a function evaluation test of a semiconductor memory device that operates at a relatively high speed is significantly more expensive than an LSI tester for performing a function evaluation test of a semiconductor memory device that operates at a relatively low speed. This is a factor that increases the cost of the function evaluation test of the semiconductor memory device.

  Here, FIG. 17 shows a schematic configuration of the LSI tester 2 that performs a function evaluation test of the conventional semiconductor memory device 20. The LSI tester 2 includes a test input pattern generation circuit 21, an expected value data storage memory 22, an output result correctness determination circuit 23, and a clock generation circuit 24. Here, a case where a function evaluation test of the synchronous semiconductor memory device is performed will be described.

  The test input pattern generation circuit 21 generates and applies a test input signal to the semiconductor memory device 20 in synchronization with the clock φ20 generated by the clock generation circuit 24. The test input signal includes an address signal φ21 that specifies a memory area of the memory cell array of the semiconductor memory device 20 from which data is read, an address fetch control signal φ22 that specifies the timing of fetching the address signal φ21 into the semiconductor memory device 20, and There is a device activation control signal φ23 or the like that activates the read operation of the semiconductor memory device 20.

  When the test input signal is input, the semiconductor memory device 20 outputs the data stored in the memory area specified by the address signal φ21 to the LSI tester 2 as the output data φDoutx in synchronization with the clock φ20.

  When the output data φDoutx is output from the semiconductor memory device 20, the output result correctness determination circuit 23 reads the expected value φTDx stored in advance from the expected value data storage memory 22, and outputs the output data φDoutx and the expected value φTDx. A comparison is made to determine whether or not they match, and φPFout is output as an output determination result output. Here, when the output data φDoutx matches the expected value φTDx, it is determined that the output data φDoutx is normally output.

  FIG. 18 shows an example of a timing chart in the function evaluation test of the semiconductor memory device 20 by the LSI tester 2 described above. Note that the black portion of the output data φDoutx in FIG. 18 indicates that the data output includes defective bits. The semiconductor memory device 20 captures the address signal φ21 at the first rising edge of the clock φ20 after the address capture control signal φ22 becomes Low (ground potential). Subsequently, the semiconductor memory device 20 reads data from the memory area specified by the address signal φ21, and the semiconductor memory device 20 is triggered by the rising edge of the clock φ20 after two cycles from the rising edge of the clock φ20 that has taken in the address signal φ21. The output data φDoutx read out from is output. At this time, the LSI tester 2 reads the expected value φTDx from the expected value data storage memory 22 at the same timing when the output data φDoutx is input to the output result correctness determination circuit 23, and inputs it to the output result correctness determination circuit 23. To do. Subsequently, the output result correctness determination circuit 23 compares the input output data φDoutx and the expected value φTDx, and outputs the determination result as a determination result output signal φPFout. By performing this series of operations on the entire address space of the semiconductor memory device 20, a defective memory cell is identified and a good / defective product is identified.

  However, in the conventional test method of the semiconductor memory device 20 in the LSI tester 2 described above, the maximum value of the frequency of the external clock input to the semiconductor memory device 20 performing the function evaluation test is limited by the operation speed of the LSI tester 2. . In order to perform a function evaluation test by inputting a high-speed clock specified for the semiconductor memory device 20 capable of high-speed operation, an expensive LSI tester 2 capable of inputting a high-speed clock is required. Such an LSI tester 2 is significantly more expensive than an LSI tester 2 that performs a function evaluation test of the semiconductor memory device 20 that operates at a relatively low speed. Further, there is a problem of an increase in cost for the function evaluation test due to an increase in test time associated with an increase in shipment quantity and storage capacity of the semiconductor memory device 20. In addition, since the interface of the semiconductor memory device 20 is faster than the interface of the LSI tester 2, the conventional LSI tester 2 cannot correctly evaluate the internal circuit operation of the semiconductor memory device 20 capable of operating at high speed. Such problems are also becoming apparent. Furthermore, the expected value data storage memory 22 for storing the expected value φTDx for determining whether the output data φDoutx is correct or not needs to be a memory that can be accessed at high speed. Similarly, high-speed determination is required for the read output result correctness determination circuit 23.

  As a technique related to a function evaluation test for a semiconductor memory device, a semiconductor memory device having a built-in self-diagnosis function is disclosed (for example, see Patent Document 1). Since this semiconductor memory device includes a part of the test function of the LSI tester, an LSI tester corresponding to the semiconductor memory device is not required, and the cost for the function evaluation test of the semiconductor memory device can be reduced. However, since this semiconductor memory device has a built-in self-diagnosis function, there is a problem that the circuit scale of the semiconductor memory device itself increases and the chip area increases.

  On the other hand, a semiconductor memory device having a circuit for multiplying the frequency of the external clock and a self-diagnosis function is disclosed as a technique for increasing the speed of the function evaluation test for the semiconductor memory device (see, for example, Patent Document 2). ). Since this semiconductor memory device includes a circuit that multiplies the frequency of the external clock, the memory cell array can perform self-diagnosis at the speed of multiplication of the external clock, and the function evaluation test can be speeded up. Further, by providing the expected value generation circuit, the self-diagnosis function can be simplified, thereby suppressing an increase in chip area.

JP 63-184989 A Japanese Unexamined Patent Publication No. 7-78495

  However, in the semiconductor memory device described in Patent Document 2, since the expected value generation circuit uses the output from the internal counter as an expected value, the degree of freedom of the expected value is lacking. There is a problem that mode detection is difficult.

  The present invention has been made in view of the above problems, and its purpose is to incorporate a self-diagnosis function capable of ensuring the degree of freedom of expected values in the function evaluation test and simplifying the device configuration. A semiconductor memory device is provided.

  In order to achieve the above object, a semiconductor memory device according to the present invention is a semiconductor memory device having an internal diagnosis function for a read operation of data stored in a memory cell array, and is simultaneously output from the memory cell array by address input. A data holding circuit that holds the output data for a certain clock cycle, and a determination circuit that compares the output data with the held data output from the data holding circuit and determines the coincidence / mismatch This is the first feature.

  The semiconductor memory device according to the present invention having the above characteristics further includes a test clock generation circuit that generates an internal clock for testing by multiplying an external clock, and a clock input of the memory cell array is switched from the external clock to the internal clock. A clock switching circuit; an address generation circuit for generating an address for the read operation in synchronization with the internal clock; and an output for outputting determination result data output from the determination circuit in synchronization with the external clock A circuit, wherein the data holding circuit holds the output data for the certain period of the internal clock, and the determination circuit determines the output data in synchronization with the internal clock. Is the second feature.

  In the semiconductor memory device according to the present invention having the above characteristics, the address generation circuit includes a counter circuit that operates in synchronization with the internal clock, and the output of the counter circuit is set to the address. Features.

  Furthermore, in the semiconductor memory device according to the second or third aspect of the present invention, the output circuit includes an RS flip-flop circuit capable of holding the determination result data, and the RS flip-flop circuit includes the determination The determination result data output from the circuit is set input, and the external clock is reset input.

  Furthermore, in the semiconductor memory device according to the second or third aspect of the present invention, the output circuit includes a D flip-flop circuit, and the data input to the D flip-flop circuit is output from the determination circuit. An OR operation or a NOR operation of all bits of the determination result data is input.

  The semiconductor memory device according to the present invention having any one of the above characteristics is characterized in that the determination circuit further includes a 2-input exclusive logic circuit having the same number as the number of bits of the output data.

  In the semiconductor memory device according to the present invention having any one of the above characteristics, the determination circuit outputs the determination result data for each of two memory areas specified by two addresses input in succession. Features.

  In order to achieve the above object, a test method for a semiconductor memory device according to the present invention is a test method for a semiconductor memory device using the semiconductor memory device having any of the above characteristics, and when writing input data to the memory cell array. In addition, it is characterized in that data corresponding to each of corresponding bits is written in two memory areas specified by two addresses inputted in succession or the same data.

  According to the semiconductor memory device of the present invention having the above characteristics, it is provided with a data holding circuit for holding output data from the memory cell array, and output data from the memory cell array (two data specified by two consecutively input addresses). Since one of the data in the memory area) and the data held from the data holding circuit (the other data in the two memory areas specified by two consecutively input addresses) are input to the determination circuit. It becomes possible to compare the data in the two memory areas specified by the two addresses inputted in succession. That is, by writing data so that the data in one memory area of two memory areas specified by two consecutively input addresses is the expected value, the data in the other memory area is expected. A memory area for storing values is not necessary, the circuit configuration can be made relatively small, and an increase in chip size can be suppressed as compared with the conventional configuration. Furthermore, the degree of freedom of the expected value in the function evaluation test can be ensured without complicating the apparatus as compared with the case where the value of the internal counter is set as the expected value as in the prior art.

  The semiconductor memory device according to the second aspect of the present invention includes the test clock generation circuit for multiplying the external clock, so that the read operation of the semiconductor memory device can be confirmed at a relatively low speed. This can be done with an LSI tester that tests the semiconductor memory device.

  Furthermore, by providing an RS flip-flop, the number of output terminals of the determination result data is limited by limiting the determination of the determination circuit to two types of coincidence (all as expected) or mismatch (an error of 1 bit or more). Can be made one terminal. As a result, even when the number of bits of output data increases, a high-speed function evaluation test can be performed even in a conventional LSI tester operating at a relatively low speed.

  According to the test method of the semiconductor memory device of the present invention having the above characteristics, by using the semiconductor memory device having the above characteristics, the data in the two memory areas specified by the two addresses input in succession are compared. Can do. As a result, when the corresponding bits write data complementary to each other in the two memory areas, the device including the data having the same corresponding bits in the comparison between the retained data and the output data is defective. I understand that there is. Similarly, when the same data is written to two memory areas in the corresponding bits, it is understood that the device including the data corresponding to the different bits is defective in the comparison between the retained data and the output data. . That is, in the function evaluation test without complicating the apparatus, the data in one of the two memory areas specified by the two consecutively input addresses is written so as to be the so-called expected value of the other data. The degree of freedom of the expected value can be secured, and the increase in chip size can be suppressed.

  According to the present invention, there is no need to introduce a new high-speed LSI tester even when the semiconductor memory device is further increased in speed and multi-bit, and the increase in the cost for the function evaluation test can be suppressed. it can. Further, according to the present invention, even when the maximum value of the operating frequency of the semiconductor memory device performing the function evaluation test exceeds the testable frequency of the LSI tester, the test at the maximum value of the operating frequency of the semiconductor memory device is performed. Is possible. Further, according to the present invention, the number of output terminals of output result data necessary for Pass / Fail confirmation of the function evaluation test can be reduced to one. Further, since it is not necessary to have expected value data in the internal diagnostic function of the semiconductor memory device, the memory for storing expected value data in the LSI tester can be reduced. Therefore, according to the present invention, it is possible to perform a high-speed function evaluation test of a semiconductor memory device capable of high-speed operation using an existing relatively low-speed and inexpensive LSI tester, which significantly increases the cost of the function evaluation test. Can be suppressed.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a semiconductor memory device and a test method thereof (hereinafter abbreviated as “device of the present invention” and “method of the present invention” as appropriate) will be described below with reference to the drawings.

<First Embodiment>
1st Embodiment of this invention apparatus and this invention method is described based on FIGS. Here, FIG. 1 shows a circuit configuration of the device 1 of the present invention. As an internal diagnosis function for a read operation of data stored in the memory cell array 15, a data latch circuit 17 as a data holding circuit and a determination A circuit 18 is provided. In the present embodiment, a test clock generation circuit 11, a clock switching circuit 12, and a counter circuit 13 as an address generation circuit are further provided. The device 1 of the present invention receives an external clock, a clock control signal C_CTL, and an output control signal OE from an LSI tester (not shown) during a function evaluation test, and outputs determination result data Φ13 to the LSI tester.

  In the present embodiment, a case where an internal clock Φ12 having a frequency twice that of the external clock is used in the function evaluation test will be described. For this reason, in this embodiment, for each two cycles of the internal clock Φ12, determination is made for two memory areas specified by two addresses that are successively input, and determination result data Φ13 is output.

  As shown in FIG. 1, the memory cell array 15 includes a decoder circuit 14 and a data read circuit 16, and operates in synchronization with the internal clock Φ12. The decoder circuit 14 receives the internal address Φ14 output from the counter circuit 13 and selects a memory area. The data read circuit 16 outputs the data in the memory area selected by the decoder circuit 14 as output data Φ15.

  The test clock generation circuit 11 generates a test internal clock Φ11 obtained by multiplying the external clock. In this embodiment, an internal clock Φ11 having a frequency twice that of the external clock is generated.

  FIG. 2 is a block diagram showing an example of the test clock generation circuit 11, and FIG. 3 is a signal waveform diagram of the external clock and the internal clock Φ11. Specifically, the test clock generation circuit 11 generates the internal clock Φ11 having a pulse width corresponding to the delay time delayed by the signal delay inverters INV31, INV32, and INV33 at the rising edge and the falling edge of the external clock.

  The clock switching circuit 12 selects either the external clock or the internal clock Φ11 as the internal clock Φ12 for synchronization of the memory cell array 15. Specifically, the clock switching circuit 12 selects an external clock as the internal clock Φ12 during a normal data read operation, and the internal clock generated by the test clock generation circuit 11 as the internal clock Φ12 during a function evaluation test. The clock Φ11 is selected.

  The counter circuit 13 generates an internal address Φ14 for a read operation in synchronization with the internal clock Φ12. Specifically, the counter circuit 13 changes the internal address Φ14 for each clock in synchronization with the internal clock Φ12 output from the clock switching circuit 12. The counter circuit 13 generates the internal address Φ14 so that all the memory cells in the memory cell array 15 are selected during the function evaluation test.

  During the function evaluation test, the data latch circuit 17 holds the output data Φ15 output from the memory cell array 15 by address input for a fixed clock cycle of the internal clock Φ12. In the present embodiment, the data latch circuit 17 takes in the output data Φ15 output from the memory cell array 15 in synchronization with the internal clock Φ12 and latches it for one cycle of the internal clock Φ12. Further, the data latch circuit 17 outputs the output data Φ15 to the determination circuit 18 in synchronization with the internal clock Φ12. Here, FIG. 4 shows an embodiment of the data latch circuit 17. As shown in FIG. 4, the data latch circuit 17 of this embodiment includes a number of D flip-flops corresponding to the number of bits of the output data Φ15 that are read simultaneously.

  The data latch circuit 17 of this embodiment outputs the output data Φ15 as it is to the output buffer 10 controlled by the output control signal OE during normal operation.

  The determination circuit 18 compares the output data Φ15 with the held data Φ16 output from the data latch circuit 17 in synchronization with the internal clock Φ12, and determines the coincidence / non-coincidence. The determination circuit 18 of this embodiment includes a 2-input exclusive logic circuit having the same number as the number of bits of the output data Φ15.

  Here, FIG. 5 shows a configuration example per bit of the determination circuit 18, and FIG. 6 is a truth table of the 2-input exclusive logic circuit EXNOR0 shown in FIG. Specifically, output data Φ15 output from the memory cell array 15 and holding data Φ16 output from the data latch circuit 17 are input to the 2-input exclusive logic circuit. As a result, the determination circuit 18 performs an exclusive OR operation on the data stored in the memory area specified by the two addresses input in succession. Since the output data Φ15 and the retained data Φ16 are output in synchronization with the internal clock Φ12, as a result, the exclusive OR operation in the determination circuit 18 is also performed in synchronization with the internal clock Φ12.

  Further, the determination circuit 18 of the present embodiment performs determination for two memory areas specified by the two internal addresses Φ14 output continuously from the counter circuit 13 every two cycles of the internal clock Φ12. The determination circuit 18 outputs determination result data Φ13 every two cycles of the internal clock Φ12. Here, the determination circuit 18 determines Fail when the output of the 2-input exclusive logic circuit is High (power supply potential) and Pass when it is Low (ground potential), and determines the output of the 2-input exclusive logic circuit. Output as result data Φ13.

  In the present embodiment, an output determination result latch circuit 19 as an output circuit is further provided at the subsequent stage of the determination circuit 18. The output determination result latch circuit 19 outputs the determination result data Φ13 output from the determination circuit 18 in synchronization with the external clock.

  The output determination result latch circuit 19 includes, for example, an RS flip-flop circuit that can hold the determination result data Φ13 output from the determination circuit 18, and the determination result data Φ13 output from the determination circuit 18 is set as an input. Let the clock be a Reset input. More specifically, the same number of RS flip-flop circuits as the number of bits of the determination result data Φ13 are used, and each bit of the determination result data Φ13 is input to the Set input of each RS flip-flop circuit. By inputting an external clock to the Reset input of the RS flip-flop, the determination result signal Jout is synchronized with the external clock. Further, by performing a logical OR operation on the outputs of all the RS flip-flop circuits and using the result as the determination result signal Jout, the determination result signal Jout can be made 1 bit. As a result, the output determination result latch circuit 19 outputs the determination result signal Jout for one cycle of the external clock.

  FIG. 7 is a block diagram showing another configuration example of the output determination result latch circuit 19. The output determination result latch circuit 19 performs a logical sum operation and then synchronizes the determination result signal Jout with an external clock using a flip-flop circuit. Specifically, an OR operation is performed on all bits of the determination result data Φ13 using a NOR circuit corresponding to the number of bits of the determination result data Φ13, and the result is input to the D flip-flop. Furthermore, by making the output of the D flip-flop circuit the determination result signal Jout, the determination result signal Jout can be made 1 bit. FIG. 7 shows a case where the determination result data Φ13 is composed of 2 bits (signals Φ13_0 and Φ13_1).

  Hereinafter, the test method of the device 1 of the present invention will be described with reference to FIGS. Here, FIG. 8 shows waveforms at the time of a function evaluation test of each signal in the device 1 of the present invention. Note that the black portions of the output data Φ15 and the holding data Φ16 in FIG. 8 indicate data output including defective bits.

  First, a write operation to the memory cell array 15 in the function evaluation test according to the method of the present invention will be described. In the method of the present invention, when input data is written to the memory cell array 15, data corresponding to each other corresponding to two memory areas specified by two consecutively input addresses, or the same data Write. Here, a case will be described in which corresponding bits write data in a complementary relationship.

  Here, FIG. 9 shows an example of write data in the present embodiment. Here, a case where the number of bits of the memory area specified by one address is 4 bits will be described. As can be seen from FIG. 9, the data written in the memory area specified by two consecutively input addresses, that is, Evenadd0 (odd address) and Oddadd1 (even address), have corresponding bits complementary to each other. ing. That is, when one is “0”, the other is “1”. Similarly, data written in a memory area specified by two addresses Evenadd2 (odd address) and Oddadd3 (even address) that are successively input are complementary to each other. As shown in patterns 2 to 5, Oddadd1 and Evenadd2 do not have to be complementary data. Also, the data written in the memory area specified by Evenadd0 and Oddadd1 and the data written in the memory area specified by the two addresses Evenadd2 and Oddadd3 input following Evenadd0 and Oddadd1 are not necessarily the same data. There is no need.

  Next, the reading operation of data stored in the memory cell array 15 according to the method of the present invention will be described.

  In the device 1 of the present invention, the normal operation mode is set when the clock control signal C_CTL is Low, and the function evaluation test mode is set when the clock control signal C_CTL is High. When the clock control signal C_CTL is Low and the normal operation mode is set, the device 1 of the present invention uses the external clock CLK as the internal clock Φ12 and operates in synchronization with the external clock CLK.

  When the clock control signal C_CTL becomes High and the function evaluation test mode is set, the clock switching circuit 12 takes the clock input of the memory cell array 15 from the external clock twice the external clock generated in the test clock generation circuit 11. Is switched to the test internal clock Φ11 having the frequency of

  Furthermore, simultaneously with the clock control signal C_CTL becoming High, the counter circuit 13 is reset, and the initial value of the counter circuit 13 is output to the memory cell array 15 as an initial address. Further, the counter circuit 13 generates the internal address Φ14 in a known addressing order every cycle using the rising edge of the internal clock Φ12 as a trigger.

  When the internal address Φ 14 is input from the counter circuit 13 to the decoder circuit 14, the memory cell array 15 selects a memory area specified by the internal address Φ 14, and outputs data in the selected memory area from the data read circuit 16. Output as data Φ15. As can be seen from FIG. 8, the memory cell array 15 here outputs the output data Φ15 from the data read circuit 16 after four cycles of the internal clock Φ12 after the internal address Φ14 is output from the counter circuit 13. It is configured as follows. The output data Φ15 read from the memory cell array 15 through the data read circuit 16 is input to the data latch circuit 17 and the determination circuit 18.

  When the output data Φ15 is input, the data latch circuit 17 holds the output data Φ15 for one cycle of the internal clock Φ12, and outputs the held data Φ16 to the determination circuit 18 and the output buffer 10.

  In the present embodiment, during the function evaluation test, the output control signal OE is set to a non-output state so that the output data D0 to Dx are not output. This is because the inventive device 1 of the present embodiment is operated by the internal clock Φ12 having a frequency twice that of the external clock during the function evaluation test, so that the output data D0 to Dx are also at the timing of the internal clock Φ12. This is because the output data D0 to Dx cannot be measured by an LSI tester that is switched and operates at an operation frequency (external clock frequency) slower than the frequency of the internal clock Φ12.

  When the output data Φ15 and the hold data Φ16 are input, the determination circuit 18 compares the output data Φ15 and the hold data Φ16 in synchronization with the internal clock Φ12, and determines a match / mismatch. Specifically, the determination circuit 18 of the present embodiment compares the output data Φ15 and the retained data Φ16 for each bit, and sets the exclusive OR of all these bits as the determination result data Φ13. As a result, the determination result data Φ13 can be set to 1 bit, and the increase in the number of output terminals can be suppressed.

  If there is a bit having the same polarity as a result of the exclusive OR operation, the determination circuit 18 determines that it is Fail, and outputs a High (power supply potential) determination result output Jout for one cycle of the external clock. Accordingly, it can be determined that a value different from the expected value is output in either the output data Φ15 or the retained data Φ16 determined by the determination circuit 18 one cycle before the external clock.

Second Embodiment
Next, 2nd Embodiment of this invention apparatus 1 and this invention method is described based on FIG.10 and FIG.11. In the present embodiment, a case where the circuit configuration of the test clock generation circuit 11 is different from that of the first embodiment will be described.

  As shown in FIG. 10, the test clock generation circuit 11 of the present embodiment is configured to input two external clocks CLK1 and CLK2 having a phase difference of ¼ cycle from the LSI tester as external clocks. An internal clock Φ11 having a cycle twice that of the external clock is generated from the external clocks CLK1 and CLK2. FIG. 11 is a waveform diagram of each signal of the test clock generation circuit 11 shown in FIG.

<Third Embodiment>
Next, 3rd Embodiment of this invention apparatus 1 and this invention method is demonstrated based on FIGS. 12-14. In the first and second embodiments, the case where an internal clock having a frequency twice that of the external clock is used in the function evaluation test has been described. However, in this embodiment, an internal frequency having a frequency that is four times that of the external clock is used. A case where a clock is used will be described.

  The test clock generation circuit 11 of this embodiment generates an internal clock Φ11 having a frequency four times that of an external clock. Here, FIG. 12 shows a circuit configuration of the test clock generation circuit 11 of the present embodiment, which is configured by combining the circuit of FIG. 2 and the circuit of FIG. FIG. 13 is a waveform diagram of each signal in the test clock generation circuit 11 shown in FIG.

  The determination circuit 18 of the present embodiment includes two D flip-flops DFF71 and DFF72 as shown in FIG. Specifically, in the determination circuit 18 of this embodiment, the held data Φ16 from the data latch circuit 17 is input to the D flip-flop circuit DFF71 in the determination circuit 18, and the output of the D flip-flop DFF71 is the D flip-flop. It is input to the DFF 72. In this way, by connecting the two D flip-flops DFF71 and DFF72 like a shift register, the output data Φ15 from the memory cell array 15, the retained data Φ16 from the data latch circuit 17, and the D flip-flop DFF71 in the determination circuit 18 are connected. The output signal Φ71 and the output signal Φ71 of the D flip-flop DFF72 can be monitored at the same timing. Accordingly, it is possible to simultaneously determine the four memory areas specified by the four addresses continuously output from the counter circuit 13 every four cycles of the internal clock Φ11. In other words, two sets of determinations for two memory areas specified by two addresses can be performed simultaneously.

  Furthermore, the determination circuit 18 of the present embodiment outputs determination result data Φ13 every four cycles of the internal clock Φ12. Similar to the first and second embodiments, the determination result data Φ13 is an output of a 2-input exclusive logic circuit, and High is output for Fail and Low is output for Pass.

  In this way, the internal clock Φ11 having a frequency four times that of the external clock is generated using the test clock generation circuit 11 shown in FIG. 12, and the determination circuit 18 shown in FIG. It is possible to determine the four memory areas specified by the four addresses output in synchronization with the internal clock Φ12. Then, by outputting the determination result signal Jout in synchronization with the external clock, the function evaluation test can be performed at a speed four times that of the external clock.

<Fourth embodiment>
Next, a fourth embodiment of the device 1 of the present invention and the method of the present invention will be described based on FIGS. 15 and 16. In the first to third embodiments, the case where the corresponding bits write data complementary to each other has been described for the write operation to the memory cell array 15 in the function evaluation test. However, in the present embodiment, the corresponding bits The case where each writes the same data is demonstrated.

  The determination circuit 18 of the present embodiment configures EXNOR0 constituting the determination circuit 18 (see FIG. 5) of the first and second embodiments, or the determination circuit 18 (see FIG. 14) of the third embodiment. EXNOR1 and EXNOR2 are replaced with the EXOR logic shown in FIG. This makes it possible to determine when the corresponding bits write the same data.

  In the method of the present invention of this embodiment, in the function evaluation test, the corresponding bits write the same data in the two memory areas specified by the two addresses that are successively input.

  Here, FIG. 16 shows an example of write data in the present embodiment, and shows a case where the number of bits of the memory area specified by one address is 4 bits, as in the first to third embodiments. Yes. As can be seen from FIG. 16, the same data is written in the memory area specified by two consecutively input addresses, that is, Evenadd0 and Oddadd1. Similarly, the same data is written in a memory area specified by two addresses Evenadd2 and Oddadd3 that are successively input. As in the first to third embodiments, when viewed with four consecutively input addresses, the data written in the memory area specified by Evenadd0 and Oddadd1 and the data input after Evenadd0 and Oddadd1 are input. The data written in the memory area specified by the two addresses Evenadd2 and Oddadd3 is not necessarily the same data. Conversely, it is possible to perform a test with a test pattern in which all test data are arranged with the same polarity.

<Another embodiment>
Next, another embodiment of the device 1 of the present invention and the method of the present invention will be described.

  <1> In the first to third embodiments, the fourth embodiment is described in the case where complementary data is written in two memory areas specified by two consecutively input addresses in the function evaluation test. In the embodiment, the case where the same data is written to two memory areas specified by two consecutively input addresses has been described. However, two memory areas specified by two consecutively input addresses On the other hand, a case where complementary data is written and a case where the same data is written may be combined.

  If two memory areas contain a defect in the same direction, the same data cannot be detected when writing the same data to two memory areas specified by two consecutively input addresses. The defect can be detected when the related data is written. Similarly, when two memory areas include defects in different directions, the defect cannot be detected when complementary data is written into two memory areas specified by two addresses that are successively input. When the same data is written, the defect can be detected. Therefore, by performing the function evaluation test in combination with a case where complementary data is written and a case where the same data is written in two memory areas specified by two consecutively input addresses, Defects can be reliably detected.

  <2> In each of the above embodiments, a 1-bit determination result signal Jout is output and only the quality of the semiconductor memory device 1 is determined. However, the address of the memory area including the defective bit may be specified. . Specifically, the function evaluation test is performed in combination with the case where the addresses continuously input are shifted by one. For example, the address input is performed so as to compare the data in the two memory areas specified by Evenadd2 and Oddadd3. By doing so, it is possible to detect which memory area is specified by which address is defective.

  The present invention is useful for a semiconductor memory device, particularly a synchronous semiconductor memory device that operates at high speed.

1 is a block diagram showing a schematic configuration of a first embodiment of a semiconductor memory device according to the present invention. 1 is a block diagram showing a configuration example of a test clock generation circuit in a first embodiment of a semiconductor memory device according to the present invention; Timing chart for explaining the operation of the test clock generation circuit in the first embodiment of the semiconductor memory device according to the present invention. 1 is a block diagram showing a configuration example of a data latch circuit of a semiconductor memory device according to the present invention. 1 is a block diagram showing a configuration example of a determination circuit of a semiconductor memory device according to the present invention. Truth table showing operation of exclusive OR circuit constituting determination circuit in first embodiment of semiconductor memory device according to the present invention 4 is a block diagram showing a configuration example of an output determination result latch circuit of a semiconductor memory device according to the present invention. Timing chart showing operation during function evaluation test of semiconductor memory device according to the present invention FIG. 5 is a diagram showing an example of a test pattern used in the first embodiment of the test method of the semiconductor memory device according to the invention. FIG. 7 is a block diagram showing a configuration example of a test clock generation circuit in the second embodiment of the semiconductor memory device according to the invention. Timing chart for explaining the operation of the test clock generation circuit in the second embodiment of the semiconductor memory device according to the invention The block diagram which shows the structural example of the test clock generation circuit in 3rd Embodiment of the semiconductor memory device which concerns on this invention. Timing chart for explaining the operation of the test clock generation circuit in the third embodiment of the semiconductor memory device according to the invention. The block diagram which shows the structural example of the determination circuit in 3rd Embodiment of the semiconductor memory device based on this invention. Truth table showing operation of exclusive OR circuit constituting determination circuit in fourth embodiment of semiconductor memory device according to the present invention The figure which shows an example of the test pattern used in 4th Embodiment of the test method of the semiconductor memory device concerning this invention Block diagram showing a configuration example of an LSI tester and a semiconductor memory device according to the prior art Timing chart showing operation during function evaluation test of LSI tester and semiconductor memory device according to prior art

Explanation of symbols

1: Semiconductor memory device 2 according to the present invention: LSI tester 10: output buffer 11: test clock generation circuit 12: clock switching circuit 13: counter circuit 14: decoder circuit 15: memory cell array 16: data read circuit 17: data latch circuit 18: Determination circuit 19: Output determination result latch circuit 20: Semiconductor memory device 21 according to prior art: Test input pattern generation circuit 22: Expected value data storage memory 23: Output result correctness determination circuit 24: Clock generation circuit INV31- 38, INV71, INV81: Inverters NAND31-34: NAND gates NOR31, NOR32, NOR71, NOR81: NOR gates DFF51, DFF71-72, DFF81: D-type flip-flop circuits EXNOR0-2: EXNOR gates EXNOR0 to 1: EXOR gate Φ11: Internal clock Φ12: Internal clock Φ13: Determination result data Φ14: Internal address Φ15: Output data Φ16: Holding data Φ20: Clock Φ21: Address signal Φ22: Address capture control signal Φ23: Device activation control Signals Φ71 and Φ72: Output signal φTDx: Expected value φDoutx: Output data signal

Claims (8)

A semiconductor memory device having an internal diagnostic function for a read operation of data stored in a memory cell array,
A data holding circuit for holding output data simultaneously output from the memory cell array by address input for a fixed clock period;
A semiconductor memory device, comprising: a determination circuit that compares the output data with the held data output from the data holding circuit and determines a match / mismatch. A test clock generation circuit for generating an internal clock for testing by multiplying an external clock;
A clock switching circuit for switching the clock input of the memory cell array from the external clock to the internal clock;
An address generation circuit for generating an address for the read operation in synchronization with the internal clock;
An output circuit that outputs a predetermined determination result signal in synchronization with the external clock based on the determination result data output from the determination circuit;
The data holding circuit holds the output data for the certain period of the internal clock,
The semiconductor memory device according to claim 1, wherein the determination circuit determines the output data in synchronization with the internal clock.   3. The semiconductor memory device according to claim 2, wherein the address generation circuit includes a counter circuit that operates in synchronization with the internal clock, and an output of the counter circuit is used as the address. The output circuit has an RS flip-flop circuit capable of holding the determination result data,
4. The semiconductor memory device according to claim 2, wherein the RS flip-flop circuit uses the determination result data output from the determination circuit as a Set input and uses the external clock as a Reset input.   The output circuit includes a D flip-flop circuit, and an OR operation or a NOR operation of all bits of the determination result data output from the determination circuit is input to a data input of the D flip-flop circuit. The semiconductor memory device according to claim 2 or 3.   The semiconductor memory device according to claim 1, wherein the determination circuit includes a 2-input exclusive logic circuit having the same number as the number of bits of the output data.   7. The semiconductor according to claim 1, wherein the determination circuit outputs the determination result data for each of two memory areas specified by two consecutively input addresses. Storage device. A test method for a semiconductor memory device using the semiconductor memory device according to claim 1,
When writing input data to the memory cell array, data corresponding to each other is written in two memory areas specified by two consecutively input addresses or the same data. A method for testing a semiconductor memory device.