JP2006317962A - Method of fabricating liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent increase of resistance caused by plasma application in a method of fabricating a liquid crystal display device, in which a transparent conductive film is patterned on an interlayer insulating film having at least an organic insulating film. <P>SOLUTION: The interlayer insulating film is comprised of an inorganic insulating film 32 and the organic insulating film 33 formed on the inorganic insulating film 32. A step to form transparent electrodes 71, 72, which are electrically connected to the switching device through the interlayer insulating film, on the interlayer insulating film is provided. The step includes a step to pattern the organic insulating film 33, a step to apply plasma to the substrate including the organic insulating film 33, a step to form contact holes 26, 27 throughout the inorganic insulating film 32, a step to deposit the transparent conductive film on the interlayer insulating film, and a step to form the transparent electrodes 71, 72 by patterning the transparent conductive film. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a liquid crystal display device, and more particularly to a method for manufacturing a liquid crystal display device including a step of patterning a transparent conductive film on an organic insulating film using an organic insulating film as an interlayer insulating film.

  Liquid crystal display devices are classified into transmissive liquid crystal display devices, reflective liquid crystal display devices, and transflective liquid crystal display devices according to the type of light source.

  The transmissive liquid crystal display device includes a light source for backlight, and display is performed by the backlight. The reflection type liquid crystal display device has a reflection plate inside, and reflects light incident from the outside by this reflection plate as a light source. Therefore, unlike a transmissive liquid crystal display device, it is not necessary to provide a backlight as a light source. The transflective liquid crystal display device is configured such that half of the display area is a transmissive liquid crystal display device and the other half is a reflective liquid crystal display device.

  Among the three types of liquid crystal display devices described above, in a transmissive liquid crystal display device, a thin film transistor (TFT) or a MIM (Metal Insulator Metal) has been widely used as a switching element for driving and controlling a pixel electrode. It has been. As the pixel electrode, an indium tin oxide film (ITO) or other transparent conductive film is widely used from the viewpoint of ensuring high transmittance and low resistivity.

  Various techniques have been disclosed so far for patterning ITO into pixel electrodes.

  For example, in Japanese Patent Laid-Open No. 6-89773 (Patent Document 1), ITO is formed on a silicon oxide or other inorganic interlayer insulating film by sputtering at a temperature of 0 ° C. to 100 ° C., and after patterning, 200 in a hydrogen atmosphere. A technique of performing heat treatment at a temperature of from ℃ to 400 ℃ (preferably from 230 ℃ to 380 ℃) is disclosed. As a result, the heat treatment for reducing the dangling bonds in the semiconductor layer of the TFT and improving the electrical characteristics and the heat treatment (annealing) for increasing the ITO transmittance and decreasing the resistivity are performed in one step. It is stated that it can be.

  On the other hand, as a technique for patterning ITO on an acrylic resin or other organic insulating film, for example, in Japanese Patent Laid-Open No. 9-258247 (Patent Document 2), ITO is deposited on an organic interlayer insulating film made of acrylic resin at 230 ° C. A technique is disclosed in which a film is formed by sputtering at a temperature of about a degree, heat treatment is performed immediately after the film formation at a temperature of 100 ° C. or more and a film formation temperature or less, and ITO is patterned after the heat treatment. It is stated that the line width shift during ITO patterning can be reduced by performing a heat treatment after the ITO film is formed.

  When an organic insulating film is used as an interlayer insulating film, as in Patent Document 1, when heat treatment is performed at a temperature of 230 ° C. or higher, the organic insulating film is generally decomposed and the transmittance is reduced. For this reason, the heat treatment for reducing dangling bonds in the semiconductor layer of the TFT and improving the electrical characteristics is usually performed before the formation of the organic insulating film and is performed independently of the heat treatment after the ITO film formation.

  Furthermore, as a technique for simultaneously forming an ITO pattern on an acrylic resin or other organic insulating film and on a silicon nitride or other inorganic insulating film, for example, Japanese Patent Laid-Open No. 2001-343901 (Patent Document 3) discloses the above-mentioned patent document. 2, ITO is formed on the organic insulating film and the inorganic insulating film, and after the film formation, heat treatment is performed at a temperature of 150 ° C. to 220 ° C. (preferably 200 ° C. to 220 ° C.), and the ITO is patterned after the heat treatment. Technology is disclosed.

Japanese Patent Application Laid-Open No. 2001-345023 (Patent Document 4) and Japanese Patent Application Laid-Open No. 2001-345024 (Patent Document 5) perform plasma treatment with oxygen, Ar, and CF ₄ before forming an ITO film to form an organic insulating film. A technique for controlling the crystal grain size of the above ITO to 20 nm to 50 nm is disclosed. The etching rate of ITO on the organic insulating film and the ITO on the inorganic insulating film become almost the same by the heat treatment after the ITO film formation and the plasma treatment before the film formation, and the line width shift at the time of ITO patterning can be reduced. Is stated. Further, Patent Document 4 states that after ITO is patterned, a heat treatment at a temperature of 150 ° C. to 220 ° C. may be added.

Further, as a technique for patterning ITO on polyimide resin, acrylic resin or other organic insulating film, for example, JP-A-10-161158 (Patent Document 6) discloses sputter etching, dry etching, A technique for roughening an organic insulating film by a UV treatment method is disclosed. It is stated that these treatments increase the contact area between the ITO and the organic insulating film and improve the adhesion between them, so that the ITO can be accurately patterned. Further, it is stated that these treatments may be performed either after the contact hole is opened or before the contact hole is opened.
Japanese Patent Laid-Open No. 6-88973 (page 3) JP-A-9-258247 (page 4-5) JP 2001-343901 A (page 6) Japanese Patent Laying-Open No. 2001-345023 (pages 12-14 and FIGS. 12-16) JP 2001-345024 A (page 7-8, FIG. 7-9) Japanese Patent Laid-Open No. 10-161158 (page 10-11, FIGS. 13-14)

  When considering the pattern formation of ITO on an acrylic resin or other organic interlayer insulating film, in the method of Patent Document 1 described above, since the heat treatment temperature is generally higher than the heat resistance temperature of the organic insulating film, the organic insulating film is decomposed and colored. Occurs and the transmittance decreases. In the temperature range of about 200 ° C. to 230 ° C., the decomposition of the organic insulating film is generally suppressed, but the temperature is too low and insufficient to reduce dangling bonds in the semiconductor layer of the TFT. Therefore, it is impossible to perform the heat treatment (annealing) step once in the manufacture of the TFT substrate.

  On the other hand, in the method of Patent Document 2 described above, the ITO film is altered by the gas discharged from the organic insulating film during the ITO film formation, and an etching residue is generated during patterning. The etching residue can be suppressed to some extent if the ITO film formation temperature is lowered to 100 ° C. or lower, but the generation of the residue cannot be completely suppressed. In addition, by performing the heat treatment after the ITO film formation, a heat treatment (annealing) step in manufacturing the TFT substrate is required twice.

In Patent Document 4 and Patent Document 5 described above, the plasma treatment is performed before the ITO film is formed, that is, after the contact hole is opened in the organic interlayer insulating film. It has been found through experiments by the present inventors that the contact resistance with the lower metal film increases. In particular, this phenomenon is remarkable when CF ₄ or other fluorine-based gas or He gas is used.

  Further, in Patent Document 6 described above, when the organic insulating film is first subjected to UV treatment, the organic insulating film is decomposed and coloring occurs. When sputter etching or dry etching is performed before opening the contact hole, if the organic insulating film is non-photosensitive, it is possible to form the organic insulating film and perform sputter etching or dry etching after firing. On the other hand, when the organic insulating film is photosensitive, it is necessary to perform sputter etching or dry etching in a state where the organic insulating film is formed. Therefore, the etching apparatus is contaminated or productivity is remarkably increased. In addition to harming, minute irregularities of the formed organic insulating film are flattened during firing, and the intended purpose cannot be achieved. On the other hand, when sputter etching or dry etching is performed after opening the contact hole, there is a problem that the contact resistance described above increases.

  This increase in contact resistance may cause phenomena such as horizontal crosstalk and uneven horizontal stripes in a common storage type TN (Twisted Nematic) type or IPS (In-Plane Switching) type liquid crystal display device. In other words, in the case of the common storage method, a common potential is applied to the common wiring (common wiring), and thus it is necessary to bind the common wiring to each other. However, the TFT is formed by performing the binding through the ITO film on the interlayer insulating film. In the case of adopting the structure, since the organic insulating film is used, the contact resistance becomes high, and it is inevitable that the resistance of the entire common wiring becomes high.

  In recent years, a high aperture ratio such that a common electrode made of a transparent conductive film is formed on a signal line through an organic interlayer insulating film, and a pixel electrode made of the same transparent conductive film as the common electrode is formed facing the common electrode. IPS type liquid crystal display device has been realized (see, for example, WO 98/47044).

  In such a liquid crystal display device, it is very important to pattern the transparent conductive film on the organic insulating film accurately and uniformly in the substrate surface. This is because display unevenness occurs when the process control of the transparent conductive film forming step is not sufficient. In addition, as described above, in the common storage type IPS liquid crystal display device, it is important to reduce the contact resistance between the transparent conductive film and the base metal film through the organic interlayer insulating film.

  Thus, the pattern accuracy of the transparent conductive film on the organic interlayer insulating film can be improved, and the contact resistance between the transparent conductive film on the organic interlayer insulating film and the base metal film can be kept low. There is a need for a manufacturing method.

  The present invention has been made in view of the above problems, and in the method for manufacturing a liquid crystal display device using at least an organic interlayer insulating film, formation of contact holes in the inorganic interlayer insulating film and the organic interlayer insulating film, In addition, when forming the pattern of the transparent conductive film on the organic interlayer insulating film, the pattern can be formed uniformly and accurately within the substrate surface without producing an etching residue of the transparent conductive film. An object of the present invention is to provide a method of manufacturing a liquid crystal display device that can eliminate display defects by preventing an increase in contact resistance between the two.

  The present invention includes a first step of forming a switching element on a substrate, a second step of covering the switching element with an interlayer insulating film having an upper layer made of at least an organic insulating film, and the interlayer insulating film through the interlayer insulating film. And a third step of forming a transparent electrode connected to the switching element on the interlayer insulating film, wherein the interlayer insulating film has the organic insulating film on the inorganic insulating film. The third step includes a step of patterning the organic insulating film, a step of performing plasma treatment on a substrate including the organic insulating film, a step of opening a contact hole in the inorganic insulating film, A method for manufacturing a liquid crystal display device, comprising: depositing a transparent conductive film on an interlayer insulating film; and patterning the transparent conductive film to form a transparent electrode. To provide.

  In the step of patterning the organic insulating film, it is preferable that the organic insulating film is patterned so as to cover at least a part of the signal line including the drain electrode of the switching element.

  The first step includes, for example, forming a scanning line including a gate electrode and a common wiring for supplying a common potential on the substrate, and covering the scanning line and the common wiring with gate insulation on the substrate. A step of forming a film, a step of forming a semiconductor layer that becomes an active layer of the switching element on the gate insulating film, a signal line that intersects the scanning line and includes a drain electrode of the switching element, and the switching Forming a source electrode of the element, and patterning the transparent conductive film to form a transparent electrode includes patterning the transparent conductive film and forming the transparent electrode on the interlayer insulating film. The method may include a step of forming a pixel electrode connected to the switching element and a common electrode connected to the common wiring.

  The plasma treatment is preferably performed with helium (He) plasma.

  The step of opening a contact hole in the inorganic insulating film includes, for example, a step of patterning a photoresist on the interlayer insulating film, a step of post-baking the photoresist, and the inorganic insulating film using the photoresist as a mask. And wet etching or performing both wet etching and dry etching.

  The transparent conductive film is preferably formed of, for example, an indium tin oxide film (ITO) or an indium zinc oxide film (IZO).

  According to the present invention, an interlayer insulating film composed of an inorganic insulating film and an organic insulating film is provided on a TFT, and a He plasma treatment is performed on the interlayer insulating film including the organic insulating film before opening a contact hole in the inorganic insulating film. By performing this, patterning of the transparent conductive film can be performed accurately and uniformly, and at the same time, an increase in contact resistance between the transparent conductive film and the base metal film can be prevented. In particular, in an IPS liquid crystal display device having a common electrode and a pixel electrode made of a transparent conductive film on an interlayer insulating film, display unevenness due to non-uniform patterning of the transparent conductive film and display unevenness due to increased contact resistance are eliminated, Manufacturing yield can be improved.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a plan view conceptually showing the structure of a TFT substrate in a liquid crystal display device manufactured by the method for manufacturing a liquid crystal display device according to the first embodiment of the present invention. This embodiment is an example of an IPS liquid crystal display device.

  As shown in FIG. 1, a plurality of scanning lines 11, signal lines 12 orthogonal to the scanning lines 11, and adjacent scanning lines 11 are parallel to the scanning lines 11 on the opposite substrate side surface of the TFT substrate 10. And a common wiring 13 extending to. Thin film transistors (TFTs) 14 are formed in a matrix at intersections of the scanning lines 11 and the signal lines 12.

  A scanning line terminal 15 is provided at the end of the scanning line 11, and a drive signal from an external drive circuit is input to the scanning line 11 via the scanning line terminal 15. A signal line terminal 16 is provided at the end of the signal line 12, and a drive signal from an external drive circuit is input to the signal line 12 via the signal line terminal 16.

  The common wirings 13 are connected to each other in order to give a common potential as a reference for AC driving of the liquid crystal. That is, common wiring binding lines 17a and 17b extending in parallel with the signal line 12 are provided on both sides of the TFT substrate 10, and the common wiring binding line 17a is connected to one end of each common wiring 13 (for example, the left end). The common wiring bundling wire 17b connects the other ends (for example, right end portions) of the common wirings 13 to each other. A capacitance is formed between the common wiring 13 and the pixel electrode connected to the source electrode of the TFT 14. A common wiring terminal 18a is provided at the end of the common wiring binding line 17a, and a common wiring terminal 18b is provided at the end of the common wiring binding line 17b.

  2 is an enlarged plan view showing one pixel portion of the TFT substrate shown in FIG. 1, and FIGS. 3 (a), 3 (b), and 3 (c) respectively show lines 3A-3A and 3B in FIG. It is sectional drawing which follows a -3B line and 3C-3C line.

  As shown in FIG. 2, a pair of scanning lines 11 adjacent to each other and a pair of signal lines 12 adjacent to each other formed on the TFT substrate intersect with each other, and a display area surrounded by them is formed in each pixel portion. Partition. In each pixel portion, pixel electrodes 21 and common electrodes 22 formed in a comb-like shape are alternately arranged to face each other, and an electric field substantially parallel to the TFT substrate 10 between the pixel electrodes 21 and the common electrodes 22. And the alignment of liquid crystal molecules is controlled.

  As shown in FIG. 3, the TFT substrate includes a transparent insulating substrate 20, a scanning line 11 and a common wiring 13 formed on the transparent insulating substrate 20, and a transparent insulation so as to cover the scanning line 11 and the common wiring 13. A gate insulating film 31 formed on the conductive substrate 20, a thin film transistor (TFT) 14 formed on the gate insulating film 31, a passivation film 32 formed on the gate insulating film 31 so as to cover the TFT 14, and a passivation The organic insulating film 33 is formed on the film 32, and the pixel electrode 21 and the common electrode 22 are formed on the organic insulating film 33.

  The passivation film 32 and the organic insulating film 33 constitute an interlayer insulating film 38, and the pixel electrode 21 and the common electrode 22 are provided on the interlayer insulating film 38 as shown in FIGS. 3 (a) and 3 (c). It has been.

  The TFT 14 includes a gate electrode 23 formed on the transparent insulating substrate 20, a gate insulating film 31 covering the gate electrode 23, a source electrode 24 and a drain electrode 25 formed on the gate insulating film 31, and a source electrode 24. And a semiconductor layer 34 formed on the gate insulating film 31 between the drain electrode 25 and the drain electrode 25.

  In this embodiment, the TFT 14 is an example of an inverted staggered thin film transistor, and the gate electrode 23 of the TFT 14 is formed as a part of the scanning line 11 as shown in FIG. The drain electrode 25 is formed as a part of the signal line 12 as shown in FIG.

  As shown in FIG. 3A, the pixel electrode 21 is connected to the source electrode 24 of the TFT 14 through the contact hole 26 formed in the interlayer insulating film 38, and the common wiring 13 is connected to the source electrode 24 of FIG. As shown in c), the common electrodes 22 are connected through the contact holes 27 formed in the interlayer insulating film 38 and the gate insulating film 31, respectively.

  A scanning signal is input to the TFT 14 through the scanning line 11 and the gate electrode 23, and a display signal is input through the signal line 12 and the drain electrode 25, and charge is written to the pixel electrode 21.

  Further, as shown in FIGS. 3A and 3C, a storage capacitor is formed between the common wiring 13 and the storage capacitor electrode 35.

  Next, a manufacturing method of the TFT substrate in the first embodiment will be described.

  4, 6, 8, 10, 12, and 2 are plan views showing each manufacturing process of one pixel portion, and FIGS. 5, 7, 9, 11, 13, and 3 are 4, 6, 8, 10, 12, and 2, each AA line ((a) diagram), each BB line ((b) diagram), each CC line (( c) It is sectional drawing which follows a figure. Here, a cross-sectional portion along each AA line indicates a TFT portion, a contact hole portion for the pixel electrode, and a storage capacitor portion, a cross-sectional portion along each BB line indicates a pixel portion, and each CC line A cross-sectional portion along the line indicates a signal line portion, a common electrode contact hole portion, and a storage capacitor portion.

  First, as shown in FIGS. 4 and 5, about 100 conductive layers made of Cr, Mo, Cr / Al laminated film, Mo / Al laminated film, etc. are formed on a glass substrate or other transparent insulating substrate 20 by sputtering. A scanning line 11 including the gate electrode 23, a common wiring 13, a scanning line terminal portion (not shown), and a common wiring terminal portion (not shown) are formed by a photolithography process. .

  Next, as shown in FIGS. 6 and 7, transparent insulation is performed so as to cover the scanning line 11, the common wiring 13, the scanning line terminal portion (not shown), and the common wiring terminal portion (not shown) by plasma CVD. A gate insulating film 31 made of a silicon nitride film is formed on the conductive substrate 20 to a thickness of about 300 to 500 nm.

Further, amorphous silicon (a-Si) is formed on the gate insulating film 31 in a thickness of about 150 to 300 nm, and amorphous silicon doped with phosphorus (n ⁺ -type a-Si) is formed on the gate insulating film 31 with a thickness of about 30 to 50 nm. A semiconductor layer 34 that is to be an active layer of the TFT 14 is formed on the gate insulating film 31 by photolithography. A breakdown voltage improving semiconductor layer 64 is formed on the gate insulating film 31 at the same time as the semiconductor layer 34 at the intersection between the scanning line 11 and the common wiring 13 and the signal line 12.

  Next, as shown in FIGS. 8 and 9, a conductive layer made of Cr, Mo, Cr / Al / Cr laminated film, Mo / Al / Mo laminated film, etc. is gated to a thickness of about 100 to 400 nm by sputtering. A source electrode 24, a drain electrode 25, a storage capacitor electrode 35, a signal line 12, and a signal line terminal portion (not shown) are formed on the insulating film 31 by a photolithography process.

Subsequently, using the source electrode 24 and the drain electrode 25 as a mask, the n ⁺ type a-Si on the semiconductor layer 34 is removed by etching to form a channel.

  Next, as shown in FIGS. 10 and 11, the source electrode 24, the drain electrode 25, the semiconductor layer 34, the storage capacitor electrode 35, the signal line 12, and the signal line terminal portion (not shown) are covered by plasma CVD. Then, a passivation film 32 made of a silicon nitride film or other inorganic film is formed on the gate insulating film 31 to a thickness of about 100 to 300 nm.

  Thereafter, the substrate is annealed in a nitrogen atmosphere at a temperature of about 280.degree.

  Subsequently, an organic insulating film 33 having a film thickness of about 1.5 to 3.5 μm is formed on the passivation film 32 using a positive photosensitive novolac resist, and the organic insulating film 33 is formed by a photolithography process. After the openings 66 and 67 are formed in the contact hole forming portion, the organic insulating film 33 is baked at a temperature of about 230 ° C.

  Thereafter, as shown in FIGS. 12 and 13, the passivation film 32 is etched by a photolithography process to expose the pixel electrode contact hole 26 that exposes the source electrode 24 at a position corresponding to the opening 66 (FIG. 13A). And a contact hole (not shown) for exposing the metal film of the signal line terminal portion. At the same time, the passivation film 32 and the gate insulating film 31 are etched to expose the common wiring 13 at a position corresponding to the opening 67 (see FIG. 13C), and the scanning line terminal portion. A contact hole (not shown) that exposes the metal film and the metal film of the common wiring terminal portion and a contact hole (not shown) for the common wiring binding line that exposes an end portion of each common wiring 13 are formed. .

  This etching may be performed by dry etching or wet etching. Alternatively, wet etching and dry etching may be used in combination.

  Next, as shown in FIGS. 2 and 3, a transparent conductive film made of ITO is formed on the organic insulating film 33 by sputtering, and the pixel electrode 21, the common electrode 22, and the scanning line terminal portion are formed by a photolithography process. A metal film, a metal film of the signal line terminal part, a connection electrode (not shown) on the metal film of the common wiring terminal part, and a common wiring binding line (not shown) are formed.

  At this time, as shown in FIG. 3B, one of the common electrodes 22 is positioned on the organic insulating film 33 corresponding to the signal line 12, and the organic insulating film corresponding to the storage capacitor electrode 35. The pixel electrode 21 is formed so that one of the pixel electrodes 21 is positioned on the substrate 33. As a result, the pixel electrode 21 is connected to the source electrode 24 via the pixel electrode contact hole 26, the common electrode 22 is connected to the common wiring 13 via the common electrode contact hole 27, and The connection electrode is connected to the metal film of the scanning line terminal portion, the metal film of the signal line terminal portion, and the metal film of the common wiring terminal portion through the contact holes for the scanning line, the signal line, and the common wiring terminal portion, respectively. Further, the common wiring binding line is connected to the end of each common wiring 13 through the contact hole for the common wiring binding line (the structure of the terminal portion will be described later).

  Here, the ITO film is formed by reactive sputtering in an atmosphere of Ar gas and oxygen gas. Oxygen gas is mixed with about 1 to 5 atom% with respect to Ar gas. Furthermore, about 1 atomic% of water or hydrogen may be added to the Ar gas. Further, the substrate is not heated at the time of film formation, and annealing after the film formation is not performed. Thereby, an amorphous ITO film can be formed.

  Etching of the amorphous ITO film is performed by wet etching using aqua regia or an oxalic acid-based etchant. When a minute amount of water or hydrogen is added during film formation, etching without etching residue can be easily performed. The etching time of the amorphous ITO film may be an appropriate time depending on the etching rate of the film, and the both sides of the line width of the ITO film after etching are subtracted from the line width of the photoresist after photoresist development. The etching amount can be controlled to about 1 μm on the organic insulating film.

  Next, the structure of the terminal portion of the TFT substrate in the first embodiment will be described.

  14 is a plan view of the terminal portion around the substrate, and FIG. 15A is a cross-sectional view taken along the line 15A-15A in FIG. 14, showing the scanning line terminal and the common wiring terminal. b) is a cross-sectional view taken along line 15B-15B in FIG. 14 and shows signal line terminals.

  As shown in FIG. 15A, the scanning line terminal and the common wiring terminal are the same as the common electrode on the terminal part metal film 41 formed on the transparent insulating substrate 20 with the same metal film as the scanning line 11. The connection electrode 42 is formed of a transparent conductive film (ITO film).

  Further, as shown in FIG. 15B, the signal line terminal is the same transparent conductive material as the common electrode on the terminal metal film 81 formed on the gate insulating film 31 with the same metal film as the signal line 12. The connection electrode 82 is formed of a film (ITO film).

  Here, the connection electrode 42 has a structure connected to the terminal metal film 41 through the terminal contact hole 43 opened in the gate insulating film 31 and the passivation film 32, and the connection electrode 82 is connected to the passivation film 32. The terminal part metal film 81 is connected through a terminal part contact hole 83 that is opened to the terminal part. Thus, the organic insulating film 33 is not formed on each terminal portion.

  Here, the side etching amount of the ITO film on the passivation film 32 is smaller than the side etching amount of the ITO film on the organic insulating film 33. Therefore, since the side etching amount of the ITO film on the organic insulating film 33 is controlled to about 1 μm on both sides, there is no practical problem.

  Each common wiring 13 is connected to the common wiring binding wires 17a and 17b via the common wiring binding wire contact hole 44 (see FIG. 14). Although the sectional structure of the contact hole 44 is not shown, it has a structure similar to that of the terminal contact hole 43 shown in FIG.

  Here, an example is shown in which the common wiring binding lines 17 a and 17 b are formed of a transparent conductive film, but the common wiring binding lines 17 a and 17 b can be formed of the same metal film as the signal line 12.

  Although not shown, part of the common wiring bundling lines 17 a and 17 b is drawn on the organic insulating film 33 by a transparent conductive film through a contact hole opened in the passivation film 32. Further, the end portions of the common wiring binding lines 17 a and 17 b are drawn out on the organic insulating film 33 by the same transparent conductive film through contact holes opened in the gate insulating film 31 and the passivation film 32. In this way, the common wiring bundling lines 17a and 17b and the respective common wirings 13 can be connected via the transparent conductive film. By adopting such a structure, it is possible to reduce the resistance of the common wiring bundling wires 17a and 17b.

  Next, a method for manufacturing a liquid crystal panel in which liquid crystal is sandwiched between the TFT substrate and the counter substrate in the first embodiment will be schematically described.

  FIG. 16 is a cross-sectional view of one pixel portion of the liquid crystal panel. The liquid crystal panel shown in FIG. 16 includes the above-described TFT substrate 10, a counter substrate 50 disposed to face the TFT substrate 10, and a liquid crystal layer 55 sandwiched between the TFT substrate 10 and the counter substrate 50. , Is composed of.

  The counter substrate 50 is a glass substrate or other transparent insulating substrate 30, a black matrix 52 formed on the surface of the transparent insulating substrate 30 facing the TFT substrate 10, and a transparent insulation so as to cover the black matrix 52. The three color filters 53R, 53G, 53B formed on the conductive substrate 30, the overcoat film 54 formed on the color filters 53R, 53G, 53B, and the TFT substrate 10 of the transparent insulating substrate 30 are opposite. And a transparent conductive layer 56 formed on the side surface.

  The TFT substrate 10 and the counter substrate 50 are formed as follows.

  After forming the TFT substrate 10 as described above, an alignment film 51 having a film thickness of 30 to 60 nm made of a polyimide-based alignment agent is formed on the organic insulating film 33 of the TFT substrate 10, and a temperature of 180 ° C. to 240 ° C. Is fired to perform orientation treatment.

  Thereafter, a sealing material (not shown) made of an epoxy resin adhesive is formed along the periphery of the TFT substrate 10. Firing after the formation of the alignment film 51 also serves as annealing of the transparent conductive film. That is, by baking after forming the alignment film 51, the amorphous ITO film can be polycrystallized, the transmittance of the ITO film can be improved, and the resistance value can be reduced.

  Next, an ITO or other transparent conductive layer 56 having a thickness of about 80 to 150 nm is formed on the surface of the transparent insulating substrate 30 constituting the counter substrate 50 opposite to the surface on which the color filters 53R, 53G, and 53B are formed. Form a film.

  Next, a negative photosensitive acrylic pigment dispersion resist or carbon resist is used on the surface of the transparent insulating substrate 30 facing the TFT substrate 10 to have a film thickness of about 1 to 3 μm and an optical density (OD value). A black matrix 52 having a sheet resistance value of 3 × 10 10 Ω / □ or more is formed.

  Next, a red color filter 53R having a film thickness of about 1.0 to 1.5 μm is formed using a negative photosensitive acrylic pigment dispersion resist. Similarly, the color layers of the blue color filter 53B and the green color filter 53G are formed.

  Next, an overcoat film 54 made of an organic insulating film having a thickness of about 2.0 to 3.5 μm is formed using a novolac resist.

  Further, an alignment film 51 having a film thickness of 30 to 60 nm made of a polyimide-based alignment agent is formed thereon, and after baking, an alignment process is performed to form the counter substrate 50.

  Thereafter, the counter substrate 50 is overlaid on the TFT substrate 10 via a sealing material and an in-plane spacer (not shown).

  Subsequently, a liquid crystal 55 made of a fluorine-based compound is injected between both substrates through an injection port (not shown), and then the injection port is sealed with a sealing material (not shown) made of a UV curable acrylate resin. Stop and get a panel with a certain gap. The gap may be controlled using, for example, a columnar color filter (not shown) made of an acrylic resin.

  Finally, a polarizing plate 57 made of an iodine polarizing film is attached to the surface of the TFT substrate 10 opposite to the element surface and the surface of the counter substrate 50 opposite to the color filter.

  Thereby, a liquid crystal panel having a wide viewing angle and a high aperture ratio using the above-described TFT substrate 10 is manufactured.

  As described above, according to the present embodiment, the amorphous ITO film is patterned on the organic insulating film, and the ITO film is polycrystallized by baking after forming the alignment film, thereby patterning the ITO film. It can be performed accurately and uniformly (described later).

  Further, in the TFT substrate manufacturing process, the heat treatment (annealing) process can be reduced by one process.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. In the second embodiment, plasma processing is performed on the organic insulating film 33.

  Since the manufacturing method up to the step of forming the organic insulating film 33 in FIGS. 2, 3 to 10 and 11 is exactly the same as that in the first embodiment, the description thereof will be omitted.

  After the formation of the organic insulating film 33, helium (He) plasma treatment is performed on the entire surface of the substrate. This helium plasma treatment is performed by high-frequency discharge of He gas in a dry etching apparatus.

  Thereafter, as shown in FIGS. 12 and 13, the passivation film 32 is etched by a photolithography process to expose the pixel electrode contact hole 26 that exposes the source electrode 24 at a position corresponding to the opening 66 (FIG. 13A). And a contact hole (not shown) for exposing the signal line terminal portion. At the same time, the passivation film 32 and the gate insulating film 31 are etched to expose the common wiring 13 at a location corresponding to the opening 67 (see FIG. 13C), and the scanning line terminal portion. A contact hole (not shown) for exposing the metal film of the common wiring terminal portion and a metal film of the common wiring terminal portion, and a contact hole (not shown) for a common wiring binding line for exposing the end portion of each common wiring 13, respectively. Form.

  This etching may be performed by dry etching or wet etching. Alternatively, wet etching and dry etching may be used in combination.

  However, when the contact hole is opened by dry etching, post-baking after photoresist development is not performed. When the contact hole is opened by wet etching, or when dry etching is performed after wet etching, post-baking after photoresist development is performed at a temperature of about 140 ° C.

  Next, as shown in FIGS. 2, 3, and 14 to 16, a transparent conductive film made of ITO is formed on the organic insulating film 33 by sputtering, and the pixel electrode 21 and the common electrode are formed by a photolithography process. 22, connection electrodes 42 and 82 on the metal film 41 of the scanning line terminal portion and the common wiring terminal portion, and the metal film 81 of the signal line terminal portion, and common wiring binding wires 17 a and 17 b are formed.

  At this time, as shown in FIG. 3B, one of the common electrodes 22 is positioned on the organic insulating film 33 corresponding to the signal line 12, and the organic insulating film corresponding to the storage capacitor electrode 35. The pixel electrode 21 is formed so that one of the pixel electrodes 21 is positioned on the substrate 33. As a result, the pixel electrode 21 is connected to the source electrode 24 via the pixel electrode contact hole 26, the common electrode 22 is connected to the common wiring 13 via the common electrode contact hole 27, and The connection electrodes 42 and 82 are connected to the scanning line terminal portion, the common wiring terminal portion, and the signal line terminal portion contact holes 43 and 83 through the scanning line terminal portion, the common wiring terminal portion metal film 41, and the signal line terminal portion metal film 81, respectively. Furthermore, the common wire binding wires 17a and 17b are connected to the end portions of the common wires 13 through the contact holes 44 for the common wire binding wires.

  Here, the ITO film forming conditions are the same as those in the first embodiment.

  The transparent conductive film may be an indium zinc oxide film (IZO) instead of ITO. In the case of IZO, an amorphous film is formed regardless of the film formation conditions.

  Hereinafter, the manufacturing method of the liquid crystal panel in which the liquid crystal 55 is sandwiched between the TFT substrate 10 and the counter substrate 50 in the second embodiment is exactly the same as that in the first embodiment, and thus the description thereof is omitted. .

  As described above, by performing He plasma treatment on the organic insulating film before opening the contact hole in the inorganic insulating film, the transparent conductive film can be patterned accurately and uniformly, and at the same time, the transparent conductive film An increase in contact resistance between the film and the base metal film can be prevented (this will be described later).

  Table 1 is a table showing the relationship between the film quality of the ITO film and the etching quality (line width shift, pattern chipping).

ＩＴＯ成膜時に２００℃程度の温度に加熱したり、ＩＴＯ膜成膜後に２００℃程度の温度で熱処理を行った場合、ＩＴＯ膜の膜質は多結晶となる。この場合、ＩＴＯ膜のエッチングレートは遅くなり、残渣も発生しやすくなるため、エッチング時間は長く設定する必要がある。エッチングによる有機絶縁膜上のＩＴＯ膜のサイドエッチング量は１μｍ程度に制御することが可能であり、有機及び無機絶縁膜上のＩＴＯ膜の線幅シフトは問題ない（○印は問題なしを意味する）。

When the ITO film is heated to a temperature of about 200 ° C. or heat-treated at a temperature of about 200 ° C. after the ITO film is formed, the film quality of the ITO film becomes polycrystalline. In this case, the etching rate of the ITO film becomes slow and residue is likely to be generated, so the etching time needs to be set long. The side etching amount of the ITO film on the organic insulating film by etching can be controlled to about 1 μm, and there is no problem in the line width shift of the ITO film on the organic and inorganic insulating films. ).

  However, according to an experiment by the present inventor, it has been found that the ITO film on the organic film lacks a pattern (a cross indicates that there is a problem). This is presumably because the film quality of the polycrystalline ITO film is partially non-uniform.

  On the other hand, as in the present invention, when the ITO film is not heated, or when it is further performed in an atmosphere containing about 1 atomic% of water or hydrogen, the film quality of the ITO film becomes amorphous. In this case, the etching rate of the ITO film is increased and no residue is generated. The etching time may be set short according to the etching rate of the ITO film, and the side etching amount of the ITO film on the organic insulating film by etching can be controlled to about 1 μm, and the ITO on the organic and inorganic insulating films can be controlled. There is no problem with the line width shift of the film (circles). In addition, pattern chipping of the ITO film could be prevented (circle mark).

  Table 2 shows the relationship between the plasma treatment and the uniformity of the etching of the ITO film and the contact resistance between the ITO film and the base metal film when the organic insulating film is subjected to the plasma treatment after opening the contact hole.

ＩＴＯ膜のエッチングの均一性は、第１及び第２の実施形態に示したＩＰＳ型液晶表示装置における共通電極と画素電極の出来栄えと、エッチング不均一に起因する表示ムラの有無とにより判定し、ＩＴＯ膜と下地金属膜間のコンタクト抵抗は、第１及び第２の実施形態に示したＩＰＳ型液晶表示装置におけるＩＴＯ膜と共通配線の金属膜、信号線の金属膜（ここでは何れもＣｒ）との間のコンタクト抵抗値と、このコンタクト抵抗に起因する表示ムラの有無とにより判定したものである。

The uniformity of the etching of the ITO film is determined by the quality of the common electrode and the pixel electrode in the IPS liquid crystal display device shown in the first and second embodiments, and the presence or absence of display unevenness due to the etching non-uniformity, The contact resistance between the ITO film and the underlying metal film is the same as the ITO film, the common wiring metal film, and the signal metal film (here, Cr) in the IPS liquid crystal display device shown in the first and second embodiments. And the presence / absence of display unevenness caused by the contact resistance.

  According to the experiment of the present inventor, according to the Ar plasma treatment, the uniformity of etching of the ITO film is very good (circle mark), and the contact resistance is not treated if the conditions close to the sputter etching are selected. Compared to the case, it was reduced (○ mark).

  According to the He plasma treatment, the uniformity of etching of the ITO film was very good (circle mark), but the contact resistance increased (x mark) compared to the case without treatment. This is probably because the effect of sputter etching cannot be obtained.

According to the O ₂ plasma treatment, the uniformity of etching of the ITO film was the same as that without treatment, and no improvement effect was observed (-mark). The contact resistance is slightly improved as compared with the case without treatment, but the display unevenness due to the contact resistance cannot be improved (Δ mark).

According to the plasma treatment of CF _{4 and} other fluorine-based gases, the uniformity of etching of the ITO film and the contact resistance were deteriorated as compared with the case where the treatment was not performed (× mark).

  Therefore, it was found from the above results that the He plasma treatment needs to be performed before the contact hole is opened.

  Furthermore, according to the experiments of the present inventors, if the post-baking is performed after developing the photoresist in the contact hole opening process shown in the first and second embodiments, the uniformity of etching of the ITO film may be deteriorated. found. The reason for this is not clear, but post-baking improves the adhesion between the organic insulating film and the photoresist, and when removing the photoresist after opening the contact hole, part of the surface on the organic insulating film is also removed. Therefore, it is presumed that the new surface of the organic insulating film is affected by the stripping solution and deteriorates the adhesion with the ITO film to be formed next.

  Therefore, when the contact hole is opened by dry etching, it is preferable not to perform post-baking.

  On the other hand, when the contact hole is opened by wet etching, or when wet etching and dry etching are used in combination, it is necessary to perform post-bake. Therefore, it is preferable to perform He plasma treatment before opening the contact hole. I understood it. However, when wet etching is used for opening the contact hole, the He plasma treatment is likely to cause the penetration of the etchant, and therefore it is necessary to optimize the He plasma treatment and the post-bake conditions.

  In the first and second embodiments described above, the example in which the interlayer insulating film 38 is formed of a laminated film of the inorganic insulating film 32 and the organic insulating film 33 has been described. Patterns are formed only on the lines 12 or on the signal lines 12 and the scanning lines 11. That is, the interlayer insulating film 38 may be formed of a laminated film of the inorganic insulating film 32 and the organic insulating film 33 only in this region, and the interlayer insulating film 38 may be formed of a single layer of the inorganic insulating film 32 in other regions.

  In the first embodiment, the interlayer insulating film 38 is formed of the laminated film of the inorganic insulating film 32 and the organic insulating film 33, but may be formed of only the organic insulating film 33.

  In the first and second embodiments, an example is shown in which the common electrode 72 is formed so as to cover a part of the signal line 12 except for the intersection of the scanning line 11 and the signal line 12. However, it may be formed so as to cover the entire signal line 12 including the intersection of the scanning line 11 and the signal line 12, or it may be formed so as to cover both the scanning line 11 and the signal line 12. May be.

  In the above-described embodiment, the example in which the present invention is applied to the IPS liquid crystal display device has been described. However, the present invention can be applied to any liquid crystal display device in which a transparent conductive film is formed on an organic insulating film. The present invention can also be applied to such a liquid crystal display device. For example, the present invention can be applied to a TN (Twisted Nematic) type or VA (Vertical Alignment) type liquid crystal display device.

  In the above-described embodiment, an example in which the organic insulating film 33 such as a photosensitive novolak resist is used has been described. However, a polyimide resin or an acrylic resin can be used instead.

  Further, a non-photosensitive organic insulating film can be used instead of the photosensitive organic insulating film. In this case, an etching process and a resist stripping process are required after development, as in a normal photolithography process.

  In addition, although the example in which the opening process of the organic insulating film and the opening process of the passivation film are separate photolithography processes has been described, the opening may be performed in the same photolithography process.

  In the above-described embodiment, the liquid crystal display device having an inverted staggered channel etch type TFT has been described. However, a channel protection type or a forward stagger type TFT may be used, and not only a staggered type TFT but also a coplanar type TFT. Needless to say, it can also be applied.

  Further, the present invention can be applied not only to an amorphous (a-Si) TFT but also to a polysilicon (p-Si) TFT.

  Further, as the switching element, MIM can be used instead of TFT.

1 is a plan view conceptually showing a configuration of a TFT substrate in a lateral electric field type liquid crystal display device manufactured by a method for manufacturing a liquid crystal display device according to a first embodiment of the present invention. It is a top view which expands and shows 1 pixel part of the TFT substrate of FIG. It is sectional drawing which follows the 3A-3A line | wire, 3B-3B line | wire, and 3C-3C line | wire of FIG. FIG. 4 is a process plan view (first process) of one pixel portion for explaining an example of a method for manufacturing a liquid crystal panel using the TFT substrate of FIG. 1. It is process sectional drawing which follows the 5A-5A line | wire, 5B-5B line | wire, and 5C-5C line | wire of FIG. It is a process top view (2nd process) of 1 pixel part explaining an example of the manufacturing method of the liquid crystal panel using the TFT substrate of FIG. It is process sectional drawing which follows the 7A-7A line of FIG. 6, the 7B-7B line, and the 7C-7C line. It is a process top view (3rd process) of 1 pixel part explaining an example of the manufacturing method of the liquid crystal panel using the TFT substrate of FIG. It is process sectional drawing which follows the 9A-9A line of FIG. 8, 9B-9B line, and 9C-9C line. It is a process top view (4th process) of 1 pixel part explaining an example of the manufacturing method of the liquid crystal panel using the TFT substrate of FIG. It is process sectional drawing which follows the 11A-11A line of FIG. 10, the 11B-11B line, and the 11C-11C line. It is a process top view (5th process) of 1 pixel part explaining an example of the manufacturing method of the liquid crystal panel using the TFT substrate of FIG. It is process sectional drawing which follows the 13A-13A line of FIG. 12, the 13B-13B line, and the 13C-13C line. It is a top view of the terminal part around the TFT substrate of FIG. 15A is a cross-sectional view taken along the line 15A-15A in FIG. 14, and FIG. 15B is a cross-sectional view taken along the line 15B-15B in FIG. It is sectional drawing of the 1 pixel part of the liquid crystal panel using the TFT substrate of FIG.

Explanation of symbols

10 TFT substrate 20, 30 Transparent insulating substrate 11 Scan line 12 Signal line 13 Common wiring 14 TFT
15 Scan line terminal 16 Signal line terminal 17a, 17b Common wiring bundling line 18a, 18b Common wiring terminal 21, 71 Pixel electrode 22, 72 Common electrode 23 Gate electrode 24 Source electrode 25 Drain electrode 26, 27, 44, 96, 97 Contact Hole 31 Gate insulating film 32 Passivation film 33 Organic insulating film 34 Semiconductor layer 35 Storage capacitor electrode 38 Interlayer insulating film 41, 81 Terminal part metal film 42, 82 Connection electrode 43, 83 Terminal part contact hole 50 Counter substrate 51 Alignment film 52 Black Matrix 53R, 53G, 53B Color filter 54 Overcoat film 55 Liquid crystal layer 56 Transparent conductive layer 57 Polarizing plate 64 Withstand voltage improving semiconductor layer 66, 67 Opening

Claims (6)

A first step of forming a switching element on the substrate, a second step of covering the switching element with an interlayer insulating film having an upper layer made of at least an organic insulating film, and connecting to the switching element via the interlayer insulating film A third step of forming a transparent electrode on the interlayer insulating film, and a method for manufacturing a liquid crystal display device,
The interlayer insulating film is configured to have the organic insulating film on an inorganic insulating film,
The third step includes
Patterning the organic insulating film;
Applying plasma treatment to the substrate including the organic insulating film;
Opening a contact hole in the inorganic insulating film;
Depositing a transparent conductive film on the interlayer insulating film;
Patterning the transparent conductive film to form a transparent electrode;
A method of manufacturing a liquid crystal display device comprising:   2. The liquid crystal display according to claim 1, wherein in the step of patterning the organic insulating film, the organic insulating film is patterned so as to cover at least a part of a signal line including a drain electrode of the switching element. Device manufacturing method. The first step includes
Forming a scanning line including a gate electrode and a common wiring for supplying a common potential on the substrate;
Forming a gate insulating film on the substrate so as to cover the scanning line and the common wiring;
Forming a semiconductor layer serving as an active layer of the switching element on the gate insulating film;
Forming a signal line that intersects the scanning line and includes a drain electrode of the switching element, and a source electrode of the switching element,
The step of patterning the transparent conductive film to form a transparent electrode includes:
2. The method according to claim 1, further comprising a step of patterning the transparent conductive film to form a pixel electrode connected to the switching element and a common electrode connected to the common wiring on the interlayer insulating film. Or the manufacturing method of the liquid crystal display device of 2.   The method for manufacturing a liquid crystal display device according to claim 1, wherein the plasma treatment is performed using helium (He) plasma. Opening the contact hole in the inorganic insulating film,
Patterning a photoresist on the interlayer insulating film;
Post-baking the photoresist;
Performing wet etching or both wet etching and dry etching on the inorganic insulating film using the photoresist as a mask;
5. The method for manufacturing a liquid crystal display device according to claim 1, comprising:   6. The method for manufacturing a liquid crystal display device according to claim 1, wherein the transparent conductive film is formed of an indium tin oxide film (ITO) or an indium zinc oxide film (IZO).

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