KR20050011476A - Liquid crystal display - Google Patents

Abstract

PURPOSE: An LCD is provided to form pixel electrodes and data lines on different substrates for increasing an area of each of the pixel electrodes without any increase of parasitic capacitance generated by the overlapping between the pixel electrodes and the data lines. CONSTITUTION: An LCD includes a lower display plate and an upper display plate facing the lower one. The lower display plate has a first insulating substrate formed with a plurality of gate lines(121,122), gate electrodes connected to the gate lines, a plurality of thin film transistors formed of drain and source electrodes(175,173), a plurality of pixel electrodes(190) connected to the drain electrodes, and a plurality of column spacers(320) connected to the source electrodes. The upper display plate has a second insulating substrate formed with a plurality of color filters, common electrodes facing the pixel electrodes, and data lines(171). Via conductive contact holes, the data lines contact the column spacers. Each of the pixel electrodes is apart from the data lines, so that a distance between the pixel electrodes is minimized for increasing an aperture rate, regardless of a parasitic capacitance caused by the overlapping with the data lines.

Description

Liquid crystal display

The present invention relates to a liquid crystal display device.

In general, a liquid crystal display device includes a liquid crystal layer having a field generating electrode for generating an electric field and having an anisotropic dielectric constant injected into two display panels spaced apart from each other with a predetermined gap and a gap between the two display panels. Such a liquid crystal display generates an electric field in the liquid crystal layer by applying a voltage to the field generating electrode, and displays an image by controlling the transmittance of light passing through the liquid crystal layer by adjusting the intensity of the electric field depending on the magnitude of the voltage.

Among the liquid crystal display devices, a liquid crystal display device including a thin film transistor for forming an electrode on each of two display panels and switching a voltage applied to the electrode is used. One of the two display panels includes a pixel electrode and a thin film transistor for switching a voltage applied thereto, and a gate line and a data line for transmitting a signal to the thin film transistor (hereinafter referred to as a thin film transistor display panel), and the other display panel includes a pixel electrode. It is common to provide a common electrode facing and a color filter of red (R), green (G), and blue (B).

In order to improve the brightness of such a liquid crystal display device, it is important to secure a high aperture ratio. To this end, a method of improving the aperture ratio by overlapping a pixel electrode connected to a drain electrode of a thin film transistor array panel with a gate line and a data line has been proposed.

However, in such a structure, there is a problem in that parasitic capacitance is increased due to overlap of the pixel electrode and the data line.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a liquid crystal display device capable of reducing parasitic capacitance between a pixel electrode and a data line while improving an aperture ratio.

1 is a layout view of a liquid crystal display according to an exemplary embodiment of the present invention.

2A to 2C are cross-sectional views of the liquid crystal display shown in FIG. 1 taken along lines IIa-IIa ', IIb-IIb', and IIc-IIc '.

3A to 6B are cross-sectional views at intermediate stages of a method of manufacturing an upper panel in accordance with an embodiment of the present invention, respectively, in the liquid crystal display shown in FIGS.

7, 10 and 12 are layout views in an intermediate step of a method of manufacturing a lower panel (thin film transistor array panel) according to an embodiment of the present invention in the liquid crystal display device shown in FIGS. 1 to 2C, respectively. Drawing as listed,

8A to 8C are cross-sectional views taken along the lines VIIIa-VIIIa ', VIIIb-VIIIb', and VIIIc-VIIIc 'of the thin film transistor array panel of FIG. 7, respectively.

9A to 9C are cross-sectional views taken along the lines VIIIa-VIIIa ', VIIIb-VIIIb', and VIIIc-VIIIc 'of the thin film transistor array panel of FIG. 7, respectively. ,

11A through 11C are cross-sectional views of the thin film transistor array panel of FIG. 10 taken along lines XIa-XIa ', XIb-XIb', and XIc-XIc ', respectively.

13A to 13C are cross-sectional views of the thin film transistor array panel of FIG. 12 taken along lines XIIIa-XIIIa ', XIIIb-XIIIb', and XIIIc-XIIIc ', respectively.

In order to achieve the above object, the present invention provides the following liquid crystal display device.

More specifically, a plurality of thin film transistors each comprising a first insulating substrate, a plurality of gate lines insulated from each other formed on the first substrate, a gate electrode connected to the gate line, a drain electrode, and a source electrode, and the drain electrode A lower display panel including a plurality of pixel electrodes connected to the first electrode and a plurality of columnar spacers connected to the source electrode, a second insulating substrate facing the first insulating substrate, and formed on the second insulating substrate. An upper display panel including a data line extending to cross the gate line, a plurality of color filters formed on the second substrate, and a common electrode facing the pixel electrode, and the data line and the columnar spacer; A liquid crystal display device including a conductive contact hole for contacting is provided.

The columnar spacer is preferably made of the same dry etching material as the data line.

The light emitting device may further include a plurality of light blocking members formed of the same layer as the data line and positioned between the data lines.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is over another part, this includes not only the part directly above the other part but also another part in the middle. In contrast, when a part is just above another part, it means that there is no other part in between.

A liquid crystal display according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a layout view of a liquid crystal display according to an exemplary embodiment of the present invention, and FIGS. 2A to 2C are lines IIa-IIa ', IIb-IIb', and IIc-IIc 'of the liquid crystal display shown in FIG. 1. It is a cross-sectional view cut along.

As shown in FIGS. 1 to 2C, the liquid crystal display according to the present exemplary embodiment may face the lower display panel 100 and the upper display panel 200 spaced apart from each other with a predetermined gap, and the upper display panel 200 and the lower display panel. And a liquid crystal layer 3 filled in the gap between the layers 100.

First, the upper panel 200 will be described.

In the upper panel 200, a plurality of data lines 171 and a plurality of light blocking members 172 are formed on the insulating substrate 210.

The data line 171 extends mainly in the vertical direction and transmits a data voltage. The data line 171 has a contact portion 87 in the form of a groove.

The light blocking member 172 is spaced apart from each other by a predetermined distance between the neighboring data lines 171 and mainly extends in the horizontal direction.

The data line 171 and the light blocking member 172 include a conductive film made of a silver-based metal such as silver (Ag) or a silver alloy having low resistivity, or an aluminum-based metal such as aluminum (Al) or an aluminum alloy. In addition to the conductive film, chromium (Cr), titanium (Ti), tantalum (Ta) and molybdenum (Mo) have good physical, chemical and electrical contact properties with other materials, especially indium tin oxide (ITO) or indium zinc oxide (IZO). And other conductive films made of alloys thereof (eg, molybdenum-tungsten (MoW) alloys). An example of the combination of the lower layer and the upper layer is chromium / aluminum-neodymium (Nd) alloy.

A plurality of red, green, and blue color filters 230 are formed on the data line 171 and the light blocking member 172. The color filter 230 partially overlaps the data line 171 and does not cover the contact portion 87 of the data line 171.

The common electrode 270 is formed on the color filter 230. The common electrode 270 is made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), and receives a common voltage. The common electrode 270 covers the entire surface of the display panel 200 and has an opening that exposes the contact portion 87.

An upper alignment layer 21 is formed on the common electrode 270 and the data line 171.

Finally, a conductive contact ball 50 is coated on the upper alignment layer 21 corresponding to the contact portion 87 of the data line 171.

The lower panel 100 will be described in detail.

A plurality of gate lines 121 and 122 and a plurality of gate connections 128 connecting the pair of gate lines 121 and 122 are formed on the insulating substrate 110.

The gate lines 121 and 122 transmit gate signals and mainly extend in the horizontal direction. A portion of each gate line 121 protrudes downward to form a gate electrode 124, and each pair of gate lines 121 and 122 is connected to a plurality of pairs of connection portions 128.

Like the data line 171, the gate lines 121 and 122 and the gate connecting portion 128 include a conductive film made of a silver-based metal or an aluminum-based metal having a low resistivity. It may have a multilayer film structure including other conductive films made of chromium (Cr), titanium (Ti), tantalum (Ta), molybdenum (Mo), and alloys thereof having good contact properties.

Sides of the gate line 121 and the gate connection portion 128 are inclined, and the inclination angle is in a range of about 30-80 ° with respect to the surface of the substrate 110.

A gate insulating layer 140 made of silicon nitride (SiNx) is formed on the gate line 121 and the gate connection portion 128.

A plurality of island semiconductors 154 and 159 made of hydrogenated amorphous silicon (amorphous silicon is abbreviated a-Si) and the like are formed on the gate insulating layer 140. The island semiconductor 159 is positioned near the upper edge of the display panel 100.

On top of the semiconductors 154 and 159, a plurality of island-like ohmic contacts 163, 165 and 169 made of a material such as n + hydrogenated amorphous silicon doped with a high concentration of silicide or n-type impurities are formed. Formed. The island contact members 163 and 165 are paired and positioned over the semiconductor 154, and the ohmic contact member 169 is positioned over the island semiconductor 159.

Sides of the semiconductors 154 and 159 and the ohmic contacts 163, 165 and 169 are also inclined, and the inclination angle is 30 to 80 degrees.

A plurality of source electrodes 173, a plurality of drain electrodes 175, and a plurality of data connectors 179 are formed on the ohmic contacts 163, 165, and 169, respectively.

The pair of source electrode 173 and the drain electrode 175 are separated from each other and positioned opposite to the gate electrode 124. The gate electrode 124, the source electrode 173, and the drain electrode 175 form a thin film transistor (TFT) together with the semiconductor 154, and a channel of the thin film transistor is connected to the source electrode 173. It is formed in the semiconductor 154 between the drain electrode 175.

The data line connector 179 is connected to the uppermost source electrode 173 and is exposed to the outside of the upper panel 200.

The source electrode 173, the drain electrode 175, and the connection part 179 also include a conductive film made of a silver-based metal or an aluminum-based metal. In addition to the conductive film, chromium (Cr), titanium (Ti), and tantalum (Ta) may be used. ), Molybdenum (Mo), and other alloys made of such alloys may have a multilayer film structure. Sides of the source electrode 173, the drain electrode 175, and the connection portion 179 are also inclined, and the inclination angle is in the range of about 30-80 ° with respect to the horizontal plane.

On the source electrode 173, the drain electrode 175 and the connection portion 179 and the exposed portion of the semiconductor 154, an organic material having excellent planarization characteristics and photosensitivity, plasma enhanced chemical vapor deposition , A passivation layer 180 made of a low dielectric constant insulating material such as a-Si: C: O, a-Si: O: F, or silicon nitride, which is an inorganic material, is formed by PECVD.

The ohmic contacts 163, 165, and 169 exist only between the semiconductors 154 and 159 thereunder and the source electrode 173, the drain electrode 175, and the data connection 179 therebetween, and the contact therebetween. It lowers resistance. The semiconductors 154 and 159 may be substantially connected to the source electrode 173, the drain electrode 175, the data connection 179, and the ohmic contacts 163, 165, and 169 under the thin film transistor. It has the same planar shape. In particular, the island semiconductor 159, the data connection 179, and the island resistive contact member 169 have substantially the same planar shape. Alternatively, the island-type semiconductor 154 may include the source electrode 173 and the drain electrode 175 in addition to the portions that exist under the source electrode 173 and the drain electrode 175 and the ohmic contacts 163 and 165 thereunder. It is located in between and has exposed parts.

The passivation layer 180 is formed with a plurality of contact holes 182, 183, and 185 exposing the connection portion 179, the source electrode 173, and the drain electrode 175, respectively.

A plurality of pixel electrodes 190 and a plurality of contact assistants 82 made of ITO or IZO are formed on the passivation layer 180.

The pixel electrode 190 is physically / electrically connected to the drain electrode 175 through the contact hole 185 to receive a data voltage from the drain electrode 175.

The pixel electrode 190 to which the data voltage is applied rearranges the liquid crystal molecules of the liquid crystal layer 3 between the two electrodes 190 and 270 by generating an electric field together with the common electrode 270 of the upper panel 200.

In addition, the pixel electrode 190 and the common electrode 270 form a capacitor (hereinafter referred to as a liquid crystal capacitor) to maintain an applied voltage even after the thin film transistor is turned off. There are other capacitors connected in parallel with the capacitor, which are called storage electrodes. The storage capacitor is formed by the superposition of the pixel electrode 190 and the neighboring gate lines 121 and 122 (this is called a prior gate line), and the like to increase the capacitance of the storage capacitor, that is, the storage capacitor. The drain electrode 175 connected to the electrode 190 is overlapped with the gate line 122 to close the substantial distance between the two, while the drain electrode 175 is extended at the overlapping portion to increase the overlap area.

Each pixel electrode 190 is mainly located between the pair of gate lines 121 and 122 and overlaps the gate lines 121 and 122 and the gate connection portion 128. Since the pixel electrode 190 is far from the data line 171 provided in the upper panel 200, the distance between the pixel electrodes 190 is maximized without having to worry about parasitic capacitance due to overlapping with the data line 171. It is possible to increase the aperture ratio by making it close.

The contact auxiliary member 82 is connected to the data line connector 179 through the contact hole 182. The contact assisting member 82 is not essential to complement and protect the adhesion between the data line connecting portion 179 and the external device, and application thereof is optional.

On the contact hole 183 of the passivation layer 180, a columnar spacer 320 made of the same material as the data line 171, in particular, a material capable of dry etching is formed.

Finally, an alignment layer 11 is formed on the pixel electrode 190 and the passivation layer 180.

A plurality of conductive contact holes may be formed between the alignment layer 11 on the columnar spacer 320 of the lower panel 100 and the alignment layer 21 on the contact portion 87 of the data line 171 of the upper panel 200. 50) is located.

The conductive contact hole 50 penetrates through the alignment layers 11 and 21 to contact the contact portion 87 of the data line 171 and the columnar spacer 320. As a result, the data line 171 and the source electrode 173 are electrically connected to each other through the conductive contact hole 50 and the columnar spacer 320.

The light blocking member 172 of the upper panel 200 covers a gap between the upper and lower pixel electrodes 190 of the lower panel 100 to prevent light leakage.

Next, a method of manufacturing the upper panel 200 and the lower panel 100 for a liquid crystal display according to the exemplary embodiment of the present invention will be described.

First, a method of manufacturing the upper panel of the liquid crystal display according to the exemplary embodiment of the present invention will be described in detail with reference to FIGS. 3A to 6B.

3A to 6B are cross-sectional views at intermediate stages of the method for manufacturing the upper panel for the liquid crystal display device shown in FIGS. 1 to 2B according to the embodiment of the present invention, respectively, and are arranged in the order of the process.

As shown in FIGS. 3A and 3B, in the method of manufacturing the upper panel 200 of the liquid crystal display according to the exemplary embodiment of the present invention, first, a conductive layer 70 such as a metal is placed on the insulating substrate 210. Deposit.

After the photosensitive film is applied on the conductor layer 70 to a thickness of 1 μm to 2 μm, the photosensitive film is irradiated with light through a photomask (not shown) and then developed. The thickness of the developed photoresist film varies depending on the position. In FIGS. 3A and 3B, the photoresist film is composed of first to third portions whose thickness becomes smaller. The first part located in the area A and the second part located in the area C are denoted by reference numerals 42 and 44, respectively, and no reference has been given to the third part located in the area B. This is because the portion has a thickness of zero, so that the lower conductive layer 70 is exposed. The ratio of the thicknesses of the first portion 42 and the second portion 44 varies depending on the process conditions in the subsequent process, but the thickness of the second portion 44 is 1/2 of the thickness of the first portion 42. It is preferable to set it as follows.

As described above, there may be various methods of varying the thickness of the photoresist film according to the position, and the transparent mask and the light blocking area as well as the translucent area may be provided in the exposure mask. Yes. The translucent region is provided with a slit pattern, a lattice pattern, or a thin film having a medium transmittance or a medium thickness. When using the slit pattern, it is preferable that the width of the slits and the interval between the slits are smaller than the resolution of the exposure machine used for the photographic process. Another example is to use a photoresist film that can be reflowed. That is, a thin portion is formed by forming a reflowable photoresist pattern with a normal mask having only a transparent region and a light shielding region and then reflowing so that the photoresist film flows into an area where no photoresist remains.

Given the appropriate process conditions, the thickness of the lower layer may be adjusted by etching due to the difference in thickness of the photoresist layers 42 and 44. Therefore, when the etching process is performed using the photosensitive films 42 and 44 having different thicknesses, a plurality of data lines having a plurality of light blocking members 172 and groove-shaped contact portions 87 as shown in FIGS. 4A and 4B ( 171 is formed.

If the photoresist residue remains on the surface of the conductor layer 70, it is removed through ashing.

Subsequently, as illustrated in FIGS. 5A and 5B, the photosensitive organic materials including the red, green, and blue pigments are sequentially applied, respectively, to form the red, green, and blue color filters 230 in turn.

6A and 6B, the common electrode 270 is formed by stacking a transparent conductive material such as ITO or IZO on the color filter 230.

Next, as shown in FIGS. 2A and 2B, the alignment layer 21 is formed on the common electrode 270.

Next, a method of manufacturing the lower panel of the liquid crystal display according to the exemplary embodiment of the present invention will be described in detail with reference to FIGS. 7 to 13C and FIGS. 1 to 2C.

7, 10 and 12 are layout views in an intermediate step of a method of manufacturing a lower panel (thin film transistor array panel) according to an embodiment of the present invention in the liquid crystal display device shown in FIGS. 8A through 8C, 11A through 11C, and 13A through 13C illustrate the lower display panels of FIGS. 7, 10, and 12, respectively, as shown in a line VIIIa-VIIIa 'through VIIIc-VIIIc', Cross-sectional views taken along lines XIa-XIa 'through XIc-XIc' and XIIIa-XIIIa 'through XIIIc-XIIIc', and FIGS. 9A through 9C are diagrams illustrating VIIIa-VIIIa 'of the thin film transistor array panel of FIG. FIG. 8A is a cross sectional view taken along the line VIIIb-VIIIb 'and VIIIc-VIIIc', and is a view at the next step of FIG. 8A.

First, as shown in FIGS. 7 to 8C, a conductive layer such as a metal is deposited on the insulating substrate 110 by a sputtering method and etched to form a plurality of gate lines 121 and a plurality of gate connections 1128. To form.

Next, as shown in FIGS. 9A and 9C, the gate insulating layer 140, the intrinsic amorphous silicon layer 150, and the impurity amorphous silicon layer 160 are successively stacked by chemical vapor deposition (CVD) or the like. Silicon nitride is preferred as the material of the gate insulating film 140, and the lamination temperature is preferably about 250 to 400 DEG C, and the thickness is about 2,000 to 5,000 GPa. Subsequently, a conductive layer 170 such as metal is deposited to a predetermined thickness by a method such as sputtering, and then a photosensitive film is applied thereon to a thickness of 1 μm to 2 μm.

Thereafter, the photosensitive film is irradiated with light through a photomask (not shown) and then developed. The thickness of the developed photoresist film varies depending on the position. In FIGS. 9A and 9C, the photoresist film is composed of first to third portions whose thickness becomes smaller. The first part located in the area A (hereinafter referred to as the wiring area) and the second part located in the area C (hereinafter referred to as the channel area) are denoted by reference numerals 52 and 54, respectively. Reference numerals are not given to the third portion located in the region, because the third portion has a thickness of zero, so that the lower conductive layer 170 is exposed. The ratio of the thickness of the first portion 52 and the second portion 54 may vary depending on the process conditions in the subsequent process, but the thickness of the second portion 54 is less than 1/2 of the thickness of the first portion 52. It is preferable to set it as it, for example, it is good that it is 4,000 Pa or less.

As described above, there may be various methods of varying the thickness of the photoresist film according to the position, and the transparent mask and the light blocking area as well as the translucent area may be provided in the exposure mask. Yes. The translucent region is provided with a slit pattern, a lattice pattern, or a thin film having a medium transmittance or a medium thickness. When using the slit pattern, it is preferable that the width of the slits and the interval between the slits are smaller than the resolution of the exposure machine used for the photographic process. Another example is to use a photoresist film that can be reflowed. That is, a thin portion is formed by forming a reflowable photoresist pattern with a normal mask having only a transparent region and a light shielding region and then reflowing so that the photoresist film flows into an area where no photoresist remains.

Given the appropriate process conditions, the underlying layers can be selectively etched due to the difference in thickness of the photoresist films 52 and 54. Accordingly, a plurality of source electrodes 173, a plurality of drain electrodes 175, and a plurality of data connectors 179 as shown in FIGS. 10 through 11C are formed through a series of etching steps, and a plurality of island-type ohmic contacts 163 are formed. , 165, 169, and a plurality of island-like semiconductors 154, 159.

For convenience of explanation, portions of the conductor layer 170, the impurity amorphous silicon layer 160, and the intrinsic amorphous silicon layer 150 positioned in the wiring region A are referred to as first portions, and the conductor layer located in the channel region C. A portion of the impurity amorphous silicon layer 160 and the intrinsic amorphous silicon layer 150 is referred to as a second portion, and the conductor layer 170 located in the other region B, the impurity amorphous silicon layer 160, and the intrinsic A part of the amorphous silicon layer 150 is called a third part.

One example of the order of forming such a structure is as follows.

(1) removing the third portion of the conductor layer 170, the impurity amorphous silicon layer 160 and the amorphous silicon layer 150 located in the other region (B),

(2) removing the second portion 54 of the photosensitive film located in the channel region,

(3) removing the second portion of the conductor layer 170 and the impurity amorphous silicon layer 160 located in the channel region C, and

(4) Removal of the first portion 52 of the photosensitive film located in the wiring region A. FIG.

Another example of this order is as follows.

(1) removing the third portion of conductor layer 170 located in other region B,

(2) removing the second portion 54 of the photosensitive film located in the channel region C,

(3) removing the third portion of the impurity amorphous silicon layer 160 and the amorphous silicon layer 150 located in the other region (B),

(4) removing the second portion of conductor layer 170 located in channel region C,

(5) removing the first portion 52 of the photosensitive film located in the wiring region A, and

(6) Removal of the second portion of the impurity amorphous silicon layer 160 located in the channel region (C).

When the second portion 54 of the photoresist film is removed, the thickness of the first portion 52 of the photoresist film will decrease, but since the thickness of the second portion 54 of the photoresist film is thinner than the first portion 52 of the photoresist film, the lower layer The first portion 52 which prevents it from being removed or etched away is not removed.

By selecting an appropriate etching condition, the impurity amorphous silicon layer 160 and the intrinsic amorphous silicon layer 150 and the second portion 54 of the photoresist film under the third part of the photoresist film may be removed at the same time. Similarly, the portion of the impurity amorphous silicon layer 160 under the second portion 44 of the photosensitive film and the first portion 52 of the photosensitive film may be removed at the same time. For example, when a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ is used, the photosensitive film and the intrinsic amorphous silicon layer 150 (or impurity amorphous silicon layer 160) are etched at almost the same etching rate. can do.

If the photoresist residue remains on the surface of the conductor layer 170, it is removed through ashing.

In step (3) of the first example or step (4) of the second example, an example of an etching gas used to etch the intrinsic amorphous silicon layer 150 is a mixture of CF ₄ and HCl or a mixture of CF ₄ and O ₂ . A gas may be used, and when CF ₄ and O ₂ are used, the amorphous silicon layer 150 may be scraped off to a uniform thickness.

Then, as shown in FIGS. 12 and 13C, silicon nitride is deposited in the range of about 250 to 1500 ° C. by CVD, or an acrylic organic insulating material having excellent planarization characteristics is applied, or an a-Si: C: O film or A low dielectric constant insulating material including an a-Si: O: F film or the like is laminated by PECVD to form a passivation layer 180, and then the passivation layer 180 is photo-etched together with the gate insulating layer 140 to form a plurality of contact holes. (182, 183, 185).

Finally, as illustrated in FIGS. 1 and 2C, a conductive film (not shown) is deposited using the same material as the source line 173, the drain electrode 175, and the data line 171 of the upper panel 200. Next, dry etching is performed by using a photo process to form a plurality of columnar spacers 320.

Subsequently, the ITO layer or the IZO layer is deposited by a sputtering method, and photo-etched to form the plurality of pixel electrodes 190 and the plurality of contact assistants 82, and the alignment layer 11 is coated.

After the two display panels 100 and 200 are formed as described above, the conductive contact hole 50 is coated on a portion of the alignment layer 21 positioned on the contact portion 87 of the data line 171 of the upper display panel 100. A sealing material (not shown) is applied to the display panel 100. When the two display panels 100 and 200 are aligned, pressed, and coupled such that the column spacer 320 of the lower display panel 100 and the data line contact portion 87 of the upper display panel 200 are aligned, the conductive contact holes 50 are connected. Penetrates through the upper and lower alignment layers 11 and 21 to electrically connect the data line contact portion 87 and the columnar spacer 320.

The thin film transistor array panel according to the exemplary embodiment of the present invention may be manufactured in various modified forms and methods.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, by forming the data line and the pixel electrode on different substrates, the aperture ratio can be increased by increasing the area of the pixel electrode without increasing the parasitic capacitance caused by the overlap of the data line and the pixel electrode.

Claims (13)

Insulation board, A plurality of gate lines formed on the insulating substrate, A gate insulating film formed on the gate line, A semiconductor layer formed on the gate insulating film. A plurality of source electrodes formed on the semiconductor layer and separated from each other; A plurality of drain electrodes formed on the semiconductor layer and separated from the source electrode, A protective film formed on the source electrode and the drain electrode, A columnar spacer formed on the source electrode and having a pillar shape electrically connected to the source electrode, and A plurality of pixel electrodes formed on the passivation layer and electrically connected to the drain electrode Thin film transistor array panel comprising a. In claim 1, The passivation layer has a first contact hole exposing the drain electrode and a second contact hole exposing a source electrode, the pixel electrode is connected to the drain electrode through the first contact hole, and the columnar spacer is formed in the second contact hole. The thin film transistor array panel connected to the source electrode through a contact hole. In claim 1, The gate line includes a plurality of first gate lines, a plurality of second gate line pairs, and a plurality of gate connection portions connecting the first and second gate line pairs. In claim 3, The pixel electrode overlaps the gate connection part. In claim 3, The drain electrode overlaps the second gate line. Insulation board, A plurality of data lines formed on the insulating substrate, and A common electrode formed over the entire surface of the substrate and having a plurality of openings exposing at least a portion of the data line; Display panel for liquid crystal display device comprising a. In claim 6, The data line includes a plurality of contact portions forming a groove. In claim 7, And a plurality of conductive contact holes formed on the contact portions of the data lines. In claim 6, A display panel for a liquid crystal display device further comprising a plurality of color filters formed on the substrate. In claim 6, And a plurality of light blocking members formed on the same layer as the data line and positioned between the data lines. A first insulating substrate, a plurality of insulated gate lines formed on the first substrate, a plurality of thin film transistors each consisting of a gate electrode, a drain electrode, and a source electrode connected to the gate line, and connected to the drain electrode A lower display panel including a plurality of pixel electrodes and a plurality of columnar spacers connected to the source electrodes; A second insulating substrate facing the first insulating substrate, a data line formed on the second insulating substrate and extending to cross the gate line, a plurality of color filters formed on the second substrate, and the pixel electrode; An upper panel including opposite common electrodes, and A conductive contact hole in contact with the data line and the columnar spacer; Liquid crystal display comprising a. In claim 11, The columnar spacer is made of the same dry etching material as the data line. In claim 11, And a plurality of light blocking members formed on the same layer as the data line and positioned between the data lines.