CN100437251C - Liquid crystal display with transparent conductive film on coated formed sandwich insulation film - Google Patents
Liquid crystal display with transparent conductive film on coated formed sandwich insulation film Download PDFInfo
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- CN100437251C CN100437251C CNB2005100836141A CN200510083614A CN100437251C CN 100437251 C CN100437251 C CN 100437251C CN B2005100836141 A CNB2005100836141 A CN B2005100836141A CN 200510083614 A CN200510083614 A CN 200510083614A CN 100437251 C CN100437251 C CN 100437251C
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Abstract
The present invention relates to a manufacturing method for a liquid crystal display. The liquid crystal display is provided with a bus line, a switch element and a pixel electrode, wherein the bus line is arranged in a grille-shaped manner; the switch element is coupled with the bus line; the pixel electrode is arranged on a sandwich layer insulation film which is coated, and the pixel electrode is coupled with the switch element. When the liquid crystal display is manufactured, and a transparent conductive film is formed on the sandwich layer insulation film which is coated, the control temperature of a substrate is from 100 to 170 DEG C. On the other hand, when the transparent conductive film is formed on the sandwich layer insulation film under the state of non-heating, the oxygen flow rate ratio is set to 1 % or below 1 %, and the present invention is processed by annealing after forming the film. Consequently, when an ITO film is etched on the sandwich layer insulation film, etching residues are not generated. In addition, the present invention can uniformly reduce the contact resistance between the ITO film and lower layer metal, and can prevent display defect.
Description
The application is that the name of submitting on August 16th, 2002 is called the dividing an application of patented claim that " LCD that has nesa coating on the interlayer insulating film that apply to form ", application number are 02130565.X.
Technical field
The present invention relates to LCD and manufacture method thereof.More particularly, the present invention relates to have the LCD of high-resolution display board, wherein use dielectric film to come as interlayer insulating film by applying formation such as organic membrane for example.
Background technology
Usually, use the transparent type LCD widely, wherein thin film transistor (TFT) (TFT) or metal insulator insulation (MIM) device is as the beginning element that drives and control each pixel.
Figure 22 A is the local planimetric map that amplifies, and shows the pixel parts of the active matrix substrate of the conventional transmissive type liquid crystal display of disclosed use TFT in Japanese Patent Laid-Open Publication No.9-152625.Figure 22 B is the cross-sectional view that the line B-B along Figure 22 A is got.In the active matrix substrate of this transparent mode LCD, form a plurality of pixel capacitors in the mode of matrix.
Shown in Figure 22 A, around pixel capacitors 1, be provided with sweep trace 2a and signal wire 2b.Sweep trace 2a is arranged in parallel and is used for sweep signal is supplied with pixel capacitors 1.Signal wire 2b is arranged in parallel and is vertical with sweep trace 2a.Use signal wire 2b that shows signal is supplied with pixel capacitors 1.Sweep trace 2a and signal wire 2b are set like this, and the part of each sweep trace 2a and the part of each signal wire be overlapping to be placed on the periphery of pixel capacitors.Near each part that intersects between sweep trace 2a and the signal wire 2b, be provided with thin film transistor (TFT) (TFT) 3 with pixel capacitors 1 coupling.
The gate electrode of TFT3 and sweep trace 2a coupling, the source electrode of TFT3 and signal wire 2b coupling.The drain electrode of TFT3 is coupled by electrode and by contact hole 5 and pixel capacitors, and by connection electrode 4a and additional capacitor electrode 4b coupling.
Shown in Figure 22 B, on transparent insulation substrate 6 by the sequential cascade gate electrode 3a that is mentioned, gate insulating film 7a and semiconductor layer 8a.At the center section of semiconductor layer, channel protective layer 8b is set.In addition, an amorphous silicon (n is set
+A-Si) layer, this amorphous silicon layer are carried out and are covered semiconductor layer 8a, and amorphous silicon layer is divided into source electrode 3b and drain electrode 3c on channel protective layer 8a.
End at source electrode 3b is provided with signal wire 2b, and signal wire 2b has the double-layer structure that comprises nesa coating and metal level.And, being provided with nesa coating and metal level in the end of drain electrode 3c, nesa coating extends as connection electrode 4a, so that be coupled with drain electrode 3c and pixel capacitors.Connection electrode 4a also links to each other with additional capacitor electrode 4b.In addition, being provided with interlayer insulating film (passivating film) carries out and covers TFT3, sweep trace, signal wire and connection electrode 4a.
To the manufacturing process of active matrix substrate with said structure be made an explanation below.At first, on transparent insulation substrate 6, form gate electrode 3a by manufacturings such as for example glass.In the zone that comprises gate electrode 3a etc., form gate insulating film 7a and amorphous silicon (n-Si) layer one by one with the order of mentioning.The pattern of making amorphous silicon (n-Si) layer is to form semiconductor layer 8a.Then, on the semiconductor layer 8a and above gate electrode 3a, form channel protection film 8b.Then, form amorphous silicon (n
+-Si) layer is carried out and is covered channel protective layer 8b and semiconductor layer 8a, and pattern-making is to form source electrode 3b and drain electrode 3c.
Formation comprises the interlayer insulating film 9 of organic membrane on drain electrode 3b and drain electrode 3c, and has contact hole 5 in interlayer insulating film 9.After this, form tin indium oxide (ITO) film that shoe covers interlayer insulating film 9, and the pattern of making ITO film forms a plurality of transparent pixel electrodes of being made by the ITO film by sputter.
In said process, preferably, after forming contact hole 5, remove the surface that (ashed) comprises the interlayer insulating film 9 of organic membrane by using oxygen plasma.Thereby can improve the adhesion between ITO film and the organic membrane, and avoid bad coupling between ITO film and the additional capacitor electrode metal film.
Use is compared the organic membrane that has than low-k and is replaced the reason of present used inoranic membrane to be as interlayer insulating film with inoranic membrane, reduce the interference between signal wire and the pixel capacitors.That is to say, by using organic membrane as interlayer insulating film 9, can work as pixel capacitors and signal wire overlap with improve the aperture than the time capacitive coupling of minimizing between signal wire and pixel capacitors, thereby, can reduce interference.
Usually, when forming the ITO film on the interlayer insulating film 9 that is comprising organic membrane, use high temperature sputtering method heating transparent insulation substrate 6, to improve the pattern-making characteristic of ITO film.
A kind of example that uses the high temperature sputter to make the method for ITO film is disclosed in Jap.P. No.2520399.In this patent, described to form and do not caused that the condition of the high-quality ITO film that color filter degenerates is, the temperature of substrate is arranged between 180 ℃ and 250 ℃.In Japanese Patent Laid-Open Publication No.9-152625, the condition that forms the ITO film is not described at all.
Yet when using the high temperature sputter to form the ITO film, the ITO film can degenerate because of the getter action of organic insulating film, and owing to the generation of etching residue makes the pattern of making bad.This point is particularly outstanding when using wet etching.
For fear of this scarce limit, can expect using low temperature sputter or non-heating condition to sputter at and form the ITO film on the organic insulating film.Yet when using the low temperature sputter, it is big that the contact resistance between the metal film of ITO film and low layer becomes.
When contact resistance becomes big, can not realize that contact resistance is enough even in the substrate region.Contact resistance can not cause evenly enough that the vertical stripes that is presented at the lip-deep image of display board is inhomogeneous.Contact resistance does not enough evenly have considerable influence to the displayed image in the high-resolution LCD panel, in this LCD panel since each signal wire between narrow interval, be arranged alternately at opposite side with the signal terminal of signal wire coupling, perhaps be arranged alternately at opposite side every a certain amount of such signal terminal.
And when contact resistance increased, laterally interference phenomenon will appear in twisted nematic (TN) the type LCD panel with public storage organization or appear at plane internal conversion (in-planeswitching) (IPS) in the type LCD panel.
That is to say, in having the TN type LCD panel of public storage organization, public current potential (voltage potential) is applied on the public wiring conductor that is used to form memory capacitance.Therefore, public wiring conductor is intercoupled.When using ITO film on interlayer insulating film (passivating film) to make the TFT substrate structure that public wiring conductor intercouples, contact resistance can be made by organic insulating film because of interlayer insulating film and uprise.Therefore, the all-in resistance of public wiring conductor can uprise inevitably.
Summary of the invention
Therefore, the purpose of this invention is to provide a kind of LCD and preparation method thereof,, do not produce etching residue, and can form the ITO film and make suitable ITO film figure when by for example applying when forming the ITO film on the film formed interlayer insulating film of organic insulation.
Another object of the present invention provides a kind of LCD and preparation method thereof, is wherein forming the ITO film by for example applying on the film formed interlayer insulating film of organic insulation, and can reduce the contact resistance between ITO film and following metal film.
Another object of the present invention provides a kind of LCD and preparation method thereof, can reduce the contact resistance between ITO film and following metal film, thereby can overcome the scarce limit of displayed image on LCD panel.
Another object of the present invention provides a kind of LCD and preparation method thereof, can reduce the contact resistance between ITO film and following metal film, thereby it is inhomogeneous to overcome the vertical stripes that is presented at the image on the LCD panel.
Another object of the present invention provides a kind of LCD and preparation method thereof, can reduce the contact resistance between ITO film and following metal film, thereby can avoid the horizontal interference phenomenon in LCD panel.
Another object of the present invention is the shortcoming that overcomes conventional LCD and preparation method thereof.
According to a first aspect of the invention, a kind of method of making LCD is provided, this LCD have mode with grid be arranged on on-chip bus, with the on-off element of bus coupling, by applying the pixel capacitors that the nesa coating that is provided with on the interlayer insulating film that forms forms, pixel capacitors is by film formed contact through hole of interlayer insulation and on-off element coupling, described method comprises: when forming nesa coating on interlayer insulating film, the temperature of substrate is controlled to be 100 ℃-170 ℃.
In the case, preferably, first heated substrate in heating chamber is sent to substrate in the chamber that forms nesa coating then.
Preferably, first heated substrate and ise substrate in heating chamber are transported to substrate in the chamber that forms nesa coating then.
Further, under same vacuum state, carry out the substrate heating earlier, ise after heating forms nesa coating then.
Preferably, be organic insulating film by applying the interlayer insulating film that forms.
More advantageously, LCD has the metal film with nesa coating coupling, and nesa coating is made by the ITO film, with the metal film of nesa coating coupling be that the alloy of principal ingredient is made by chromium or chromium.
According to a further aspect in the invention.A kind of method of making LCD is provided, this LCD have mode with grid be arranged on on-chip bus, with the on-off element of bus coupling, by applying the film formed pixel capacitors of electrically conducting transparent that is provided with on the interlayer insulating film that forms, pixel capacitors is by film formed contact through hole of interlayer insulation and on-off element coupling, described method comprises: non-heated condition and oxygen flow speed ratio (flow rate ratio) be 1% or still less state under, on interlayer insulating film, form nesa coating; After forming nesa coating, anneal.
In the case, preferably under the temperature of 200 ℃ of-240 ℃ of degree, anneal.
Be organic insulating film preferably also by applying the interlayer insulating film that forms.
Preferably, LCD has the metal film with nesa coating coupling, and nesa coating is made by the ITO film, with the metal film of nesa coating coupling be that the alloy of principal ingredient is made by chromium or chromium.
According to a further aspect in the invention, a kind of method of making LCD is provided, this LCD have mode with grid be arranged on on-chip bus, with the on-off element of bus coupling, by applying the pixel capacitors that the nesa coating that is provided with on the interlayer insulating film that forms forms, pixel capacitors is by passivating film and film formed contact through hole of interlayer insulation and on-off element coupling, described method comprises: when forming by passivating film and the film formed contact through hole of interlayer insulation, form the opening of passivating film by plasma etching.
In the case, the interlayer insulating film of preferred coating formation is an organic insulating film.
Preferably, LCD has the metal film with nesa coating coupling, and nesa coating is made by the ITO film, with the metal film of nesa coating coupling be that the alloy of principal ingredient is made by chromium or chromium.
According to a further aspect in the invention, provide a kind of LCD, having comprised: transparent substrate; Be arranged on many parallel scan lines on the transparent substrate; With many crossing parallel signal lines of many parallel scan lines; On-off element with sweep trace and signal wire coupling; With apply the pixel capacitors that the nesa coating on the interlayer insulating film forms forms by being arranged on, pixel capacitors is coupled by film formed contact through hole of interlayer insulation and on-off element; The nesa coating that wherein forms on interlayer insulating film has the part of contact lower metal film, and interlayer insulating film has crystallizability in the part of contact lower metal film.
In the case.The preferred interlayer insulating film that applies formation is an organic insulating film.
Preferably, nesa coating is made by the ITO film, and the lower metal film of contact nesa coating is that the alloy of principal ingredient is made by chromium or chromium.
According to a further aspect in the invention, provide a kind of LCD, having comprised: transparent substrate; Be arranged on many parallel scan lines on the transparent substrate; With many crossing parallel signal lines of many parallel scan lines; On-off element with sweep trace and signal wire coupling; With apply the pixel capacitors that the nesa coating on the interlayer insulating film forms forms by being arranged on, pixel capacitors is coupled by film formed contact through hole of interlayer insulation and on-off element; Signal wire terminals, each signal wire terminals all with the coupling of an end of corresponding signal lines, the signal wire terminals comprise the laminated portions of nesa coating and lower metal film, at the opposite side of substrate alternately or every a plurality of terminals signalization line terminals; Wherein the contact resistance between nesa coating and lower metal film is different from contact resistance difference 1500 Ω of the signal wire terminals of substrate opposite side or littler.
In the case, be organic insulating film preferably by applying the interlayer insulating film that forms.
Preferably, nesa coating is made by the ITO film, with the lower metal film of nesa coating coupling be that the alloy of principal ingredient is made by chromium or chromium.
Description of drawings
Will more be expressly understood these and other feature and advantage of the present invention by the detailed description below in conjunction with accompanying drawing, wherein identical Reference numeral is represented identical or corresponding parts in institute's drawings attached; And, wherein:
Fig. 1 is a schematic plan view, describes according to the TFT substrate structure in the transmissive type liquid crystal display of first embodiment of the invention;
Fig. 2 is a planimetric map, shows the LCD panel of the TFT substrate 10 that uses Fig. 1;
Fig. 3 is the planimetric map that amplifies, and shows the part of a pixel of the TFT substrate of Fig. 1;
Fig. 4 comprises cross-sectional view of being got along Fig. 2 line A-A and the cross-sectional view of being got along the B-B line of Fig. 3;
Fig. 5 A-5D is a cross-sectional view, and each width of cloth all is described in the structure of workpiece during the manufacturing process of LCD panel of the TFT substrate that uses Fig. 1;
Fig. 6 E-6G is a cross-sectional view, and each width of cloth all is described in after the structure shown in Fig. 5 A-5D the structure of workpiece during the manufacturing process of the LCD panel of the TFT substrate that obtains to use Fig. 1;
Fig. 7 A-7C is a cross-sectional view, and each width of cloth all is described in the structure of workpiece during the contact hole manufacturing process of pixel parts shown in Figure 4;
Fig. 8 D-8E is a cross-sectional view, and each width of cloth all is described in the structure of workpiece during the contact hole manufacturing process that obtains pixel parts shown in Figure 4 afterwards of structure shown in Fig. 7 A-7C;
Fig. 9 A-9C is a cross-sectional view, and each width of cloth all is described in the structure of workpiece during the signal wire terminals manufacturing process shown in Figure 4;
Figure 10 is a schematic plan view, describes according to the TFT substrate structure in the transmissive type liquid crystal display of second embodiment of the invention;
Figure 11 is the planimetric map that amplifies, and shows the part of a pixel of the TFT substrate of Figure 10;
Figure 12 A-12D is a cross-sectional view, and each width of cloth all is described in the structure of workpiece during the manufacturing process of TFT substrate of Figure 10;
Figure 13 E-13F is a cross-sectional view, and each width of cloth all is described in the structure of workpiece during the manufacturing process of the TFT substrate that obtains Figure 10 afterwards of structure shown in Figure 12 A-12D;
Figure 14 is a cross-sectional view, and each width of cloth all is described in the structure of workpiece during the manufacturing process of the TFT substrate that obtains Figure 10 afterwards of structure shown in Figure 13 E-13F;
Figure 15 is a curve map, shows when forming the ITO film according to first embodiment of the invention with sputter an example of the mutual relationship between the inhomogeneous occurrence rate of substrate temperature and vertical stripes (rate of occurrence);
Figure 16 is a curve map, shows when non-heated condition forms the ITO film with sputter the relation between oxygen flow speed ratio and the layer resistance;
Figure 17 A-17C is an illustration, and each width of cloth all is described under the non-heating condition after the sputtering ITO film and after 200 ℃ of annealing, the example that the layer resistance (layer resistance) in the substrate distributes;
Figure 18 is an illustration, the relation when showing the sputtering ITO film by form between the state of substrate temperature and etching residue;
Figure 19 is an illustration, shows under non-heating condition after the sputtering ITO film relation in annealing temperature and substrate between the ITO film line width homogeneity, and the relation between annealing temperature temperature and organic insulating film painted by form;
Figure 20 is an illustration, shows in first embodiment difference of the contact resistance value of upside signal terminal and downside signal terminal and relation between the uneven condition of vertical stripes occurs by form;
Figure 21 A and Figure 21 B are schematic illustration, show the example of observations of the TEM of nesa coating in the LCD that the method for making according to the present invention is made and the coupling unit between the lower metal film.
The local amplification view of Figure 22 A shows in Japanese Patent Laid-Open Publication No.9-152625 disclosed and use the pixel parts of active matrix substrate of the conventional transmissive type liquid crystal display of TFT;
Figure 22 B is the cross-sectional view that the line B-B along Figure 22 A is got.
Embodiment
Describe embodiments of the invention in detail below with reference to accompanying drawing.
(first embodiment)
Fig. 1 is a schematic plan view, has described the TFT substrate structure according to the transmissive type liquid crystal display of first embodiment of the invention.TFT substrate 10 shown in Fig. 1 is faced mutually with the relative substrate of mentioning later (opposing substrate) 17, and filling liquid crystal material is to form the LCD panel (referring to Fig. 2 and Fig. 4) of LCD in the interval between TFT substrate 10 and relative substrate 17.
On the surface of the TFT substrate 10 of relative substrate 17 sides, the multi-strip scanning line 12 that many signal line 11 is set and intersects in the mode of grid shape with signal wire 11.Near each intersection of one of signal wire 11 and one of sweep trace 12, form TFT 13.Thereby dispose TFT 13 in the mode of matrix.
In this embodiment, TFT13 constitutes a kind of high-resolution liquid crystal display board that has CF (color filter on thin film transistor (TFT)) structure at TFT, on the TFT13 of this LCD panel or TFT13 above be provided with color filter.
In the high-resolution liquid crystal display board, owing to narrow down along the interval between the adjacent signals line 11 of the vertical direction setting of plate, so each signal terminal 14 that all is arranged on signal wire 11 1 ends is positioned at the opposite side of TFT substrate 10, so as opposite side alternately signalization terminals 14 or every many signal line 11 at couple positioned opposite signal terminal 14.About the sweep trace 12 along the horizontally set of plate, each sweep trace that all is arranged on sweep trace 12 1 ends connects the side that end 15 is configured in TFT substrate 10.
Every signal line 11 all with the respective column that is arranged on the TFT matrix in the source electrode coupling of TFT13, be used for data-signal is inputed to the source electrode.Each sweep trace 12 all with the corresponding line that is arranged on TFT 13 matrixes in the gate electrode coupling of TFT13.Provide sweep signal by each sweep trace 12 to the corresponding gate electrode of TFT 13.Thereby, drive each TFT13 and data-signal write pixel capacitors with the coupling of the drain electrode of TFT 13.
Fig. 2 is a planimetric map, shows the LCD panel of the TFT substrate 10 that uses Fig. 1.Fig. 3 is the planimetric map that amplifies, and shows the part of a pixel of the TFT substrate of Fig. 1.Fig. 4 comprises cross-sectional view of being got along the line A-A of Fig. 2 and the cross-sectional view of being got along the B-B line of Fig. 3.
As Fig. 2 and shown in Figure 4, LCD panel 16 has TFT substrate 10 and relative substrate 17, and each relative substrate 17 all comprises the transparent insulation substrate of being made by glass and similar material and all is rectangular shape.Insert liquid crystal material L (referring to Fig. 4) in the gap between TFT substrate 10 and relative substrate 17, to form LCD panel 16.
At the upper surface of TFT substrate 10, be formed with black matrix 18.Black matrix 18 has a plurality of and pixel capacitors 33 (referring to Fig. 4) corresponding opening 19 (referring to Fig. 2).Opening 19 comprises the opening 19R that for example is used for red color filter, the opening 19G that is used for green color filter and the opening 19B that is used for blue color filter, respectively these openings of arranged in sequence.
Make TFT substrate 10 and the predetermined space and relative each other of relatively being separated by between the substrate 17, and, substrate 10 and substrate 17 are interfixed by encapsulant 20 along the outer part distribution of substrate 10 and relative substrate 17.At the outer peripheral part along TFT substrate 10 3 sides, signalization terminals.That is to say, a plurality of levels (H) side terminal 21, be signal wire terminals 14, be be provided with along the widthwise edge edge of plate and extend in vertical direction, a plurality of vertical (V) side terminal 22, be sweep trace terminals 15, be that a vertical edge along plate partly is provided with and extend along horizontal direction.Substrate 17 does not cover level (H) side terminal 21 and vertical (V) side terminal 22 relatively.
A part of encapsulant 20 places on the side relative with the side which is provided with terminals 22 are provided with the inlet 23 that makes liquid crystal material inject the interval between TFT substrate 10 and the relative substrate 17.After in the interval that liquid crystal material L is infused between TFT substrate 10 and the relative substrate 17, with encapsulant or fluid sealant 24 sealing inlets 23.
As shown in Figure 3 and Figure 4, on TFT substrate 10, form gate electrode 25, and further form gate insulating film 26 and cover gate electrode 25 to carry out.On gate insulating film 26, form semiconductor layer 27, so that semiconductor layer 27 is superimposed upon on the gate electrode 25 through gate insulating film 26.In addition, source electrode 28 and drain electrode 29 are set, source electrode 28 and drain electrode 29 separately and with semiconductor layer 27 are coupled by the space on semiconductor layer 27 cores.
Form the passivating film 30 that covers conductor layer 27, source electrode 28, drain electrode etc.Thereby form TFT13.
On passivating film 30, in the black matrix 18 of the part formation corresponding as light shield with TFT 13 grades.And, show near formation picture frame black matrix 18a H side terminal 21 and V side terminal 22.Although at length do not illustrate in the accompanying drawings, form picture frame optical screen film 18a on every side in the image displaying area territory.In addition, form red filter 46R, blue filter 46B and green filter (not illustrating in the accompanying drawings) in the part corresponding with pixel area.
Form outer coating film 32, cover these light filters 31 and passivating film 30.A plurality of transparent pixel electrodes 33 are set on outer coating film 32.Pixel capacitors 33 is made by for example ITO film and is distributed with matrix-style.
When using above-mentioned TFT13 as on-off element, drain electrode 29 is as the lead-in wire electrode that pixel capacitors 33 and on-off element are coupled.Through contact through hole 34 drain electrode 29 and pixel capacitors 33 are intercoupled, the contact through hole 34 of formation penetrates external coating 32 and passivating film 30.
The gate electrode 25 of TFT 13 and sweep trace 12 couplings, the source electrode 28 of TFT 13 and signal wire 11 couplings make drain electrode 29 and pixel capacitors 33 couplings by contact through hole 34.By sweep trace 12 switching signal is supplied with the gate electrode 25 of TFT13, picture intelligence is offered the source electrode 28 of TFT13, thereby electric charge injected or write pixel capacitors 33 by signal wire 11.
Under the situation of the part that does not cover contact through hole 34, form black matrix 18 and color filter 31.
Be formed with thereon on the inside surface of TFT substrate 10 of pixel capacitors 33, form the alignment films 35 that covers pixel capacitors 33.Also form alignment films 37 on the inside surface of relative substrate 17, the inside surface of substrate 17 is faced mutually with the alignment films 35 that forms on the surface of TFT substrate 10 relatively.TFT substrate 10 is faced by liquid crystal material L mutually with relative substrate 17, and is scattered with liner 36 between TFT substrate 10 and relative substrate 17, and the interval between substrate 10 and 17 is remained unchanged.
Be formed on the alignment films 37 on the relative substrate 17, so that alignment films 37 covers the transparent common electrode 38 that forms on the relative substrate 17.Transparent common electrode 38, each pixel capacitors 33 and the liquid crystal material L (see figure 4) between transparent common electrode 38 and pixel capacitors 33 constitute pixel capacitance.
In addition, on the outer surface of TFT substrate 10 and relative substrate 17,, form TFT side polarizer film 39 and relative substrate side polarizer film 40 respectively promptly at the lower surface of TFT substrate 10 and the upper surface of relative substrate 17.
Fig. 5 A-5D and Fig. 6 E-6G are cross-sectional views, and each width of cloth all is described in the structure of workpiece during the manufacturing process of LCD panel of the TFT substrate that uses Fig. 1.The cross-sectional view that each of Fig. 5 A-5D and Fig. 6 E-6G all comprises the cross-sectional view got along the line A-A of Fig. 2, got along the line B-B of Fig. 3, the cross-sectional view of being got along the line C-C of Fig. 2.Fig. 6 E-6G has described the making step after the making step shown in Fig. 5 A-5D.
Shown in Fig. 5 A-5D and Fig. 6 E-6G, at first prepare the glass substrate 10a that the thickness that is made of alkali-free (alkalifree) glass is about 0.7mm.On glass substrate 10a, form the conducting film that constitutes by Cr, Mo, Cr/Al stack membrane and Mo/Al stack membrane etc. by sputter, film thickness is about 100-300nm.By using photoetch method, make conductive film pattern to form the V side terminal (not illustrating in the accompanying drawing) of gate electrode 25, sweep trace (not illustrating in the accompanying drawing) and sweep trace terminals.
Then, use plasma CVD (chemical vapor deposition) method, form by silicon nitride (SiNx) formation gate insulating film 26, film thickness is about 300-500nm.In addition, form one deck amorphous silicon (a-Si), its film thickness is about 150-300nm, forms the phosphorus-doped amorphous silicon (n of one deck then
+A-Si), its film thickness is about 30-50nm.By using photoetch method, the pattern of making these layers is to form semiconductor layer 27.
Form the conducting film that is made of Cr, Mo, Cr/Al/Cr stack membrane and Mo/Al/Mo stack membrane etc. by sputter, film thickness is about 100-400nm.By using photoetch method, make conductive film pattern to form the H side terminal of source electrode 28, drain electrode 29, signal wire (not illustrating in the accompanying drawing) and signal wire terminals.
Use the plasma CVD method, form by passivating film 30, passivating film by as the inoranic membrane formation of silicon nitride (SiNx) film etc. and so on, film thickness is about 100-200nm (seeing Fig. 5 A).
Then, be scattered with the negativity acrylic acid photoresist of pigment or use the photoresist of carbon system (carbon system) to form black matrix 18 and picture frame black matrix 18a by use.Black matrix 18 that forms and the film thickness of picture frame black matrix 18a are about 1-3 μ m, and optical density (OD value) is 3 or bigger, and the thin-film electro resistance is 1 * 10
10Ω/ or bigger (referring to Fig. 5 B).
Further, be scattered with the negativity acrylic acid photoresist of pigment, form the red color filter 31R that film thickness is approximately 1.0-1.5 μ m by use.Form each color-filter layer (referring to Fig. 5 C) of blue color filter 31B and green color filter (not illustrating in the accompanying drawing) similarly with red color filter 31R.
Then, form external coating 32 by using positivity novolaks photoresist, external coating 32 is the organic insulating film of 2.0-3.5 μ m for film thickness, and the pattern of making external coating 32 is to form opening in each part that will form contact through hole.
Use photoengraving technology to carry out plasma etching then, dry ecthing passivating film 30 is to form contact through hole 34.In the case, when forming contact through hole 34, also remove passivating film 30 in H side terminal 21, at the gate insulating film (not illustrating in the accompanying drawing) of the passivating film 30 of V side terminal.
In plasma etching, use for example SF
6, CF
4, CHF
3Deng and so on fluorine be that gas carries out high-frequency discharge, carry out etching with the atomic group (radical) of these gases.In the case, optimize that the pressure, flow velocity, discharge power etc. of gas are desirable to obtain, the preferred profile (referring to Fig. 5 D) of each contact through hole.
Then, use the back, on the part of the drain electrode 29 that exposes by outer coating film 32 and contact through hole 34, form the thickness that constitutes by the ITO film and be about the 40-120nm nesa coating the sputtering method of introducing.With the pattern of light lithographic method making nesa coating, to form pixel capacitors 33.In the case, also on H side terminal 21 and V side terminal, form nesa coating (not illustrating in the accompanying drawings), and side by side make the pattern of this nesa coating with forming pixel capacitors 33, with form with the connection electrode 41 of H side terminal 21 couplings of signal wire terminals and with the connection electrode (not illustrating in the accompanying drawing) of the V side terminal coupling of sweep trace terminals (referring to Fig. 6 E).
On TFT substrate 10, forming by polyimide is the alignment films 35 that oriented material constitutes, and the thickness of alignment films is 30-60nm, and carries out orientation process.Afterwards, apply the encapsulant 20 (referring to Fig. 6 F) that the bonding agent by epoxy resin constitutes along the periphery of TFT substrate 10.
Similar with TFT substrate 10, in order to make relative substrate 17, at first, preparation thickness is about the glass substrate that is made of alkali-free glass of 0.7nm.On glass substrate, form constitute by the ITO film, film thickness is about 80-150nm, the thin-film electro resistance is the nesa coating of 20-40 Ω/, thereby form transparent common electrode 36 in substrate side relatively.Further, on transparent common electrode 36, the alignment films 35 that the oriented material that formation by polyimide is constitutes, the thickness of alignment films is 30-60nm, and carries out orientation process.Thereby, make relative substrate 17.
Then, make TFT substrate 10 and relative substrate 17 mutually in the face of and with liner (not illustrating in the accompanying drawing) TFT substrate 10 is fixed with therebetween encapsulant 20 with relative substrate 17.The liquid crystal material L that will comprise the compound of fluorine system from inlet 23 is infused in TFT substrate 10 and relatively the interval between the substrate 17.Afterwards, use encapsulant 24 to seal injection 23 by the curable resinoid formation of the ultraviolet ray (UV) of acrylates system.Thereby, obtain between TFT substrate 10 and relative substrate 17, to have the LCD panel of predetermined space.
At last, on the outer surface of TFT substrate 10 and relative substrate 17, that is, on the upper surface of the lower surface of TFT substrate 10 and relative substrate 17, form respectively one comprise iodine be polarized film TFT side polarized film 39 with comprise that iodine is the relative substrate side polarized film 40 of polarized film.Thus, prepared a LCD panel 16 (referring to Fig. 6 G) of using TFT substrate 10.
Fig. 7 A-7C and Fig. 8 D-8E are cross-sectional views, and each width of cloth all is described in the structure of workpiece during the contact hole manufacturing process that obtains pixel parts shown in Figure 4.Each of Fig. 7 A-7C and Fig. 8 D-8E all comprises and the cross-sectional view of getting along the vertical line of the line B-B of Fig. 3.Fig. 8 D-8E shows the making step that carries out after the making step that Fig. 7 A-7C describes.
Shown in Fig. 7 A-7C and Fig. 8 D-8E, at first, preparation glass substrate 10a.On glass substrate 10a, form gate insulating film 26, and form drain electrode 29 thereon.Then, form passivating film 30 to cover drain electrode 29 (referring to accompanying drawing 7A).
Subsequently, formation comprises for example color layer of blue color filter 31B (referring to Fig. 7 B) on the passivating film except that core 30 on the drain electrode 29.In addition, form outer coating film 32 and make the pattern of external coating, so that outer coating film 32 covers color layers and has opening (referring to Fig. 7 C) in the part that will form contact through hole.
Then, by using the photoengraving method, etching passivating film 30 makes drain electrode 29 expose (referring to Fig. 8 D) to form contact through hole 34 by contact through hole 34.
Then, by sputtering method,, form the nesa coating that constitutes by the ITO film in the part of the drain electrode 29 that exposes by contact through hole 34 with on outer coating film 32.The pattern of making nesa coating by photoengraving is to form pixel capacitors 33 (referring to Fig. 8 E).Thereby drain electrode 29 and pixel capacitors 33 are intercoupled by contact through hole 34.
Fig. 9 A-9C is a cross-sectional view, and each width of cloth all is described in the structure of workpiece during the manufacturing process of signal wire terminals shown in Figure 4.Each width of cloth of Fig. 9 A-9C all comprises the cross-sectional view of getting along the short side direction of signal wire terminals.
Shown in Fig. 9 A, at first, preparation glass substrate 10a.By plasma CVD (chemical vapor deposition) method, on glass substrate 10a, form gate insulating film 26.Then, on gate insulating film 26, form the H side terminal 21 of signal wire terminal portion.Subsequently, formationization film 30 is to cover H side terminal 21 (referring to Fig. 9 A).In the process that forms black matrix and formation color layer, do not form above-mentioned layer.
Then, use photoetch method, etching passivating film 30 is to form contact through hole 34, and contact through hole 34 makes H side terminal 21 expose (referring to Fig. 9 B).
Subsequently, on the H side terminal of exposing by contact through hole 34 21 and on the part at the passivating film 30 of the periphery of contact hole 34, form the nesa coating that constitutes by the ITO film by sputter.By the pattern of photoetch method making nesa coating, to form connection electrode 41 (referring to Fig. 9 C).Thereby the connection electrode 41 of formation is by contact through hole 34 and as signal terminal H side terminal 21 couplings partly.At this, the formation of the nesa coating of the formation of the nesa coating of connection electrode 41 and pixel capacitors 33 is carried out simultaneously.
When on organic interlayer insulating film, forming the nesa coating that constitutes by the ITO film, heating TFT substrate 10 so that the temperature of TFT substrate become near Celsius temperature 100-170 degree (℃).And when forming nesa coating, can not form film and oxygen flow speed ratio (O2/Ar) adjusted near 1% or lower preferred 0.5% or lower, 0.2% or lower better under the heated condition.Further, after forming this film, under the Celsius temperature of 200-240 degree, anneal.
(second embodiment)
Figure 10 is a schematic plan view, describes the structure according to the TFT substrate 50 in the transmissive type liquid crystal display of second embodiment of the invention.As shown in figure 10, on the surface of the TFT substrate 50 on the relative substrate side that does not illustrate in the accompanying drawings, the multi-strip scanning line 12 that is provided with many signal line 11 and intersects with the grill-shaped arrangement mode with signal wire 11.One of signal wire 11 and one of sweep trace 12 intersect near, form TFT13.Thereby, be provided with TFT13 in the mode of matrix.
Also between adjacent scanning lines 12, be provided with public wire conductors, promptly public wiring 51.Public wire conductors 51 and pixel capacitors form memory capacitance in public storage-type LCD.
Figure 11 is the planimetric map that amplifies, and shows the part of a pixel of the TFT substrate of Figure 10.As shown in figure 11, in the zone on the TFT substrate 50 that surrounds by signal wire 11 with sweep trace 12 that signal wire 11 intersects, be provided with the pectination pixel capacitors 54 and the pectination common electrode 55 of mutual interdigitated.
By the part of each sweep trace 12 of public use, form the gate electrode 25 of TFT13.Make the drain electrode 29 and pixel capacitors 54 couplings of FT13 by the contact through hole of pixel capacitors 56.Contact through hole by common electrode 57 makes public wire conductors 51 and common electrode 55 couplings.Source electrode 28 and signal wire 11 couplings.
In this TFT13, switching signal is applied to gate electrode 25 by sweep trace 12, by signal wire 11 picture intelligence is offered source electrode 28, thereby electric charge injected or write pixel capacitors 54.
Figure 12 A-12D, Figure 13 E-13F and Figure 14 are cross-sectional views, and each width of cloth all is described in the structure of workpiece during the manufacturing process of TFT substrate of Figure 10.The xsect that Figure 12 A-12D, Figure 13 E-13F and each width of cloth of Figure 14 all comprise the cross-sectional view got along the line A-A of Figure 11, got along the line B-B of Figure 11, the cross-sectional view of being got along the line C-C of Figure 11.In these accompanying drawings, the cross-sectional view of being got along the line A-A of Figure 11 has illustrated the TFT part, the xsect of being got along the line B-B of Figure 11 shows pixel parts, and the cross-sectional view of being got along the line C-C of Figure 11 has illustrated the contact through hole part of common electrode (ITO-COM part).Figure 13 E-13F is described in the making step that carries out after the making step shown in Figure 12 A-12D.Figure 14 is described in the making step that carries out after the making step shown in Figure 13 E-13F.
As Figure 12 A-12D, Figure 13 E-13F and shown in Figure 14, at first, preparation glass substrate 10a.On glass substrate 10a, form the conducting film that constitutes by Cr, Mo, Cr/Al stack membrane and Mo/Al stack membrane etc. by sputter, film thickness is about 100-300nm.By using photoetch method, make conductive film pattern to form gate electrode 25, sweep trace (not illustrating in the accompanying drawing), public wire conductors 51 and sweep trace terminals (not illustrating in the accompanying drawing) (referring to Figure 12 A).
Then, use plasma CVD (chemical vapor deposition) method, form by silicon nitride (SiNx) formation gate insulating film 26, film thickness is about 300-500nm.In addition, form one deck amorphous silicon (a-Si), its film thickness is about 150-300nm, forms the phosphorus-doped amorphous silicon (n of one deck then
+A-Si), its film thickness is about 30-50nm.By using photoetch method, the pattern of making these layers is to form semiconductor layer 27 (referring to Figure 12 B).
Form the conducting film that is made of Cr, Mo, Cr/Al/Cr stack membrane and Mo/Al/Mo stack membrane etc. by sputter, film thickness is about 100-400nm.By using photoetch method, make conductive film pattern with the pixel capacitors 58 that forms source electrode 28, drain electrode 29, signal line layer, pixel capacitors 58 signal wire 11 and signal wire terminals (not illustrating in the accompanying drawing) (referring to Figure 12 c) adjacent one another are by therebetween.
Use the plasma CVD method, form by passivating film 30, passivating film 30 by as the inoranic membrane formation of silicon nitride (SiNx) film etc. and so on, film thickness is about 100-300nm (seeing Figure 12 D).
Then, form organic insulating film 59 by using positivity novolaks photoresist, film thickness is about 2.0-3.5 μ m, makes the pattern of this organic insulating film so that form opening (referring to Figure 13 E) in will forming each part of contact through hole.
Use photoengraving technology to carry out plasma etching subsequently, dry ecthing passivating film 30 makes drain electrode 29 terminal portions contact through hole that is used for pixel capacitors 56 that exposes and the contact through hole that signal wire end (accompanying drawing does not illustrate) is exposed with formation.Also etching passivating film 30 and gate insulating film 26 make public wire conductors 51 contact through hole that is used for public wire conductors 57 that exposes and the contact through hole that signal wire end (accompanying drawing does not illustrate) is exposed with formation.At this, by carrying out plasma etching (referring to Figure 13 F) with the similar mode of first embodiment.
Next, on contact through hole 56,57 and on organic insulating film 59, form the nesa coating that constitutes by the ITO film by sputter.By the pattern of photoengraving technology making nesa coating, to form pixel capacitors 54, common electrode 55 and the connection electrode (not illustrating in the accompanying drawing) on signal wire terminals and sweep trace terminals.In the case, pixel capacitors 54 is positioned on the corresponding organic insulating film 59 in position with the pixel capacitors 58 of signal line layer.Common electrode 55 is positioned on the organic insulating film corresponding with the position of signal wire 11 59 (referring to Figure 14).
Thus, obtain a kind of like this structure: the contact through hole by pixel capacitors 56 makes pixel capacitors 54 and 28 couplings of source electrode, contact through hole by common electrode 57 makes common electrode 55 and public wire conductors 51 couplings, makes connection electrode and the coupling of signal wire terminals by the contact through hole of signal wire and the contact through hole of sweep trace respectively.
By and the similar mode of first embodiment, when on organic insulating film, forming the nesa coating that constitutes by the ITO film, heating TFT substrate 50 so that the temperature of TFT substrate 50 become near Celsius temperature 100-170 degree (℃).On the other hand, when forming nesa coating, under heated condition not, promptly under the room temperature, can form film and with oxygen flow speed ratio (O
2/ Ar) adjust to preferred 0.5% or lower, 0.2% or lower better near 1% or lower.Further, after forming this film, under the Celsius temperature of 200-240 degree, carry out annealing in process.
Then, similar with first embodiment, on the surface of TFT substrate 50, form alignment films 35, and carry out orientation process.Preparation comparative electrode 17 forms black matrix 18, color filter 31 and alignment films 37, and carries out orientation process on comparative electrode 17.Then, TFT substrate 50 is faced mutually with relative substrate 17, and fixed by encapsulant 20 and liner 36 therebetween.Liquid crystal material 1 is injected into TFT substrate 50 and relatively the gap between the substrate 17 from filling orifice.Then, seal filling orifice with encapsulant.Thus, obtain to have the LCD panel of wide visual angle and high aperture ratio.
As mentioned above, in first embodiment and second embodiment, when on organic insulating film, forming the nesa coating that constitutes by the ITO film, heating TFT substrate so that the temperature of TFT substrate become near Celsius temperature 100-170 degree (℃), this point is important.On the other hand, when forming nesa coating, under heated condition not, can form this film and with oxygen flow speed ratio (O
2/ Ar) adjust to preferred 0.5% or lower, 0.2% or lower better near 1% or lower.Further, after this film of sputter, under the Celsius temperature of 200-240 degree, carry out annealing in process.
Obtain above-mentioned condition based on following consideration: when the sputter nesa coating, the relation between substrate temperature and the vertical inhomogeneous occurrence rate of strip, oxygen flow speed ratio (O
2/ Ar) and the relation of layer between the resistance, the etching residue of organic insulating film and painted relation etc.
Figure 15 is a curve map, shows when forming the ITO film according to first embodiment of the invention with sputter substrate temperature and the inhomogeneous example that the mutual relationship between the speed occurs of vertical strip.As shown in figure 15, when at heating TFT substrate 10 time during sputtering ITO film and substrate temperature rise to 50 ℃, 100 ℃, 150 ℃ and when further rising to 200 ℃ from room temperature, the speed of the vertical inhomogeneous appearance of strip little by little diminishes.The at room temperature vertical inhomogeneous occurrence rate of strip is about 40%, but the inhomogeneous occurrence rate of vertical strip becomes approximately 5% 100 ℃ the time, and becomes in the time of 150 ℃ and is approximately zero.
In this example, carry out heating of substrate at heating chamber earlier, heating chamber separates so that effectively organic insulating film is carried out degasification with the chamber that forms film.In this example, in order to keep the temperature of substrate, heating of substrate can or do not forming in the chamber of film and carrying out.
Figure 16 is a curve map, shows the example by the relation between oxygen flow speed ratio when non-heated condition (being under the room temperature) sputter forms the ITO film and the layer resistance.As shown in figure 16, when the sputtering ITO film, and as oxygen flow speed ratio (O
2/ Ar) approximately rising at 2.5% o'clock from 0%, a layer resistance value increases gradually.Layer resistance value became about 65 Ω/ at 0.5% o'clock, approximately became 80 Ω/ at 1% o'clock, became about 110 Ω/ at 1.5% o'clock.Simultaneously, dispersion value (dispersion) 3 σ of layer resistance value also increased gradually, became about 8 Ω/ at 0.5% o'clock, became about 23 Ω/ at 1% o'clock, became about 39 Ω/ at 1.5% o'clock.
Figure 17 A-17C is an illustration, and each width of cloth all is described under the non-heating condition after the sputtering ITO film and after 200 ℃ of annealing, at the example of substrate internal layer distribution of resistance.Shown in Figure 17 A-17C, oxygen flow speed ratio (O when the sputtering ITO film
2/ Ar) rise to 0.8% and rise at 2.1% o'clock from 0.05%, degenerate in the increase of the state of substrate internal layer distribution of resistance along with layer resistance.
Figure 18 is an illustration, the relation when showing the sputtering ITO film by form between the state of substrate temperature and etching residue.At this, the etching agent of the etching agent of use chloride series and chloroazotic acid system carries out the etching of ITO film.As shown in figure 18, when substrate temperature was 100 ℃, 150 ℃ and 170 ℃, the state of etching residue was quite satisfactory or satisfied.Yet when substrate temperature was 200 ℃, the quantitative change of the etching residue of ITO film was big and can not carry out the film etching by ITO.
This be because since the degasification of organic insulating film make the mass change of ITO film or degenerate.Therefore, preferably, substrate temperature should be less than or equal to 170 ℃ when the sputtering ITO film.
Figure 19 is an illustration, shows under non-heated condition after the sputtering ITO film relation in annealing temperature and substrate between the ITO film line width homogeneity, and annealing temperature and the organic insulating film relation between painted by form.As shown in figure 19, for ITO film line width homogeneity, when annealing temperature was 150 ℃ in a second embodiment, show state degenerated.Painted for organic insulating film, when annealing temperature is 240 ℃, be admissible, but when annealing temperature is 250 ℃, the transmittance severe exacerbation.
This is because be 240 ℃ or will decompose the photo anti-corrosion agent material of organic insulating film when higher in temperature.So preferably, annealing temperature is in 200 ℃ to 240 ℃ scope after the sputter of ITO film, annealing temperature is better in 200 ℃ to 230 ℃ scope.
Figure 20 is an illustration, shows the difference of the contact resistance value of upside signal terminal and downside signal terminal (Fig. 1) part in first embodiment and relation between the uneven condition of vertical stripes occurs by form.As shown in figure 20, when the difference of the contact resistance value between upside signal terminal and the downside signal terminal part was 0 Ω or 1000 Ω, it was inhomogeneous not observe vertical strip.Yet, it is inhomogeneous to observe slight vertical strip when the difference of the contact resistance value between upside signal terminal and the downside signal terminal is 1500 Ω, and it is inhomogeneous clearly to observe vertical strip when the difference of the contact resistance value between upside signal terminal and the downside signal terminal is 3000 Ω.Therefore, preferably, the difference of the contact resistance value between upside signal terminal and the downside signal terminal is 1500 Ω or littler, and difference is 1000 Ω or more hour better.
And in and LCD that on organic interlayer insulating film form pixel capacitors that make by above-mentioned method for making, preferably, nesa coating each coupling unit between nesa coating and lower metal film has crystallizability.It is the reasons are as follows.That is,, when the part of the nesa coating that can determine from the observed result of use transmission electron microscope (TEM) to contact with lower metal film has crystallizability, think not observe as the uneven defective of vertical strip.
Figure 21 A and Figure 21 B are schematic illustration, show in the LCD that method for making is made according to the present invention the example of the observations of the TEM of the coupling unit between nesa coating and the lower metal film.
Shown in Figure 21 A, when the coupling unit between lower floor's metal film and the nesa coating is observed crystallizability, promptly when atomic arrangement reached interface portion (interface portion), the lattice of ITO was connected to the Cr part and vertical strip do not occur inhomogeneous.On the other hand, shown in Figure 21 B, when the coupling unit between lower floor's metal film and the nesa coating did not almost observe crystallizability, the lattice of ITO was free of attachment to the Cr part and vertical strip occurs inhomogeneous.Like this, according to detailed structure, can judge that LCD is a good product or the product that scarce limit is arranged in the ITO/Cr interface portion.
Therefore, preferably, under at least one state of following various states, make LCD with the pixel capacitors that on organic interlayer insulating film, forms, separate with sweep trace and signal wire.
1, in the time of substrate temperature 100-170 ℃, carries out the sputter of nesa coating.
2, before the sputter of carrying out nesa coating, heated substrate is also carried out ise (sputter etching) then under same vacuum condition.That is, in substrate being sent to the chamber that forms film before, in the heating chamber heated substrate and in advance substrate is carried out degasification.In addition, by ise, remove lip-deep oxide and fluoride at the lower metal film of each contact through hole part.
3, carry out the sputter of nesa coating under non-heated condition, the oxygen flow speed ratio is set to 1% or lower.Further, after sputter, anneal.In the case, in 200 ℃-240 ℃ temperature range, anneal.
When nesa coating is the ITO film with at lower metal is that these conditions are effective especially when being the alloy of principal ingredient by Cr or Cr.
Common using gases CF
4, CF
6Deng the contact through hole that forms in passivating film or gate insulating film is carried out etching.When under lower metal is situation about constituting for the alloy of Cr by Cr or principal ingredient, carrying out over etching (over-etching), etching Cr or principal ingredient are not the alloy of Cr, fluorine (F) element is retained on the surface of metal level, and is big thereby the contact resistance between nesa coating and the lower metal becomes.
Preferably, with using plasma etching to carry out the etching of above-mentioned contact through hole with low-energy atomic group (radical).Usually have high etching energy as reactive ion etching (reactive ion etching) the etching contact through hole, the use ion,, find that a large amount of fluorine (F) elements is retained in the surface of Cr film as analysis result to the ITO/Cr interface.
As mentioned above,, confirm that as suppressing the method that contact resistance value increases, above-mentioned state according to the present invention is quite effective by the experiment that the present inventor carries out.
Like this, according to the present invention, in having the high-resolution liquid crystal display board of organic interlayer insulating film structure or have in the LCD panel of public storage organization etc., optimize the condition of the ITO film be formed for constituting pixel capacitors, for example, heating-up temperature, oxygen flow speed ratio etc.
That is, in advance substrate is carried out after the degasification by heated substrate in heating chamber, substrate is sent to the chamber that forms film, the substrate temperature when being controlled at the ITO sputter is 100-170 ℃.Carry out sputter under the non-heated condition as room temperature, the oxygen flow speed ratio is set to 1% or lower.In addition, after sputter, anneal.In the case, in 200-240 ℃ temperature range, anneal.Thereby, obtaining a kind of like this structure, the part of the ITO film on the lower metal of contact through hole part has crystallizability.
Therefore, can avoid the degasification influence of organic interlayer insulating film, the film quality that improves the ITO film makes it have crystallizability.Can also reduce the contact resistance between ITO film and the lower metal and make this contact resistance even, and not cause that the contact resistance in substrate surface increases and its unevenness.
The result is to suppress the unevenness of the vertical strip in the high-resolution liquid crystal display board.Can reduce and have the TN of public storage organization or the horizontal interference in the IPS type LCD panel.
In the above-described embodiment, as an example, the organic insulating film of use as photosensitive phenolic varnish type photoresist film is as applying the dielectric film that forms.Yet the present invention is not limited to such film.Certainly, can use polyimide resin, acryl resin etc., also can use the inorganic resin material, silicon dioxide for example, silicon nitride etc.Also can use the material of non-photosensitivity.In the case, by and the common similar mode of photoengraving process, must carry out etching process and the resist after developing is removed process.
And in the above-described embodiments, the process of the formation dielectric film that provides by coating and the process that forms opening in passivating film are used photoengraving process separately.Yet, also can use same process to form such opening.
In addition, in the above-described embodiments, use anti-phase staggered channel etching (interted staggeredchannel etching) type TFT to describe LCD.Yet, also can use the TFT of ditch pipe protection (channel protection) type or noninverting staggered (non-inverted staggered) type.In addition, the present invention not only can also be applied among the TFT of staggered (staggered) type, and can also be applied among the coplanar type TFT.And the present invention can not only be applied to amorphous silicon (a-Si) TFT, and can be applied to polysilicon (p-Si) TFT.Further, each on-off element can be MIM (metal-insulator-metal) type element.
As mentioned above, according to the present invention, a kind of LCD is provided, mode with matrix or grid is provided with bus, on-off element and bus coupling, by applying on the interlayer insulating film that forms pixel capacitors is being set, pixel capacitors is by film formed contact through hole of interlayer insulation and on-off element coupling.In the process of making LCD, when forming nesa coating on by the interlayer insulating film that applies formation, the temperature of substrate is controlled to be 100 ℃-170 ℃.On the other hand, when forming nesa coating with non-heated condition on interlayer insulating film, the oxygen flow speed ratio is set to 1% or lower, anneals after forming film.
Thus, the ITO film on the lower metal of contact through hole part has crystallizability.When etching ITO film on interlayer insulating film, do not produce etching residue.Further, the contact resistance between ITO film and lower metal can be reduced equably, the display defect on the display screen of LCD can be avoided.
In above-mentioned instructions, the present invention has been described with reference to specific embodiment.Yet one one of skill in the art will recognize that the various modifications and variations that can make under the situation of the scope of the invention that claim is asked for protection below not breaking away from.Therefore, instructions and accompanying drawing are not restricted description, but schematically describe, and all such modifications all comprise within the scope of the invention.Therefore, the present invention includes within the scope of the appended claims all modifications and variation.
Claims (5)
1, a kind of method of making LCD, this LCD have mode with grid be arranged on on-chip bus, with the on-off element of bus coupling, apply be provided with on the interlayer insulating film that forms by the film formed pixel capacitors of electrically conducting transparent, pixel capacitors is by film formed contact through hole of interlayer insulation and on-off element coupling, and described method comprises:
Non-heated condition and oxygen and argon gas stream speed ratio be 0.2% or still less state under, on interlayer insulating film, form nesa coating by sputtering method;
After forming nesa coating, anneal.
2, the method for making LCD as claimed in claim 1 is characterized in that, anneals under the temperature of 200 ℃ of-240 ℃ of degree.
3, the method for making LCD as claimed in claim 1 is characterized in that, is organic insulating film by applying the interlayer insulating film that forms.
4, the method for making LCD as claimed in claim 1, it is characterized in that, LCD has the metal film with nesa coating coupling, and nesa coating is made by the ITO film, with the metal film of nesa coating coupling be that the alloy of principal ingredient is made by chromium or chromium.
5, the method for making LCD as claimed in claim 1 is characterized in that described contact through hole is film formed by passivating film and interlayer insulation, and described method also comprises:
When forming, form the opening of passivating film by plasma etching by passivating film and the film formed contact through hole of interlayer insulation.
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| CNB2005100836141A CN100437251C (en) | 2002-08-16 | 2002-08-16 | Liquid crystal display with transparent conductive film on coated formed sandwich insulation film |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5317193A (en) * | 1992-05-07 | 1994-05-31 | Mitsubishi Denki Kabushiki Kaisha | Contact via for semiconductor device |
| US5989782A (en) * | 1996-03-26 | 1999-11-23 | Sharp Kabushiki Kaisha | Method for producing liquid crystal display device |
| JP2000104166A (en) * | 1998-09-30 | 2000-04-11 | Sharp Corp | Formation of transparent electrically conductive film |
| US6310674B1 (en) * | 1995-12-27 | 2001-10-30 | Canon Kabushiki Kaisha | Method of making a display device with electrode characteristics |
| CN1328268A (en) * | 2000-05-25 | 2001-12-26 | 精工爱普生株式会社 | Liquid crystal apparatus, its making method and electronic apparatus |
-
2002
- 2002-08-16 CN CNB2005100836141A patent/CN100437251C/en not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5317193A (en) * | 1992-05-07 | 1994-05-31 | Mitsubishi Denki Kabushiki Kaisha | Contact via for semiconductor device |
| US6310674B1 (en) * | 1995-12-27 | 2001-10-30 | Canon Kabushiki Kaisha | Method of making a display device with electrode characteristics |
| US5989782A (en) * | 1996-03-26 | 1999-11-23 | Sharp Kabushiki Kaisha | Method for producing liquid crystal display device |
| JP2000104166A (en) * | 1998-09-30 | 2000-04-11 | Sharp Corp | Formation of transparent electrically conductive film |
| CN1328268A (en) * | 2000-05-25 | 2001-12-26 | 精工爱普生株式会社 | Liquid crystal apparatus, its making method and electronic apparatus |
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