JP2006317923A5

JP2006317923A5 -

Info

Publication number: JP2006317923A5
Application number: JP2006109612A
Authority: JP
Filing date: 2006-04-12
Publication date: 2009-04-23
Anticipated expiration: 2026-04-12

Claims

A first transistor;
A second transistor;
A pixel electrode;
The respective potentials of the pixel electrode and the scanning line, a pixel including a circuit for controlling conduction and non-conduction of the gate and the power supply line of the second transistor,
The first transistor, the gate of the scanning lines, one signal line of the source or drain is electrically connected the other of the source or drain connected to the gate of the second transistor,
The second transistor, one is the power line of a source or drain, source or display device other one thereof, characterized in Tei Rukoto are electrically connected to the pixel electrode.

A first transistor;
A second transistor;
A pixel electrode;
A circuit for controlling conduction and non-conduction between the gate of the second transistor and the power supply line according to respective potentials of the pixel electrode and the first scanning line ;
The potential of the second scanning line, a pixel including a control device for controlling conduction and non-conduction of the gate and the second scan line of the second transistor,
The first transistor, the gate of the first scan line, one signal line of the source or drain is electrically connected the other of the source or drain connected to the gate of the second transistor,
The second transistor, a display device in which one of the source or drain to the power supply line, a source or wherein the other of the drain is electrically connected to the pixel electrode.

A first transistor;
A second transistor;
A pixel electrode;
A circuit for controlling conduction and non-conduction between the gate of the second transistor and the power supply line by respective potentials of the pixel electrode, the first scanning line, and the second scanning line ;
The potential of the second scanning line, a pixel including a control device for controlling conduction and non-conduction of the gate and the second scan line of the second transistor,
The first transistor, the gate of the first scan line, one signal line of the source or drain is electrically connected the other of the source or drain connected to the gate of the second transistor,
The second transistor, a display device in which one of the source or drain to the power supply line, a source or wherein the other of the drain is electrically connected to the pixel electrode.

A first transistor;
A second transistor;
A pixel electrode;
A circuit for controlling conduction and non- conduction between the gate of the second transistor and the power supply line according to respective potentials of the pixel electrode and the first scanning line ;
The potential of the second scanning line, a pixel including a control device for controlling conduction and non-conduction of one and the power supply line of the source or drain of said second transistor,
The first transistor, the gate of the first scan line, one signal line of the source or drain is electrically connected the other of the source or drain connected to the gate of the second transistor,
The second transistor, the power supply line and one of a source or drain via the control device, the source or display device other one thereof, characterized in Tei Rukoto are electrically connected to the pixel electrode.

A first transistor;
A second transistor;
A pixel electrode;
A third transistor;
A pixel including a fourth transistor, a,
The first transistor is electrically to the gate scanning line, to one signal line of the source or drain, to one of a source or drain of the gate and the third transistor of the other said second transistor source or drain Connected,
The second transistor, one is power line of a source or drain, source or is electrically connected to a gate of said third transistor other one thereof and the pixel electrode,
The third transistor is electrically connected to one other of the source or drain of the source or drain of said fourth transistor,
The fourth transistor to the gate of the scanning lines, a display device, characterized in that the other of the source or drain is electrically connected to the power line.

A first transistor;
A second transistor;
A pixel electrode;
A third transistor;
A fourth transistor;
A control element , and a pixel including
The first transistor, the gate of the first scan line, one signal line of the source or drain, the other of the source or drain of said second transistor gate, a source and a drain of said third transistor on the other hand, and it is electrically connected to one terminal of said control element,
The second transistor, one is power line of a source or drain, source or is electrically connected to a gate of said third transistor other one thereof and the pixel electrode,
The third transistor is electrically connected to one other of the source or drain of the source or drain of said fourth transistor,
The fourth transistor to the gate of the first scan line, the other of the source or drain is electrically connected to the power line,
In the display device , the other terminal of the control element is electrically connected to the second scanning line.

A first transistor;
A second transistor;
A pixel electrode;
A third transistor;
A fourth transistor;
A fifth transistor;
A control element , and a pixel including
The first transistor, the gate of the first scan line, one signal line of the source or drain, the other of the source or drain of said second transistor gate, a source and a drain of said third transistor Electrically connected to one and one terminal of the control element ;
The second transistor, one is power line of a source or drain, source or is electrically connected to a gate of said third transistor other one thereof and the pixel electrode,
The third transistor is electrically connected to one other of the source or drain of the source or drain of said fourth transistor,
The fourth transistor to the gate of the first scan line is electrically connected to one of a source or drain of the other said fifth transistor of a source or drain,
It said fifth transistor, a gate of the second scan line, the other of the source or drain is electrically connected to the power line,
The control element, a display device, characterized in that the other terminal is connected electrical to said second scan line.

A first transistor;
A second transistor;
A pixel electrode;
A third transistor;
A fourth transistor;
A pixel including a fifth transistor, a,
The first transistor, the gate of the first scan line, one of a source or drain connected to the signal lines, the source or drain of the gate and the third transistor of the other said second transistor source or drain on the other hand, they are electrically connected,
The second transistor, to one of a source or drain of one said fifth transistor of a source or drain, the other of the source or drain is electrically connected to a gate of the third transistor and the pixel electrode,
The third transistor is electrically connected to one other of the source or drain of the source or drain of said fourth transistor,
The fourth transistor to the gate of the first scan line, the other of the source or drain is electrically connected to the power supply line,
It said fifth transistor, a gate of the second scan line, the display device characterized by the other of the source or drain is electrically connected to the power line.

In any one of Claim 2, Claim 3, Claim 6 or Claim 7,
The display device, wherein the control element is a diode.

In any one of Claim 2, Claim 3, Claim 6 or Claim 7,
The display device is characterized in that the potentials of the power supply line and the second scanning line are kept at a potential at which the second transistor is turned off.

In claim 6 or claim 7,
The control element is a sixth transistor;
One terminal of the control element is a gate and a drain of the sixth transistor,
The other terminal of the control element is a source of the sixth transistor.

In any one of Claim 5 thru | or Claim 8,
The display device, wherein the third transistor is a transistor having a plurality of gates electrically connected to each other.

In any one of Claim 5 thru | or Claim 8,
The display device, wherein the first transistor and the fourth transistor have different polarities.

In any one of Claims 1 thru / or Claim 13,
Display device characterized by having a counter electrode, a light emitting layer provided between the pixel electrode and the counter electrode.

An electronic apparatus using the display device according to any one of claims 1 to 1 4.