JP2006184888A5

JP2006184888A5 -

Info

Publication number: JP2006184888A5
Application number: JP2005344461A
Authority: JP
Filing date: 2005-11-29
Publication date: 2008-12-25
Anticipated expiration: 2025-11-29

Claims

And the door transistor,
A capacitive element;
A switch,
A wiring and, the,
The gate of the bets transistor, the wiring and are electrically connected via the capacitive element,
Before one of the pin of Quito transistor is a semiconductor device which is characterized in that through said switch is electrically connected to the gate of said transistor.

And the door transistor,
A capacitive element;
A first switch;
A second switch;
A first wiring ;
A second wiring ;
The gate of the bets transistor is electrically connected to the first wiring through the capacitive element,
The first terminal of the pre Quito transistor is electrically connected to the pixel electrode,
Before the second terminal of Quito transistor is the second wiring electrically connected via the front Symbol first switch,
The semiconductor device, wherein the second terminal of the transistor is electrically connected to the gate of the transistor through the second switch.

And the door transistor,
A capacitive element;
A first switch;
A second switch;
A third switch;
A first wiring ;
A second wiring ;
A third wiring ;
The gate of the bets transistor is electrically connected to the first wiring through the capacitive element,
The first terminal of the pre Quito transistor is electrically connected to the pixel electrode,
A first terminal of the transistor is electrically connected to the third wiring through the third switch;
Before the second terminal of Quito transistor is the second wiring electrically connected via the front Symbol first switch,
The semiconductor device, wherein the second terminal of the transistor is electrically connected to the gate of the transistor through the second switch.

And the door transistor,
A capacitive element;
A first switch;
A second switch;
A third switch;
A fourth switch ;
A first wiring ;
A second wiring;
A third wiring ;
Have,
The gate of the bets transistor is one terminal electrically connected to the capacitive element,
The other terminal of the capacitive element is connected to the first wiring and electrically via a pre Symbol third switch,
The other terminal of the capacitive element is electrically connected to the third wiring via the fourth switch,
The first terminal of the pre Quito transistor is electrically connected to the pixel electrode,
Before the second terminal of Quito transistor is the second wiring electrically connected via the front Symbol first switch,
The semiconductor device, wherein the second terminal of the transistor is electrically connected to the gate of the transistor through the second switch.

In any one of Claims 2 thru | or 4 ,
The transistor is an N-channel transistor,
The first switch is an N-channel transistor,
The second switch is a semiconductor device which is a transistor of the N-channel type.

In any one of Claims 2 thru | or 4 ,
The transistor is an N-channel transistor,
The first switch is a P-channel transistor;
The semiconductor device, wherein the second switch is an N-channel transistor.

In any one of Claims 2 thru | or 6 ,
A plurality of pixels having at least the pixel electrode, the transistor, the capacitor, the first switch, and the second switch;
Each of the pixels represents one of a plurality of color elements;
The second wiring, the semiconductor device characterized by being provided for each pixel of the color element, the potential for each pixel of the color element is set.

In claim 7 ,
The semiconductor device , wherein the plurality of pixels are arranged in a delta arrangement.

A transistor,
A capacitive element;
A first switch;
A second switch;
A third switch;
A first wiring;
A second wiring;
A gate of the transistor is electrically connected to the first wiring through the capacitor;
A gate of the transistor is electrically connected to the second wiring through the third switch;
A first terminal of the transistor is electrically connected to the pixel electrode;
A second terminal of the transistor is electrically connected to the second wiring through the first switch;
A semiconductor device, wherein the second terminal of the transistor is electrically connected to the gate of the transistor through the second switch.

A transistor,
A capacitive element;
A first switch;
A second switch;
A third switch;
A first wiring;
A second wiring;
A gate of the transistor is electrically connected to the first wiring through the capacitor;
A first terminal of the transistor is electrically connected to the pixel electrode;
A second terminal of the transistor is electrically connected to the second wiring through the third switch and the first switch;
A semiconductor device, wherein the second terminal of the transistor is electrically connected to the gate of the transistor through the second switch and the third switch.

An electronic apparatus comprising: the semiconductor device according to claim 1; and an operation switch.