JP2006313999A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of changing a logic function of a circuit with a low voltage. <P>SOLUTION: The semiconductor device, equipped with a changeable logic unit whose logic function can be changed with a switch, has the switch portion composed of, for example, an MOS transistor M3 as a switch between signal lines D1 and D2, a capacitor C1 holding an ON or OFF state of the M3, MOS transistors M1 and M2 setting information to be held by the capacitor C1, a phase shifting element PC1, etc. In this constitution, the ON or OFF state of the MOS transistor M3 is determined in accordance with the state of the phase shifting element PC1 which is written as a set or reset state with a low voltage from a control line DL, etc. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly, to a technique effective when applied to a semiconductor device having a variable logic unit that can set a logic function in a programmable manner and a nonvolatile memory unit that can rewrite stored information.

  For example, Patent Document 1 describes a technique for configuring an arithmetic circuit using a variable logic unit called an FPGA (Field Programmable Gate Array) or an FPLD (Field Programmable Logic Device). Non-Patent Document 1 describes a technique in which an electrically rewritable nonvolatile memory element such as an EEPROM or a flash memory is used as a memory cell of an FPGA.

  On the other hand, the development of a technique called “phase change memory” as described in Non-Patent Document 2 is in progress. This is a technology that uses phase change films and phase change elements that are also used in rewritable optical discs such as CDs and DVDs as storage elements. Whether the phase change elements are in an amorphous state or a crystalline state, Memorize “0” and “1”. In optical disks, writing is performed by locally heating with a high-power laser to create an amorphous state or a crystalline state. On the other hand, in the phase change memory, writing is performed by locally heating with a current pulse, and reading is performed by detecting a change in electrical resistance value due to a change in state.

In order to realize such a read / write operation of the phase change memory, one end of the phase change element is connected to a heater portion provided at the output of the transistor, and the other end is connected to a metal for flowing current. In this way, it is possible to pass a current only through a portion selected by the transistor. There are rewrite operations called reset operation and set operation. The reset operation is an operation (amorphous state and electrical resistance is high) in which a large current is once passed through the phase change element to be heated and dissolved, and then the current is turned off and rapidly cooled. The set operation is an operation in which a current smaller than the current in the reset operation continues to flow for a certain period of time, and the phase change element is crystallized by heat during that time (electrically low in the crystallized state). In reading, the transistor is turned on, and the magnitude of the resistance of the phase change element at this time is read by the current flowing through the transistor.
JP-A-10-1111790 “Interface”, CQ Publishing Co., Ltd., November 2001, p. 67-68 “Ovonic Unified Memory-High Performance Non-volatile Memory for Single Memory and Embedded Applications (A High-performance Non-volatile Technology for Memory and Alone Memory Memory)” Gill, T .; Lowrey, J. et al. Park, Proceedings of 2002 IEEE International Solid State Circuits Conference, February 2002

  By the way, as a result of the study of the technique of the variable logic unit as described above, the following (1) to (3) have been clarified.

  (1) As described above, an EEPROM, a flash memory, or the like can be used as the memory cell of the variable logic unit. Generally, a voltage of about 10 V or more is required for rewriting these elements. On the other hand, the power supply voltage supplied to the semiconductor device has been decreasing with generations and has recently been around 1V. In addition, the breakdown voltage of the MOS transistor is decreasing with the generation of miniaturization. Therefore, it is not preferable to use a voltage of about 10 V in the prior art, and a memory cell that can be rewritten at a low voltage is required.

  (2) When a CPU is embedded in a semiconductor device or enclosed in a single package, a memory cell that operates with a large capacity and a low voltage is required to store an operation program and control data of the CPU. However, since the conventional technique uses an EEPROM, a flash memory, or the like, the low voltage operation cannot be performed as described above.

  (3) For example, when the memory cell of the variable logic unit is composed of only an EEPROM or a flash memory, the area can be reduced, but the memory cell cannot be rewritten at high speed. On the other hand, in the case where the memory cell of the variable logic unit is constituted by SRAM and EEPROM or flash memory is used as means for loading initial data into the SRAM and as means for backing up end data from the SRAM, time may be required for loading and backup. There is. In addition, once loaded, it is possible to rewrite at high speed using an SRAM, but it is difficult to reduce the area because of the use of an SRAM and the need for an EEPROM or flash memory as backup means. Therefore, a memory cell capable of high-speed operation with a small area is required.

  The present invention is intended to solve such problems, and the above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The semiconductor device of the present invention includes a circuit unit having a variable logic function, and the circuit unit can take an on state or an off state corresponding to the state of the phase change element and the electrical resistance of the phase change element. The logic function of the circuit unit is set based on the on or off state of the switch.

  As described above, by enabling the logic function of the circuit unit to be set by the phase change element, the logic function can be set and changed at a low voltage, so that the semiconductor device can be reduced in voltage or power consumption. . In addition, the time required for changing the setting of the logic function of the circuit unit can be shortened, for example, compared to the case where it is realized only by the flash memory. It becomes possible.

  Here, the circuit unit can include, for example, a plurality of circuit blocks each having a variable logic function, and a connection relationship between the plurality of circuit blocks can be set using the switches. By using such a configuration, it becomes possible to easily construct a large-scale variable logic unit capable of low voltage operation. Moreover, it is possible to reduce the area and speed of a large-scale variable logic unit.

  The semiconductor device of the present invention includes a processor, a memory cell including a phase change element, and includes a nonvolatile memory unit in which a processing program in the processor is stored, and a circuit unit having a variable logic function. ing. The circuit unit includes a phase change element and a switch that can be turned on or off in accordance with the state of electrical resistance of the phase change element. It can be changed according to the resistance state of the phase change element.

  As described above, by realizing a semiconductor device in which a memory used in a processor and a memory used in a circuit unit having a variable logic function are configured by phase change elements, the semiconductor device can be compared with a case where a flash memory or the like is used. The voltage can be lowered, and the reliability of the semiconductor device can be improved.

  The semiconductor device of the present invention includes a first control line and a second control line, a first transistor whose on state or off state is controlled by a voltage of the control node, and between the first control line and the second control line. A second transistor and a first phase change element connected in series to each other, a third transistor provided between a connection node of the second transistor and the first phase change element and a control node of the first transistor, And a memory circuit that holds the voltage of the control node of one transistor. Then, the state of the first phase change element is set using the first control line, the second control line, and the second transistor, and data corresponding to the state of the first phase change element is transferred to the memory circuit via the third transistor. By setting, the first transistor functions as an on / off switch capable of setting and holding the state. The on / off switch is used as a switch for changing the logic function, for example. Further, the memory circuit can be constituted by, for example, a capacitor or a flip-flop.

  By using such a configuration, it is possible to realize a nonvolatile switch capable of setting a state with a low voltage. In addition, it is possible to realize a switch that can switch at high speed with a small area.

  A brief description of effects obtained by typical inventions among inventions disclosed in the present application enables a reduction in voltage of a semiconductor device including a variable logic function. In addition, the semiconductor device including the variable logic function can be reduced in area or speeded up.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  FIG. 1 is a circuit diagram showing an example of a configuration of a switch unit included in a semiconductor device according to an embodiment of the present invention. The switch unit RC1 shown in FIG. 1 includes, for example, three MOS transistors M1, M2, and M3, a phase change element PC1, a capacitor C1, and the like. MOS transistor M2 has one of its source / drain connected to control line DL, the other connected to node N1, and its gate connected to control line RW. Phase change element PC1 has one end connected to N1 and the other end connected to control line SL. That is, MOS transistor M2 and phase change element PC1 are connected in series between control line DL and control line SL, and the connection point is node N1.

  In the MOS transistor M1, one of its source / drain is connected to the node N1, the other is connected to the node N2, and the gate is connected to RW like M2. MOS transistor M3 has one of its source / drain connected to signal line D1, the other connected to signal line D2, and its gate connected to node N2. A capacitor C1 is provided between the node N2 and the reference potential node GND.

  When such a configuration is used, D1 and D2 can be electrically connected or disconnected depending on the potential of the gate node N2 of the MOS transistor M3. That is, the MOS transistor M3 can function as a nonvolatile switch. By combining these functions, it is possible to switch functions of various circuits as will be described later. The capacitor C1 stores information to be given to the gate of the MOS transistor M3, and the MOS transistor M1 is to give information to the gate, and the information is the equivalent resistance of M2 and PC1. It is determined by the ratio.

  Here, the phase change element PC1 can take a high resistance state and a low resistance state as described in the background art section. Then, the voltage generated at N1 varies depending on the state of the phase change element, and the state of the switch can be changed (detailed operation will be described later). If necessary, a switch may be provided between N2 and the MOS transistor M3, and this may be controlled to give the information stored in the capacitor C1 to the MOS transistor M3 only when desired. .

  FIG. 2 is a circuit diagram showing an example of another configuration of the switch unit included in the semiconductor device according to the embodiment of the present invention. The difference from FIG. 1 is that a flip-flop circuit is inserted instead of the capacitor C1 between the node N2 on the MOS transistor M1 side and the node N3 on the MOS transistor M3 side. By this circuit, a signal appearing at the node N2 can be held, and an inverted signal of this N2 appears at N3, whereby the MOS transistor M3 can be controlled.

  Whether or not to electrically connect D1 and D2 can be selected according to the state of the MOS transistor M3 serving as a switch. As will be described later, this function can be combined to form a unit whose logic function is variable. If necessary, a switch may be provided between N3 and the MOS transistor M3, and this may be controlled to give the state of the flip-flop to the MOS transistor M3 only when desired.

  FIG. 3 is a waveform diagram showing an example of the operation in the switch unit of FIG. That is, an example of a control operation of a switch using a phase change element, which is necessary when switching logic functions, is shown. Corresponding to the state of phase change element PC1, there are a state where the electrical resistance is high and a state where it is low between node N1 and control line SL shown in FIG. When the resistance is high, the phase change element PC1 is in an amorphous state. This state is called a reset state, and an operation for changing to this state is called a reset operation. The state where the resistance is low is that the PC 1 is in a polycrystal state, and this state is called the Set state, and the operation for changing to this state is called the Set operation. These operations are performed as follows.

  As shown in FIG. 3, first, in the reset operation, for example, the control line DL is set to 2V. SL is 0V. That is, the voltage difference between DL and SL is 2 V, and there is a MOS transistor M2 and a phase change element PC1 connected in series between them. In this state, the control line RW which is also the gate of the MOS transistor M2 is set to 3V. As a result, current flows through MOS transistor M2 and current also flows through phase change element PC1, and the phase change element is melted by the heat generated at that time. At this time, the voltage of N2 becomes V1 depending on the resistance value of the MOS transistor M2 and the phase change element PC1.

  Thereafter, the RW is lowered, the supply of current, that is, the supply of heat is stopped, and rapid cooling is performed in a short time t1. Then, phase change element PC1 changes to an amorphous state and enters a high resistance state. Thereafter, the control line DL is returned to 0V. At this time, the node N2 remains at V1. For this reason, at the end of the Reset operation, RW is raised again and this voltage is set to 0V.

  Next, in the Set operation, the control line DL is set to 2V and SL is set to 0V. Here, the control line RW, which is also the gate of the MOS transistor M2, is set to 2V. In this way, a current flows through M2, but since RW is as low as 2V, the current is not as large as that at the time of the reset operation, and thus heat generation is also small. This state is maintained for a time t2. While being held, crystallization is performed in the phase change element PC1. At this time, the voltage of N2 becomes V2 depending on the resistance value of the MOS transistor M2 and the phase change element PC1. When crystallization is completed, the control line RW and the control line DL are lowered. By this operation, phase change element PC1 enters a poly-crystallized state, and the resistance is lowered. Therefore, a state that is electrically different from the previous Reset state can be realized. Note that the terminal N2 remains at V2. For this reason, at the end of the Set operation, RW is raised again to keep this voltage at 0V.

  The above is the Reset operation and the Set operation, which are necessary states, and this operation is performed according to the corresponding information. Depending on how the operation is performed, the Set operation may be performed after the Reset operation is performed in advance even if the Set state is necessary, for example, for the purpose of improving reliability.

  During normal operation (normal), the control line DL is set to 1V. SL is 0V. Here, 2V is applied to the control line RW. As a result, the voltage V3 corresponding to the resistance ratio between the resistance of the phase change element PC1 corresponding to the Reset state by the Reset operation or the Set state by the Set operation and the MOS transistor M2 is generated at N1. Here, the voltage V3 is a high potential in the Reset state and a low potential (approximately 0 V) in the Set state. The voltage V3 appears at the node N2 which is one end of the capacitor C1 and the gate of the MOS transistor M3 via the MOS transistor M1. Therefore, in the Reset state, the MOS transistor M3 serving as a switch is turned on, and in the Set state, M3 is turned off.

  Since the capacitor C1 generally has a leakage current, this potential changes. Therefore, an operation (so-called refresh operation) for restoring the signal voltage of the capacitor C1 by setting a voltage on the control line DL at regular time intervals and starting up the control line RW is necessary. The example of FIG. 3 shows an example in which the voltage of V3 decreases toward 0V.

  Further, regarding the operation of the circuit of FIG. 2, the Reset operation and the Set operation are the same as the operation of the circuit of FIG. The difference from the operation of the circuit of FIG. 1 is that there is a flip-flop, so that a refresh operation is not required during normal operation (normal).

  FIG. 4 is a circuit diagram showing still another configuration example of the switch unit included in the semiconductor device according to the embodiment of the present invention. Here, unlike the configuration of FIGS. 1 and 2, the node N1 is directly connected to the gate of the MOS transistor M3. According to this method, normal operation is performed in a state where desired voltages are set in the control line DL and the control line RW. When this configuration is used, the area can be further reduced as compared with the configurations of FIGS. 1 and 2.

  As described above, by using the configuration shown in FIGS. 1, 2, and 4, a switch unit capable of high-speed operation with a small area can be realized. Furthermore, since a phase change element is used, low voltage operation (low power consumption operation) can be realized.

  FIG. 5 is an explanatory diagram showing an outline of a cross-sectional configuration example of the semiconductor device according to the embodiment of the present invention. In general, in a semiconductor element, a relatively high voltage is applied from the outside in an IO circuit or the like, and a lower voltage is applied in a decoder circuit or another logic circuit, for example. In this configuration example, a MOS transistor having a thick oxide insulating film is used for a portion to which a relatively high voltage is applied. This is transistor regions MP_IO and MN_IO, and these oxide insulating film portions are SIO4 and SIO3, respectively. A MOS transistor having a thin oxide insulating film is used for a portion to which a low voltage is applied. This is transistor regions MP_CORE and MN_CORE, and these oxide insulating film portions are SIO2 and SIO1, respectively.

  Further, the MOS transistor M2 and the like described above in FIG. 1 and the like are formed in the transistor region MN_MEM, and the oxide insulating film portion is SIO0. If the SIO0 has the same film thickness as the SIO1, a smaller cell area can be easily realized, and if it has the same film thickness as the SIO3, the voltage range that can be handled can be widened. In this figure, the phase change element PC has one side in contact with the contact layer CNT, the metal first layer ML1, and the other contact layer CNT from one side of the source / drain region (n +) of the MN_MEM, and the metal second layer ML2 is multifaceted. Is in contact with the two layers. The other of the source / drain regions (n +) of MN_MEM is connected to the metal third layer ML3.

  In this figure, each transistor is isolated by an element isolation insulating film FI, and each gate is made of a polysilicon film (Poly-Si). Although not shown in this figure, silicide or salicide (silicide in self-alignment) may be used to lower the resistance of the source / drain region or the gate and source / drain region.

  FIG. 6 is a diagram illustrating the correspondence between the switch unit and the switch used in the variable logic unit according to the embodiment of the present invention. FIG. 6A shows a signal line CN, a signal line RN that is orthogonal to the signal line CN, and a switch SW that connects these signal lines. Such a connection form is often used in a variable logic unit or the like. This switch SW can be realized by the circuit shown in the above description.

  That is, as shown in FIG. 6B, the circuit shown as the switch unit RC1 in FIGS. 1 to 4 corresponds to the switch SW, and the signal line D1 and the signal line D2 of the MOS transistor M3 in RC1 are connected to this signal. It may be connected to the line CN and the signal line RN. In the following description, the switch SW is a circuit using the RC1 as an example, and will be referred to as a “phase change switch”. The state in which the switch is closed is a state in which D1 and D2 are electrically connected, and the state in which the switch is open is an electrically non-conductive state. These two states are phase change elements. What can be realized by this state is as described in FIGS.

  FIG. 7 is a diagram showing a configuration example of a phase change switch array including the phase change switch of FIG. 6, and (a) and (b) show different description methods for the phase change switch array. In the phase change switch array SW_ARY shown in FIG. 7A, the phase change switches SW of FIG. 6 are arranged in an array and include a plurality of phase change switches SW11 to SWmn. For example, SW11 is a switch capable of selectively connecting and separating the vertical signal line CN1 and the horizontal signal line RN1, and SWmn selectively connects and separates the vertical signal line CNn and the horizontal signal line RNm. It is a possible switch. Such a phase change switch array SW_ARY may be shown as shown in FIG. As shown in this figure, any CN1 to CNn and any RN1 to RNm can be connected by a configuration in which phase change switches SW are arranged in n columns CN1 to CNn and m rows RN1 to RNm.

  FIG. 8 is a diagram illustrating a configuration example of a circuit unit having a variable function included in the semiconductor device according to the embodiment of the present invention. In FIG. 8, an AND / OR circuit is illustrated as an example of a circuit unit RCP1 having a variable function or a variable logic unit. That is, the circuit unit RCP1 has an AND surface AND_ARY for performing an AND operation and an OR surface OR_ARY for performing an OR operation, and includes a phase change switch array SW_ARY in each of them. Yes.

  In general logic operations, an AND operation is performed by combining desired signals, and a desired result can be derived by performing an OR operation by combining these AND operation results. Therefore, if a circuit as shown in the example of FIG. 8 is prepared, this combination can be realized.

  That is, in the example of this figure, with respect to the input signals A, B, C, and D, it is selected which signal the AND operation is performed by the phase change switch array SW_ARY inside the AND_ARY. Then, a plurality of AND operations are performed according to the combination of selections, and signals corresponding to the respective AND operation results are input to OR_ARY. Similarly, in OR_ARY, it is possible to select which signal to perform the OR operation from among signals corresponding to a plurality of AND operation results by using phase change switch array SW_ARY. Therefore, the output signals F1 to F4 that are the result of the OR operation are the results of performing a desired product-sum operation on the input signals A, B, C, and D. In this way, by operating the phase change switch SW using the phase change element, the circuit unit RCP1 can be reconfigured to a device that performs a desired logical operation, and a variable function logical operation circuit can be realized.

  FIG. 9 is a diagram showing another configuration example of the circuit unit having variable functions included in the semiconductor device according to the embodiment of the present invention. The variable function circuit unit RCP2 shown in FIG. 9 shows a system in which a plurality of circuit blocks CA11 to CA34 are arranged in a matrix, and each circuit block is connected only to adjacent circuit blocks. For example, CA22 is connected only to CA12, CA21, CA23, and CA32. In such a system, by providing the phase change switch SW in each circuit block CA and changing the function, an LSI capable of realizing many functions at high speed can be produced. In the following, CA11 to CA34 in FIG. 9 are represented as CAij, and how this circuit block CAij is configured will be described, for example.

  FIG. 10 is a diagram showing a detailed configuration example of each circuit block CAij included in the circuit block of FIG. The CAij in FIG. 10 exchanges signals between, for example, a lookup table LUT that stores a list of functions, a flip-flop FF that holds temporary instructions, an arithmetic circuit MUX that performs arithmetic operations according to these, and four-way signals. The connection area CNCT_AREA to be controlled is configured. A phase change memory and a phase change switch SW can be used for these LUTs and FFs. With such a configuration, it is possible to perform a logic operation whose function is variable in the circuit block CAij performing the operation.

  FIG. 11 is a diagram showing another detailed configuration example of each circuit block CAij included in the circuit unit of FIG. The CAij in FIG. 11 communicates with the circuit block PRO in charge of signal processing and other circuit blocks CAij, and exchanges data with other blocks and monitors their progress when, for example, one work is divided. And a circuit block AUR that performs such control. Here, a phase change switch SW is provided in these PRO and AUR so that the function can be changed. Each PRO and AUR is connected to PRO and AUR in the other four adjacent circuit blocks, respectively. PRO is a circuit block that mainly performs signal processing. Here, AUR will be described in more detail below.

  FIG. 12 is a diagram showing a detailed configuration example of the circuit block AUR included in the circuit block CAij of FIG. The AUR in FIG. 12 has four types of inputs and outputs in order to connect the other four adjacent circuit blocks. In this figure, this input signal is indicated by IN, IE, IS, and IW, and the output signal is indicated by ON, OE, OS, and OW. The internal structure of this AUR is composed of circuit blocks MB4, MB1, MB2 and MB3 that output output signals ON, OE, OS, and OW, and input signals IN, IE, IS, and IW are input to the respective circuit blocks. . That is, each output signal is generated by computation from all input signals. For example, the output signal OS is generated by calculating four input signals IN, IE, IS, and IW by the circuit block MB2. By adopting such a symmetric structure, a calculation with a high degree of freedom can be performed.

  Next, an example of the configuration of the circuit blocks MB1, MB2, MB3, and MB4 in FIG. FIG. 13 is a diagram showing a detailed configuration example of the circuit block MBi included in the circuit block AUR of FIG. The MBi in FIG. 13 includes, for example, logic cells L1 to L4 and phase change switch cells indicated by S1 to S5. Each of S1 to S5 has a function of connecting, for example, one of the inputs to S1 to the output by a plurality of phase change switches SW included therein.

  Further, input signals IN and IE are input to the logic cell L1, input signals IS and IW are input to the logic cell L3, and outputs of L1 and L3 are output to L2 and L2 by the phase change switch cells S1 to S4. The output of L2 and L4 is further selectively connected to the output signal O by the phase change switch cell S5. O represents one of the output signals ON, OE, OS, and OW shown in FIG. In this way, the output signal O can be generated from the input signals IN, IE, IS, and IW by a circuit whose function can be changed using the phase change switch.

  Next, an example of the configuration of each of the logic cells L1 to L4 in FIG. FIG. 14 is a diagram showing a detailed configuration example of the logic cell Li included in the circuit block MBi of FIG. The logic cell Li in FIG. 14 is, for example, a circuit example that can switch between AND (NAND), OR (NOR), and NOT of two input signals I1 and I2. This switching is performed by the phase change switch SW.

  By the way, the AUR can be more generally configured using AND and OR planes. FIG. 15 is a diagram showing another detailed configuration example of the circuit block AUR included in the circuit block CAij of FIG. In FIG. 15, for four types of input signals and output signals, the input signals are indicated by A, B, C, and D, and the output signals are indicated by F1, F2, F3, and F4. These four input signals are input to the AND / OR plane including the phase change switch array SW_ARY as described with reference to FIG. 8, and the calculation results are output as output signals F1, F2, F3, and F4. As described above, by realizing a function of performing a desired calculation from the input signals A, B, C, and D using the phase change switch, it is possible to realize a desired AUR function.

  The configuration example of the system in which the circuit blocks are arranged in a matrix and each circuit block is connected only to the adjacent circuit block has been described above. Since this system can be configured by connecting each circuit block only to adjacent circuit blocks, a very large system can be easily configured. In addition, the function change in this system is performed by a program or an external command as described later, by external information itself, or by an internally generated program / command based on the difference between this and desired output information. be able to.

  FIG. 16 is a diagram showing still another configuration example of the circuit unit having a variable function included in the semiconductor device according to the embodiment of the present invention. In the circuit unit RCP3 of FIG. 16, A1 is a circuit block whose function can be changed by a phase change switch, and is the one shown in FIGS. 8, 10, and 11 or a combination thereof. Among these, the control circuit for controlling the phase change switch is CTR, the input / output circuit in the calculation at A1 is INF, MEM is a memory, and PRC is a processor that integrates the whole while performing its own calculation. Yes, the external input / output bus is IO. The memory MEM may be connected to the INF in this way and used in common with each A1. Alternatively, the memory MEM may be distributed and arranged inside each A1. As described above, by using the configuration example of FIG. 16, the connection method of A1 and each function can be changed according to the data and command from the IO.

  FIG. 17 is a diagram illustrating an example of a configuration in which the circuit unit in FIG. 16 is modified. The difference between the circuit unit RCP4 shown in FIG. 17 and the circuit unit RCP3 shown in FIG. 16 is that the circuit blocks constituting the matrix may have different circuit configurations, and the switching of the circuit function indicated as SHFL. This is the addition of an internal control circuit. First, since each circuit block has a different circuit configuration, each of A11 to Aij shown in this figure is a circuit block having a different circuit configuration, and each of these functions and a method of connection between them. Is controlled by CTR. The means for switching between these is performed using a phase change switch. As a result, the respective functions can be switched and these connection methods can be switched, so that the functions can be switched at a higher level.

  Next, the function of SHFL will be described. FIG. 18 is a diagram for explaining an example of the function of the circuit block SHFL included in the circuit unit of FIG. In this figure, the time change of the data processing amount in one of the circuit blocks A22, Aab, Axy included in FIG. 17 is schematically shown. In this example, only A22 has a large data processing amount between t1 and t2 of time, but other Aab and Axy have a small processing amount as compared with this. That is, the processing is concentrated on the circuit block A22. At this time, in A22, the power consumption is large, the heat generation is also large, and the processable amount may be exceeded. If this state continues, the overall processing efficiency decreases. On the other hand, once entering such a state, this state often continues. In order to avoid this, a control circuit SHFL is provided.

  This SHFL monitors the activity of each circuit block from the current amount and data amount of each circuit block. For example, when an excessive amount of processing is applied to the circuit block A22, the functions are reorganized again. This may be realized by simply passing half of the processing to another circuit block and adding a function for integrating them to another circuit block or the circuit block in question. By performing this, the processing amount is distributed after t2 in the example of FIG.

  FIG. 19 is a schematic diagram showing an example of the configuration of a circuit unit when a phase change switch is applied to an FPGA in a semiconductor device according to an embodiment of the present invention. The circuit unit RCP5 shown in FIG. 19 has a configuration assuming an FPGA unit, and has a configuration in which a plurality of logic cells L11 to L33, connection cells C11 to 52, and switch cells S11 to S22 are arranged in a matrix. ing. Each of the logic cells L11 to L33, the connection cells C11 to 52, and the switch cells S11 to S22 is provided with the phase change switch SW as described above, and a desired function can be set according to these states. It has become.

  For example, the logic cells L11 to L33 can be changed to desired functions by setting logic functions such as NOR and NAND by the phase change switch SW. In the connection cells C11 to 52, the connection relationship between the corresponding logic cells L11 to L33 and the wiring can be changed by setting the phase change switch SW. In the switch cells S11 to S22, the connection between the wirings can be changed by setting the phase change switch SW. In the prior art, these can be changed by a switch composed of a non-volatile memory and a MOS transistor circuit, but there is a drawback that low voltage operation is not possible. However, by using a phase change switch, it is possible to perform a low voltage operation.

  20 is a schematic diagram showing an example of the configuration of a circuit unit different from that in FIG. 19 in the semiconductor device according to the embodiment of the present invention. The circuit unit RCP6 includes logic cells L11 to L22 and a mutual connection block CB. Each of the logic cells L11 to L22 and the mutual connection block CB is provided with a phase change switch SW, and a desired function can be set according to these states. In the logic cells L11 to L22, for example, logic functions such as registers and arithmetic units are set. In the interconnection block CB, the interconnection of the functional circuits set in the logic cells L11 to L22 can be switched. This configuration generally corresponds to a configuration called CPLD (Compliant Programmable Logic Device). Since the wiring is concentrated around the switchable interconnection block CB, there is an advantage that the wiring delay is small and almost constant.

  FIG. 21 is a block diagram showing an example of the configuration of the semiconductor device according to one embodiment of the present invention. The semiconductor device shown in FIG. 21 includes, for example, a circuit unit RCP (an FPGA using a phase change switch or a circuit unit using another variable logic) using a phase change switch as described above. . The semiconductor device shown in the figure is not particularly limited, but is formed on a single semiconductor substrate (semiconductor chip) such as single crystal silicon by a CMOS integrated circuit manufacturing technique. This semiconductor device includes, for example, a microcomputer unit MC, an RCP as a circuit unit whose function can be switched by the phase change switch described so far, an input / output circuit IO, a peripheral circuit unit PERI, and a peripheral bus P bus (P_BUS). Have.

  The microcomputer unit MC includes a CPU (Central Processing Unit), a phase change memory PCM as a nonvolatile memory unit, and a RAM (Random Access Memory) as a volatile memory unit, and is commonly connected to an internal bus (I_BUS). The peripheral circuit unit PERI is connected to P_BUS, and IO is connected to P_BUS and I_BUS. The IO serves as an interface between an external bus (not shown) and an external peripheral circuit. RCP is connected to I_BUS and IO. The other peripheral circuit unit PERI includes a timer, a counter, and the like, although not particularly limited.

  According to this, a phase change memory PCM as a non-volatile memory for storing a processing program by the CPU, a normal programmable microcomputer by the CPU, and a high-speed FPGA using the phase change switch can be formed on the same chip. Speed and freedom can be greatly improved. Furthermore, since there is no circuit that requires a high voltage such as a flash memory in the chip, a chip that can operate at a low voltage can be realized.

  FIG. 22 is a block diagram showing an example of the detailed configuration of the semiconductor device of FIG. In FIG. 22, a user debug interface UDI is an input / output circuit for a user to perform debugging, and is connected to a debugging system (not shown). The user break controller UBC is a controller that performs breakpoint control during system debugging. The DE-RAM is a RAM used as an emulation memory or the like during debugging. They are connected to the I bus (I_BUS) along with the CPU, phase change memory PCM and RAM. The interrupt controller INTC performs interrupt control to the CPU. The direct memory access controller DMAC performs memory access control on behalf of the CPU.

  The circuit unit RCP having a variable logic function including the phase change switch SW is connected to I_BUS. D / A and A / D are a conversion circuit from a digital signal to an analog signal and a conversion circuit from an analog signal to a digital signal, respectively. The SCI is a serial interface circuit that constitutes one of the input / output circuits. The external bus interface (EX_Bus_I / F) is an input / output circuit that interfaces with an external bus, and is connected to I_BUS via a bus state controller BUS_CL. BUS_CL is connected to the P bus (P_BUS) via the peripheral bus controller PBUS_CL. The clock pulse generator CPG includes a PLL synthesizer and the like, and generates an internal reference clock signal. The watchdog timer WDT monitors the runaway of the CPU.

  FIG. 23 is a block diagram showing an example of a configuration different from FIG. 21 in the semiconductor device according to the embodiment of the present invention. In the semiconductor device shown in the figure, a write permission circuit WRIT_CL for the circuit unit RCP is added to the configuration of FIG. This is because the permission to change the function by this RCP is given from the outside. Since it is possible to determine whether or not to change the function by this circuit, it is possible to protect a specific function that has already been created using the phase change switch SW, or to indicate that this write permission circuit WRIT_CL has been operated. It is possible to detect that RCP has been used. This is used for information such as billing.

  WRIT_CL deals with this, for example, by providing a user release area (USER_AREA), a user non-release area (Security_AREA), a key data storage area (KEY_AREA), etc. in the phase change memory PCM. There are two types of passwords that allow a change to the phase change switch SW in the RCP when a specific password is input through the network, etc., and a function that allows different writing areas or ranges. Further, it may be a function that allows the user to access only the writable part without providing a password. As a password or key, a command may be input, or the vendor side is allowed only when a specific signal is given to a specific terminal, or after the chip is sealed in the package The structure may be such that the user cannot touch this specific terminal.

  FIG. 24 is a block diagram showing an example of a configuration further different from FIG. 21 and the like in the semiconductor device according to the embodiment of the present invention. FIG. 24 shows an example in which a high frequency block (RF) is used for the program of the circuit unit RCP and the phase change memory PCM. RF performs setting or program change for RCP or PCM through a wireless network or another network connected to the wireless network, using a high frequency such as 2.4 GHz band. This is convenient for adding a new function or correcting a bug after the semiconductor device is shipped or mounted on a circuit board. Further, a write permission circuit WRIT_CL as described in FIG. 23 may be provided in order to give a change permission in the wireless network or to notify that there has been a change.

  25A and 25B are diagrams showing an example of the outer shape of a semiconductor device according to an embodiment of the present invention, where FIG. 25A is a cross-sectional view and FIG. 25B is a plan view. FIG. 25 shows an example in which a semiconductor device is configured by MCM (multi-chip module). That is, the semiconductor device of FIG. 25 includes, for example, a CPU chip (CPU_CHIP) that can be switched in function by including a phase change switch, a variable-function RCP chip (RCP_CHIP) that includes a phase change switch, and a phase change switch. The provided RF chip (RF_CHIP), memory chip (DRAM_CHIP), and the like are mounted on a high-density mounting substrate. According to this, the function that the user wants to realize can be realized in a shorter period than in the case of high performance and single chip.

  26A and 26B are diagrams showing another example of the outer shape of a semiconductor device according to an embodiment of the present invention, where FIG. 26A is a cross-sectional view and FIG. 26B is a plan view. FIG. 26 shows an example in which a semiconductor device is configured by MCP (multi-chip package). That is, in the semiconductor device of FIG. 26, for example, a CPU chip (CPU_CHIP) capable of switching functions with a phase change switch and a variable function RCP chip (RCP_CHIP) with a phase change switch are mounted in a stack. Has been. Thus, a system with a short trial period and low power can be configured.

  FIG. 27 is a block diagram showing an example of a configuration further different from FIG. 21 and the like in the semiconductor device according to the embodiment of the present invention. The semiconductor device shown in FIG. 27 has a configuration referred to as an SOC (system on chip) type system LSI. The configuration includes, for example, an RCP + CPU unit using a phase change memory and a phase change switch, a memory part (Memory) using SRAM or DRAM, an encryption processing accelerator block (Encryption), a modem function block (Modulator), JAVA (registered trademark) accelerator block (Java (registered trademark)), audio / video CODEC processing accelerator block (AVCODEC), sensor block (SENSOR), high frequency block (RF), and input / output interface Block (I / O) and the like are included.

  In the RCP + CPU unit using the phase change memory and the phase change switch, both software processing by the CPU and hardware processing by the RCP can be set in a programmable manner, and this configuration is realized on one semiconductor substrate. Therefore, it is possible to easily cope with future high-speed multimedia processing.

  FIG. 28 is a block diagram showing an example of a configuration further different from FIG. 21 and the like in the semiconductor device according to the embodiment of the present invention. The semiconductor device shown in FIG. 28 is a portable device system such as a cellular phone. The configuration includes, for example, antenna ATN, power amplifier PA, high frequency block RF, processor PRC, A / D converter and D / A converter, microphone and speaker SPKR, liquid crystal display LCD, LCD driver (LCD_DRV), ROM, RAM , An IC card interface (IC_CARD_IF), a flash memory card interface (FLASH_CARD_IF), and the like. The processor PRC is configured by a CPU using a phase change memory and a phase change switch and the RCP described above. Accordingly, both software processing by the CPU and hardware processing by the RCP can be set in a programmable manner, so that it is possible to quickly respond to market changes, standard changes, and service changes.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in FIGS. 1 to 4, the configuration of the switch unit including the phase change element and the operation thereof are illustrated, but the configuration can be variously modified depending on the application. One example will be described below.

  FIG. 29 is a circuit diagram showing an example of a configuration obtained by modifying the switch unit of FIG. In the switch section RC1 shown in FIG. 29, unlike the configuration of FIG. 2, different control lines RW and PRW are connected to the gates of the MOS transistors M1 and M2, respectively. When the configuration of FIG. 2 described above is used, the number of signals can be reduced by connecting the common control line RW to the gates of the MOS transistors M1 and M2. On the other hand, when different control lines RW and PRW are connected as shown in FIG. 29, the number of signals increases, but it is possible to increase the speed when changing the function of a circuit unit (circuit block), for example.

  That is, particularly in an LSI that performs a desired operation while sequentially changing the function of the circuit unit as described with reference to FIG. 17 and the like, the state of the next phase change switch is previously set in the background as shown in FIG. It becomes possible to set. FIG. 30 is a waveform diagram showing an example of the operation in the switch unit of FIG.

  In FIG. 30, first, the control line PRW is driven to perform, for example, a reset operation (Reset) on the phase change element PC1, and then the control line PRW and the control line RW are driven, so that the flip-flop Data is set (Normal (1)). While the MOS transistor M3 is driven with this setting data (here, M3 is OFF) (during Normal (1)), writing corresponding to the next setting data (here, set operation (Set)) Is previously performed on the phase change element. Thereafter, by driving the control line PRW and the control line RW at a desired time, the next setting data is set in the flip-flop (Normal (2)), and the MOS transistor M3 is driven by this setting data (M3 is here) ON).

  As described above, by rewriting the phase change element PC1 in the background, it is possible to speed up the switching of the phase change switch. In addition, since rewriting in the background can be performed at a low voltage, noise generated in the switch unit or other circuits is not particularly problematic and can be easily rewritten.

  FIG. 31 is a circuit diagram showing an example of a configuration obtained by modifying the switch unit of FIG. 1, and FIG. 32 is a circuit diagram showing an example of a configuration obtained by further modifying the switch unit of FIG. Unlike the configurations of FIGS. 1 and 2, these switch units RC <b> 1 have a configuration including two phase change elements.

  That is, in switch unit RC1 shown in FIG. 31, MOS transistor M21 and phase change element PC11 are connected in series between control line DL and control line SL, and node N11 at the connection point of M21 and PC11 is the source of MOS transistor M11. / Connected to one of the drains. Further, similarly, the MOS transistor M22 and the phase change element PC12 are connected in series between the control line DL and the control line SL, and the node N12 at the connection point of M22 and PC12 is one of the source / drain of the MOS transistor M12. It is connected to the.

  The other of the source / drain of these MOS transistors M11 and M12 is connected in common to the node N2, and the capacitor N1 and the gate of the MOS transistor M3 are connected to this node N2. Note that the gates of the MOS transistors M11 and M12 are connected to the control lines RW1 and RW2, respectively, and the gates of the MOS transistors M21 and M22 are connected to the control lines PRW1 and PRW2, respectively. Further, the configuration of FIG. 32 is a configuration in which the capacitor C1 of FIG. 31 is replaced with a flip-flop.

  When such a configuration is used, for example, similarly to the operation described in FIG. 30, one of the phase change elements PC11 and PC12 is rewritten in the background, and the MOS transistor M3 serving as a switch is driven while switching between them. It becomes possible. Furthermore, for example, when the power is turned off, both the current setting data and the next setting data can be stored, and the two phase change elements can be used while being rewritten alternately. It is also possible to extend the rewriting life of the change element.

  FIG. 33 is a waveform diagram showing an example of the operation in the switch section of FIG. 31, and FIG. 34 is a waveform diagram showing an example of the operation following FIG. In FIGS. 33 and 34, for example, a reset operation or a set operation is performed on the phase change element PC11, and data corresponding to the state of the phase change element PC11 is set in the capacitor C1 (Normal (1)). Then, the reset operation or the set operation of the phase change element PC12 is performed while the MOS transistor M3 is being driven with the setting data (during Normal (1)). Thereafter, at a desired time, the data of the capacitor C1 is switched to data corresponding to the phase change element PC12 (Normal (2)), and the MOS transistor M3 is driven with the set data. Further, during normal (2), a reset operation or a set operation is performed on the phase change element PC11.

  FIG. 35 is a circuit diagram illustrating an example of a configuration obtained by modifying the switch unit of FIG. In the switch unit RC1 shown in FIG. 35, the control line DL is separated into the control line DL1 and the control line DL2 and the control lines DL1 and DL2 are associated with the MOS transistors M21 and M22, respectively, in the configuration of FIG. It has a configuration. With this configuration, for example, the operation of setting the data of the phase change element PC11 in the flip-flop and the operation of writing the data to the phase change element PC12 can be performed in the same time zone. It is possible to further speed up the switching cycle.

  The semiconductor device of the present invention is particularly useful when applied to a system LSI or microcomputer of a system-on-chip type in which the connection and function of a circuit are changed using a switch using a phase change memory. The present invention is not limited to this, and can be applied to all LSIs whose functions such as FPGA can be changed.

1 is a circuit diagram illustrating an example of a configuration of a switch unit included in a semiconductor device according to an embodiment of the present invention. FIG. In the semiconductor device by one embodiment of this invention, it is a circuit diagram which shows an example of the other structure of the switch part contained in it. It is a wave form diagram which shows an example of the operation | movement in the switch part of FIG. FIG. 11 is a circuit diagram showing still another configuration example of a switch unit included in a semiconductor device according to an embodiment of the present invention. In the semiconductor device by one embodiment of this invention, it is explanatory drawing which shows the outline of the cross-sectional structural example. It is a figure explaining the correspondence between the switch part by one embodiment of this invention, and the switch used by a variable logic unit etc. FIG. It is a figure which shows the structural example of the phase change switch array containing the phase change switch of FIG. 6, (a), (b) shows the different description method of a phase change switch array, respectively. 1 is a diagram illustrating a configuration example of a circuit unit having a variable function included in a semiconductor device according to an embodiment of the present invention; In the semiconductor device by one embodiment of this invention, it is a figure which shows the other structural example of the circuit unit in which the function contained in it is variable. FIG. 10 is a diagram illustrating a detailed configuration example of each circuit block CAij included in the circuit unit of FIG. 9. FIG. 10 is a diagram illustrating another detailed configuration example of each circuit block CAij included in the circuit unit of FIG. 9. FIG. 12 is a diagram illustrating a detailed configuration example of a circuit block AUR included in the circuit block CAij of FIG. 11. FIG. 13 is a diagram illustrating a detailed configuration example of a circuit block MBi included in the circuit block AUR of FIG. 12. FIG. 14 is a diagram illustrating a detailed configuration example of a logic cell Li included in the circuit block MBi of FIG. 13. FIG. 12 is a diagram illustrating another detailed configuration example of the circuit block AUR included in the circuit block CAij of FIG. 11. FIG. 11 is a diagram showing still another configuration example of a circuit unit having a variable function included in the semiconductor device according to the embodiment of the present invention. It is a figure which shows an example of the structure which deform | transformed the circuit unit of FIG. FIG. 18 is a diagram illustrating an example of functions of a circuit block SHFL included in the circuit unit of FIG. 17. In the semiconductor device by one embodiment of this invention, it is the schematic which shows an example of a structure of the circuit unit at the time of applying a phase change switch to FPGA. In the semiconductor device according to one embodiment of the present invention, FIG. 19 is a schematic diagram showing an example of the configuration of a circuit unit. 1 is a block diagram showing an example of the configuration of a semiconductor device according to an embodiment of the present invention. FIG. 22 is a block diagram showing an example of a detailed configuration of the semiconductor device of FIG. 21. FIG. 22 is a block diagram showing an example of a configuration different from that in FIG. 21 in the semiconductor device according to the embodiment of the present invention. FIG. 22 is a block diagram showing an example of a configuration further different from FIG. 21 and the like in the semiconductor device according to the embodiment of the present invention. 1A is a cross-sectional view of an example of the outer shape of a semiconductor device according to an embodiment of the present invention, and FIG. In the semiconductor device by one embodiment of this invention, it is a figure which shows another example of the external shape, (a) is sectional drawing, (b) is a top view. FIG. 22 is a block diagram showing an example of a configuration further different from FIG. 21 and the like in the semiconductor device according to the embodiment of the present invention. FIG. 22 is a block diagram showing an example of a configuration further different from FIG. 21 and the like in the semiconductor device according to the embodiment of the present invention. FIG. 3 is a circuit diagram illustrating an example of a configuration obtained by modifying the switch unit of FIG. 2. FIG. 30 is a waveform diagram illustrating an example of an operation in the switch unit of FIG. 29. It is a circuit diagram which shows an example of the structure which deform | transformed the switch part of FIG. FIG. 3 is a circuit diagram illustrating an example of a configuration obtained by further modifying the switch unit of FIG. 2. FIG. 32 is a waveform diagram illustrating an example of an operation in the switch unit in FIG. 31. FIG. 34 is a waveform diagram showing an example of an operation following FIG. FIG. 33 is a circuit diagram illustrating an example of a configuration obtained by modifying the switch unit of FIG. 32.

Explanation of symbols

D1, D2, CN, CN1-n, RN, RN1-m Signal lines DL, DL1, DL2, RW, RW1, RW2, SL, PRW, PRW1, PRW2 Control lines M1, M2, M3, M11, M12, M21, M22 MOS transistor C1 Capacitor PC1, PC11, PC12 Phase change element RC, RC1 Switch unit MP_IO, MN_IO IO transistor MP_CORE, MN_CORE Core transistor MN_MEM Memory cell transistor ML1, ML2, ML3 Metal layer SIO0-4 Oxide insulating film CNT Contact Layer n +, p + diffusion layer NWELL, PWELL well FI element isolation insulating film Poly-Si polysilicon film SW, SW11 to SWmn phase change switch SW_ARY phase change switch array AND_AR AND plane OR_ARY OR plane A, B, C, D, IS, IN, IW, IE, I1, I2 Input signal F1-F4, OS, ON, OW, OE, O, O1, O2 Output signal RCP, RCP1-6 Circuit units CA11 to 34, CAij, PRO, AUR, MB1 to 4, A1, A11 to Aij Circuit block CNCT_AREA Connection area LUT Look-up table FF Flip-flop MUX arithmetic circuit L1 to L4, L11 to L33, Li logic cells S1 to S5 Switch cells C11 to C52 Connection cells CTR, SHFL Control circuit INF, IO I / O circuit MEM memory PRC, CPU processor CB Interconnection block MC Microcomputer unit PCM Phase change memory RAM Volatile memory I_BUS, P_BUS bus PERI Peripheral circuit unit UDI U User debug interface UBC User break controller DE-RAM Debug RAM
INTC Interrupt controller DMAC Direct memory access controller D / A Digital-analog conversion circuit A / D Analog-digital conversion circuit SCI Serial interface circuit EX_Bus_I / F External bus interface BUS_CL Bus state controller PBUS_CL Peripheral bus controller CPG Clock pulse generator WDT Watchdog Timer WRIT_CL Write permission circuit RF High frequency block ATN Antenna PA Power amplifier SPKR Microphone and speaker LCD LCD display LCD_DRV LCD driver IC_CARD_IF IC card interface FLASH_CARD_IF Flash memory card interface

Claims (13)

A semiconductor device including a circuit unit having a variable logic function,
The circuit unit is
A phase change element;
A switch that can be turned on or off in response to the state of electrical resistance of the phase change element,
A semiconductor device, wherein a logic function of the circuit unit is set based on an ON state or an OFF state of the switch. The semiconductor device according to claim 1,
The circuit unit is composed of a plurality of circuit blocks each having a variable logic function,
A logic function of the circuit unit is set by setting a connection relation between the plurality of circuit blocks using the switch. The semiconductor device according to claim 1,
The circuit unit is
An AND operation unit that sets a combination of a plurality of input signals and outputs an AND operation result according to the setting;
An OR operation unit that sets a combination of the output AND operation results and outputs an OR operation result according to the setting;
The semiconductor device, wherein the switch is used to set the combination in the AND operation unit and the OR operation unit. 3. The semiconductor device according to claim 2, further comprising:
A function of monitoring the processing amount in each of the plurality of circuit blocks;
A semiconductor device comprising: a logic function of the plurality of circuit blocks and a function of reconstructing a connection relationship between the plurality of circuit units based on the monitored result. A processor;
A non-volatile memory unit configured with a memory cell including a phase change element and storing a processing program in the processor;
A semiconductor device including a circuit unit having a variable logic function,
The circuit unit is
A phase change element;
A switch that can be turned on or off in response to the state of electrical resistance of the phase change element,
The logic function of the circuit unit can be changed according to the resistance state of the phase change element in the circuit unit. The semiconductor device according to claim 5.
The semiconductor device, wherein the processor, the nonvolatile memory unit, and the circuit unit are provided on one semiconductor chip. The semiconductor device according to claim 5.
The processor, the nonvolatile memory unit and the circuit unit are formed on different semiconductor chips, respectively.
The semiconductor device, wherein the plurality of semiconductor chips are stored in one package. A first control line and a second control line;
A first transistor whose on state or off state is controlled by the voltage of the control node;
A second transistor and a first phase change element connected in series between the first control line and the second control line;
A third transistor provided between a connection node between the second transistor and the first phase change element and a control node of the first transistor;
A storage circuit for holding the voltage of the control node of the first transistor;
The state of the first phase change element is set using the first control line, the second control line, and the second transistor, and data corresponding to the state of the first phase change element is passed through the third transistor. And setting the memory circuit to cause the first transistor to function as a nonvolatile switch capable of setting and holding the state. The semiconductor device according to claim 8.
The semiconductor device, wherein the memory circuit is a capacitor. The semiconductor device according to claim 8.
The semiconductor device is a flip-flop. 9. The semiconductor device according to claim 8, further comprising:
A semiconductor device comprising: a third control line commonly connected to a control node of the second transistor and a control node of the third transistor. 9. The semiconductor device according to claim 8, further comprising:
A third control line connected to the control node of the second transistor;
A semiconductor device comprising: a fourth control line connected to a control node of the third transistor. 9. The semiconductor device according to claim 8, further comprising:
A fourth transistor and a second phase change element connected in series between the first control line and the second control line;
A semiconductor device comprising: a fifth transistor provided between a connection node between the fourth transistor and the second phase change element and a control node of the first transistor.

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