JP2010020860A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a memory circuit of which multifunctionality is achieved by a simple configuration. <P>SOLUTION: Each of a plurality of memory cells includes: first and second inverter circuits, to which the input and output cross-connected to first and second memory nodes are respectively connected; first and second switches MOSFET respectively prepared between the first/second memory nodes and first/second input/output terminals; and a third switch MOSFET prepared between the first memory node and a third memory node. In the first and second memory nodes, the write and read of a first memory information from the first and second input output terminals are attainable. In the third memory node, a power source voltage or grounding potential is regularly supplied corresponding to a second memory information. The memory information of the third memory node is conveyed to the first and second memory nodes by turning on the third switch MOSFET. The read from the first and second terminals is attained through the first and second switches MOSFET. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a technique that is effective when used in a semiconductor device having a ROM (Read Only Memory) and an SRAM (Static Random Access Memory).

Japanese Patent Laid-Open No. 5-128328 has a mask ROM and an SRAM, and among the data stored in the mask ROM, a part of the data related to the current reading is stored in a small-capacity SRAM having a high reading speed. It is disclosed that when data is transferred and data is read, the SRAM is activated and read out. Japanese Patent Application Laid-Open No. 2004-318330 discloses a semiconductor integrated circuit device having a CPU, a boot ROM, and an SRAM.
Japanese Patent Laid-Open No. 5-128328 JP 2004-318330 A

  The boot ROM as in Patent Document 2 reads stored information (program) only when the microcomputer is activated. That is, the boot ROM is not read when writing to or reading from the SRAM. Focusing on this, the inventors of the present application considered giving the SRAM a ROM function.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a novel memory circuit which has a simple structure and is multifunctional. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  One embodiment disclosed in the present application is as follows. Each of the plurality of memory cells includes a first and second inverter circuit having inputs and outputs connected to the first and second storage nodes, respectively, and the first and second storage nodes, first and second First and second switch MOSFETs provided between two input / output terminals, and a third switch MOSFET provided between the first storage node and the third storage node. The first and second storage nodes can write / read the first storage information from the first and second input / output terminals. The third storage node is constantly supplied with a power supply voltage or a ground potential corresponding to the second storage information. The storage information of the third storage node is transmitted to the first and second storage nodes by turning on the third switch MOSFET. Reading from the first and second terminals is enabled via the first and second switch MOSFETs.

  By providing the SRAM with a ROM function, a multi-function memory circuit can be realized with a simple configuration.

  FIG. 1 is a circuit diagram showing one embodiment of a memory cell according to the present invention. The input and output of the first CMOS inverter circuit composed of the P-channel MOSFET Q1 and the N-channel MOSFET Q2 and the second CMOS inverter circuit composed of the P-channel MOSFET Q3 and the N-channel MOSFET Q4 are cross-connected to constitute a latch circuit as a first storage unit. A pair of input / output nodes of the latch circuit are storage nodes MT and MB. An N-channel switch MOSFET Q5 is provided between one storage node MT and a first input / output terminal connected to the non-inverted (true) bit line BLT. An N-channel switch MOSFET Q6 is provided between the other storage node MB and the second input / output terminal connected to the inverted (bar) bit line BLB. The gates of the switch MOSFETs Q5 and Q6 are connected to the word line WL.

  In this embodiment, the same memory cell is provided with MOSFETs Q7 and Q8 and a connection part CN constituting the second memory part. An N-channel switch MOSFET Q7 is provided between the storage node MT and the connection portion CN. Although not particularly limited, one source and drain of a MOSFET Q8 similar to the switch MOSFET Q7 is connected to the other storage node MB as a dummy. The other source, drain and gate of the MOSFET Q8 are connected to receive the circuit ground potential VSS. Although the connection portion CN is not particularly limited, the connection portion CN is configured by a contact hole, and a contact provided between a wiring layer to which the power supply voltage VDD is applied to the connection portion or a wiring layer to which the circuit ground potential VSS is applied. It is fixedly connected to one of the stored information as a hole. The gate of the MOSFET Q7 is connected to the selection line RE. The first storage unit constitutes a storage unit for SRAM cells, and the second storage unit constitutes a ROM cell.

  FIG. 2 is an operation explanatory diagram of one embodiment of the memory cell of FIG. In step (1), power is supplied. In step (2), the selection line RE is temporarily set to the high level in conjunction with the power-on reset signal. As a result, the MOSFET Q7 is turned on, and the power supply voltage VDD (high level) or the ground potential VSS (low level) is supplied to the storage node MT. Thereby, for example, if the connection portion CN is connected to the power supply voltage VDD, in other words, if a high level is stored in the ROM cell, the first CMOS inverter circuit (Q1 and Q2) and the second CMOS inverter circuit ( In the latch circuit consisting of Q3 and Q4), the high level corresponding to the stored information is transmitted to the storage node MT corresponding to the ON state of the switch MOSFET Q7, and the storage node MB is set to the low level corresponding to this. By the step (2), the storage information of the second storage unit is transferred to the first storage unit.

  In step (3), the ROM is read. That is, by selecting the word line WL and selecting the bit lines BLT / BLB, the memory cell is selected, and the storage information of the first storage unit, that is, the storage information of the second storage information (ROM) is read. For example, when the memory cell is mounted on a microcomputer, a boot program is stored in the ROM, and the microcomputer is activated by reading (Boot) in step (3).

  In step (4), normal operation is performed. That is, data is written to and read from the memory cell. That is, the normal operation is to operate as an SRAM, and any data can be written and read by selecting the memory cell by selecting the word line WL and selecting the bit lines BLT / BLB.

  When it is necessary to read the information as ROM again from the normal operation, the process returns to step (2), a reset signal is generated, and a signal RE is generated in conjunction with this, and then read in step (3). That's fine. Step (5) is power shutdown.

  FIG. 3 shows an element layout diagram of one embodiment of the memory cell according to the present invention. A P-type well region PWEL1 in which N-channel MOSFETs (Q2, Q4, Q5, Q6) of the SRAM portion are formed across an N-type well region (NWEL) in which two P-channel MOSFETs (Q1, Q3) are formed; The N-channel MOSFETs (Q7, Q8) in the ROM portion are formed and distributed to the P-type well region PWEL2 where the N-channel MOSFETs (Q7, Q8) are formed.

  In the P-type well region PWEL1 and the N-type well region NWEL, the gates G are integrally formed in the P-channel MOSFET Q1 and the N-channel MOSFET Q2 constituting the first CMOS inverter circuit. Similarly, the gate G is integrally formed in the P-channel MOSFET Q3 and the N-channel MOSFET Q4 constituting the second CMOS inverter circuit. The two N-channel MOSFETs Q2 and Q4 are connected to the ground line VSS via a contact CN with a common diffusion layer constituting the source region. The drains of the N-channel MOSFETs Q2 and Q4 are connected to the drains of the P-channel MOSFETs Q1 and Q3 by the first wiring layer M1, and are cross-connected to the gate G of the other CMOS inverter circuit to form storage nodes MT and MB. The The diffusion layers constituting the source regions of the two P-channel MOSFETs Q1 and Q2 are shared and connected to the power supply voltage line VDD by the contact CN. The contact CN is a hole provided in an interlayer insulating film that separates upper and lower wirings and the like, and a conductive material such as a metal is embedded in the hole to connect the upper and lower layers.

  The N-channel MOSFET Q5 has a diffusion layer corresponding to the storage node MT of the MOSFET Q2 as one source / drain diffusion layer, and the other source / drain diffusion layer sandwiching the gate is a first wiring for connecting to the bit line BLT. Connected to layer M1. The N-channel MOSFET Q6 has a diffusion layer corresponding to the storage node MB of the MOSFET Q4 as one source / drain diffusion layer, and the other source / drain diffusion layer across the gate is connected to the bit line BLB. Connected to layer M1.

  In the P type well region PWEL2, N channel MOSFETs Q7 and Q8 are formed. In the MOSFET Q8 as a dummy, one diffusion layer is connected to the wiring layer M1 constituting the storage node MB, and the gate and the other of the diffusion layers are connected by the wiring layer M1 and supplied with the ground potential VSS. In the MOSFET Q7 for reading ROM, one diffusion layer is connected to the wiring layer M1 constituting the storage node MT. The other diffusion layer is connected to the first wiring layer M1. The gate is connected to the first wiring layer so as to be connected to the selection line RE.

  The second wiring layer M2 constitutes a power supply line VDD, a ground line VSS, and bit lines BLT and BLB, respectively. Although connection between these wirings and the inside of the memory cell is not shown in the drawing, the power line VDD is connected to the common source diffusion layer of the P-channel MOSFETs Q1 and Q3. The power supply voltage is supplied by being connected to the layer M1. The bit line BLT is connected to the first wiring layer M1 connected to the other source and drain of the MOSFET Q5. The bit line BLB is connected to the first wiring layer M1 connected to the other source and drain of the MOSFET Q6. The ground line VSS is connected to the first wiring layer M1 connected to the common source diffusion layer of the MOSFETs Q1 and Q3, and supplies the ground potential. Either one of the power supply lines VDD or VSS for the ROM is connected to the first wiring layer M1 connected to the other diffusion layer of the MOSFET Q7.

  The third wiring layer M3 constitutes a power supply line VDD, a ground line VSS, a word line WL, and a selection line RE, respectively. Although the connection between these wirings and the inside of the memory cell is not shown in the drawing, the ground line VSS is connected to a wiring layer M1 connected to the gate of the MOSFET Q8 and the other of the diffusion layers. . The power supply line VDD is connected to the first wiring layers M1 and M2 connected to the common source diffusion layer of the P-channel MOSFETs Q1 and Q3 and supplies a power supply voltage. The word line WL is connected to a first wiring layer M1 that commonly connects the gates of the MOSFETs Q5 and Q5. The selection line RE is connected to the first wiring M1 connected to the gate of the MOSFET Q7.

  FIG. 4 shows an overall circuit diagram of an embodiment of the memory circuit according to the present invention. This memory circuit basically has both the functions of RAM / ROM by incorporating ROM eyes into memory cells constituting a static RAM. This memory circuit includes a memory cell array composed of the memory cells as described above, an address selection circuit, a read circuit, a write circuit, and the like provided in the peripheral circuit.

  As a memory cell array, three word lines WL1 to WL3, three pairs of complementary bit lines BLT0, BLB0 to BLT2, and BLB2, and nine memory cells MC provided at the intersections are shown as representatives. Yes. The memory cell MC comprises MOSFETs Q1 to Q8 as shown in FIGS.

  Although not particularly limited, in an actual memory cell array, 256 memory cells are arranged on one word line WL. Therefore, the complementary bit lines BLT and BLB are composed of 256 pairs such as BLT0, BLB0 to BLT255, and BLB255. For example, 256 memory cells are arranged on the pair of bit lines BLT and BLB. Therefore, the word line is composed of 256 lines WL0 to 255. Each of the bit lines BLT and BLB is provided with a precharge & equalize circuit (not shown). This precharge circuit & equalize circuit includes, for example, a P channel MOSFET that applies a precharge voltage such as a power supply voltage to the complementary bit lines BLT and BLB and a P channel MOSFET that short-circuits between the complementary bit lines BLT and BLB. Composed. Further, a P-channel MOSFET in which the gate and the drain are cross-connected may be provided as a pull-up MOSFET between the complementary bit lines BLT and BLB and the power supply terminal. The pull-up MOSFET prevents the bit line on the high level side from dropping during reading.

  Although not particularly limited, the 256 pairs of bit lines are 64 pairs of complementary read data lines CB by P-channel MOSFETs Q20, Q21, Q22, Q23 and Q24, Q25, etc. that constitute a read column switch YS composed of P-channel MOSFETs. , / CB. One read data line CBT, CBB is connected to any one of four pairs of bit lines BL, / BL. The read data lines CBT and CBB are provided with a sense amplifier SA. The sense amplifier SA includes a CMOS latch circuit in which the inputs and outputs of two CMOS inverter circuits composed of P-channel MOSFETs Q28 and Q29 and N-channel MOSFETs Q26 and Q27 are cross-connected, and a source of the N-channel MOSFET of the CMOS latch circuit. The N channel MOSFET Q30 is provided at the circuit ground potential VSS. Corresponding to the 64 pairs of read data lines CBT and CBB being provided as described above, a total of 64 sense amplifiers SA are also provided.

  The sense amplifier selection signal sac formed by the timing generation circuit is supplied to the gate of the N-channel MOSFET Q30 that activates the sense amplifier SA. The sense amplifier SA is activated by the selection signal sac and amplifies the signals of the read data lines CBT and CBB. The amplified signal of the sense amplifier SA is transmitted to, for example, an output latch circuit, and an output signal is formed by the output circuit.

  In this embodiment, although not particularly limited, a read operation in which all the 64 sense amplifiers SA are activated to output a 64-bit read signal, and 32 of the 64 sense amplifiers SA are activated to 32. A read operation for outputting a read signal composed of bits or a read operation for activating 16 of the 64 sense amplifiers SA and outputting a read signal composed of 16 bits is selectively made possible. The sense amplifier selection signal sac controls the sense amplifier SA and the like corresponding to the three types of read operations.

  In this embodiment, a write amplifier WA is provided for each bit line pair BLT, BLB. These write amplifiers supply a write signal supplied to the write data line to the bit line pair BLT and BLB in response to the read operation as described above. As described above, since the write amplifier WA is provided without using the column switch YS, the selected one of the write amplifiers is activated and the 64-bit, 32-bit, 16-bit or the like as described above is activated. Writing is performed in units of data. Such a selection operation of the column switch YS and the sense amplifier SA and a selection operation of the write amplifier WA are performed by a signal from the control circuit CTRL.

  One of the 256 word lines WL is selected by a word driver WDR that receives a selection signal formed by a decoder circuit DEC. The decoder circuit DEC receives the timing signal and the address signal formed by the timing generation circuit, and forms the word line selection signal and the column selection signal. In the operation mode such as the standby operation, all the word lines are set to the non-selected level regardless of the address signal. The column selection signal formed by the decoder circuit performs a selection operation corresponding to the 32-bit operation, 16-bit operation, and 8-bit operation by a logic circuit included in the control circuit CTRL.

  Although not particularly limited, a selection driver for the selection line RE is provided in the word driver WDR unit for reading the ROM information of each memory cell MC. In these selection drivers, the signal re generated by the control circuit CTRL is commonly supplied via the drive circuit. As a result, the information stored in the ROM of all the memory cells MC is transferred to the latch circuit that constitutes the memory cell. Therefore, by reading the normal SRAM as described above, it is possible to take out the stored information stored in the eyes of the ROM. When data is written in the memory cell storing the ROM storage information, the ROM storage information is replaced with the write data.

  FIG. 5 shows an operation waveform diagram of the memory cell of the embodiment of FIGS. This waveform diagram is obtained by circuit simulation by a computer, and shows an example in which a read operation (Lead) and a write operation (Write) are performed on the memory cell provided with the ROM portion as described above.

  The read operation (Lead) is performed in synchronization with the clock CLK, the word line WL is selected by the address selection operation, and a potential difference corresponding to the storage node appears on the bit lines BLT / BLB. By the operation of selecting the word line WL, the low level of the storage node (memory node) of the memory cell temporarily rises, but returns to the original state by the latch operation. As the sense amplifier SA is activated, the common source potential of the sense amplifier becomes low level, and the amplification operation is started, and the sense line CBT / CBB connected to the selected bit line BLT / BLB is amplified to high level / low level. This amplified signal is output (Lead) as a signal signal.

  The write operation (Write) is performed in synchronization with the clock CLK in the same manner as described above, and the word line WL is selected by the address selection operation, and a potential difference corresponding to the storage node appears on the bit lines BLT / BLB. By the operation of selecting the word line WL, the low level of the storage node (memory node) of the memory cell is temporarily raised. When a write signal is transmitted by the write switch, the bit lines BLT / BLB are switched, and data rewrite (inverse write) of the memory node is performed correspondingly. As shown in the figure, it is confirmed that even if the MOSFETs Q7 and Q8 for the ROM function as described above are added, the read and write operations similar to those of a normal SRAM memory cell can be performed without any problem. In particular, as in the above-described embodiment, by adding the MOSFET Q8 as a dummy, the input / output load balance of the latch circuit is improved.

  FIG. 6 shows an overall block diagram of an embodiment of a semiconductor device according to the present invention. This embodiment is directed to a microcomputer unit (system LSI or SOC), and each circuit block shown in the figure is made of a single crystal silicon or the like by a known CMOS (complementary MOS) semiconductor integrated circuit manufacturing technique. It is formed on one substrate. The microcomputer LSI of this embodiment realizes high-performance arithmetic processing by, for example, a RISC (Reduced instruction set computer) type central processing unit CPU and integrates peripheral devices necessary for the system configuration, for example, for portable device applications. It has been.

  The CPU is the central processing unit, and the SRAM is a storage circuit according to the present invention, and is used as a high-speed, small-capacity storage device connected to the data bus BUS of a semiconductor device (SOC; system on chip). . A DRAM is a dynamic RAM, and is used as a low-speed, large-capacity storage device connected to the data bus BUS. LCDD is a liquid crystal drive circuit, for example, and performs a display operation. The interface circuit INF exchanges signals with the outside of the semiconductor device (SOC). The SRAM has a ROM portion like the memory cell MC shown in FIG. 4, and a boot program for starting the microcomputer is written therein.

  In the reset operation immediately after the power is turned on, the selection signal RE is generated in the SRAM, and the boot program in the ROM portion is transferred to the memory cell MC. As a result, the CPU accesses the SRAM, reads the boot program, and starts up. Thereafter, the boot program is rewritten corresponding to data writing by treating the SRAM as the SRAM. In this configuration, the SRAM (ROM) is used as the boot ROM and SRAM in a time division manner, so that the circuit can be simplified. In other words, the memory array portion becomes slightly larger as the ROM portion is added to the SRAM cell, but simplification as a whole can be achieved by sharing peripheral circuits such as the address selection circuit and the sense amplifier. As for the operation speed, ROM can be read at the same speed as SRAM.

  FIG. 7 shows a circuit diagram of another embodiment of the memory cell according to the present invention. In this embodiment, the ROM portion is composed of a pair of CNT and CNB. That is, the ROM storage information is transmitted complementarily to the storage nodes MT and MB via the switch MOSFETs Q7 and Q8 by the MOSFETs Q7 and Q8. For example, when the connection portion CNT is connected to the power supply voltage VDD side, the connection portion CNB is connected to the ground potential VSS side. On the contrary, when the connection portion CNT is connected to, for example, the ground potential VSS side, the connection portion CNB is connected to the power supply voltage VDD side. Thus, the ROM storage information can be transmitted to the storage nodes MT and MB by the MOSFETs Q7 and Q8 which are smaller than the embodiment of FIG. 1, and the cell size can be reduced.

  Although the invention made by the inventor has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. For example, the configuration of the ROM section can take various embodiments such as one that generates stored information depending on whether or not wiring is cut by a fuse or a laser beam. The latch circuit constituting the memory cell can be modified such as a latch circuit using an N-channel MOSFET and high-resistance polysilicon in addition to a CMOS inverter circuit. The layout of the memory cell of FIG. 3 can similarly take various embodiments depending on the elements used. The stored information stored in the ROM unit may be anything other than the boot program.

  The present invention can be widely used for semiconductor devices that require ROM / RAM in addition to the microcomputer.

1 is a circuit diagram of one embodiment of a memory cell according to the present invention. FIG. 2 is an operation explanatory diagram of one embodiment of the memory cell of FIG. 1. 1 is an element layout diagram of an embodiment of a memory cell according to the present invention. 1 is an overall circuit diagram of an embodiment of a memory circuit according to the present invention. FIG. 4 is an operation waveform diagram of the memory cell of the embodiment of FIGS. 1 and 3. 1 is an overall block diagram of an embodiment of a semiconductor integrated circuit device according to the present invention. FIG. 6 is a circuit diagram of another embodiment of the memory cell according to the present invention.

Explanation of symbols

Q1-Q8 ... MOSFET, WL ... Word line, BLT / BLB ... Bit line, RE ... Select line, MT, MB ... Storage node, NWEL ... N-type well region, PWEL1,2 ... P-type well region, MC ... Memory cell , WDR ... word driver, DEC ... decoder circuit, CTRL ... control circuit, SA ... sense amplifier, WA ... write amplifier, YS ... column switch,
CPU ... Central processing unit, BUS ... Bus, INF ... Interface, SRAM (ROM), DRAM ... Memory circuit, LCDD ... Liquid crystal drive circuit,

Claims (5)

Having a plurality of memory cells;
The memory cell
First and second inverter circuits having inputs and outputs cross-connected to the first and second storage nodes, respectively;
First and second switch MOSFETs provided between the first and second storage nodes and the first and second input / output terminals, respectively.
A third switch MOSFET provided between the first storage node and the third storage node;
The first and second storage nodes can write / read the first storage information from the first and second input / output terminals,
The third storage node is constantly supplied with a power supply voltage or a ground potential corresponding to the second storage information,
The storage information of the third storage node is transmitted to the first and second storage nodes with the third switch MOSFET turned on, and the first and second terminals are transmitted via the first and second switch MOSFETs. A semiconductor device which can be read out from the device. In claim 1,
The means for constantly supplying the power supply voltage or the ground potential to the third storage node corresponding to the second storage information is between the third storage node and the wiring layer for transmitting the power supply voltage or the ground potential. A semiconductor device used as a contact hole. In claim 2,
A fourth storage node;
A fourth switch MOSFET between the second storage node and the fourth storage node;
The second storage information is a semiconductor that supplies one of the power supply voltage and the ground potential to the fourth storage node when one of the power supply voltage and the ground potential is supplied to the third storage node. apparatus. In claim 3,
Multiple word lines,
A plurality of complementary bit lines;
A readout line;
The gates of the first and second switch MOSFETs of the memory cell are connected to the corresponding word line,
The first and second input / output terminals of the memory cell are connected to the corresponding complementary bit line,
The gate of the third switch MOSFET of the memory cell is a semiconductor device connected to the read line. In claim 4,
Further comprising a microcomputer;
The second storage information is a semiconductor device constituting a boot program for starting a microcomputer.

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