JP2006309909A - Semiconductor device, and method of testing the same, and electronic information apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To test a semiconductor device with reduced labors and costs in the semiconductor device where a plurality of semiconductor storage devices are mounted in one package. <P>SOLUTION: In the semiconductor device 20, a flash memory 30 and an SRAM 40 where an address bus 27, a data bus 28, and a part of control signal lines 25 and 26 are shared are mounted in the one package or constituted on the same chip. In the semiconductor device 20, using a write state machine 33 of the flash memory 30 as a test control circuit, an address signal, a data signal and a control signal of the SRAM 40 are controlled, and data is written/read from the flash memory 30 to the SRAM 40 to test the SRAM 40. By only testing the flash memory 30 from an external tester, the SRAM 40 is also tested. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device in which a plurality of semiconductor memory devices are mounted in one package or configured on the same chip, a test method thereof, and an electronic information device such as a personal computer or a mobile phone device using the same. About.

  Conventionally, as a semiconductor device, a logic semiconductor device used for controlling an electronic information device such as a mobile device such as a personal computer or a mobile phone device, and a control program for operating the logic semiconductor device are stored, It is roughly classified into a memory semiconductor device (semiconductor memory device) for storing data such as image data. Recently, a system LSI in which these logic semiconductor device and memory semiconductor device are configured on the same chip has also been developed.

  In such a semiconductor device, after a semiconductor circuit is fabricated on a wafer, a test is performed, and a semiconductor device that passes the test is shipped. In a semiconductor memory device, (1) a test in a wafer state and (2) a test after assembly are usually performed. For example, in the wafer state, a defective memory cell such as a short circuit generated due to dust or the like adhering to a semiconductor circuit in a semiconductor manufacturing process and a memory cell with insufficient margin are rejected. Thereafter, after the assembly, various tests such as function characteristics and AC characteristics of the semiconductor device are performed, and those passing the test are shipped.

  As mobile devices such as personal computers and mobile phone devices become more sophisticated, various types of semiconductor memory devices with large capacity are mounted. The mounting area on top is getting smaller.

  As a method for reducing the mounting area, a method of reducing the package size and mounting a plurality of semiconductor devices in one package, and a method of configuring a plurality of types of semiconductor devices on the same chip to form a system LSI Are widely used. That is, a configuration in which two or more types of semiconductor devices are mounted in one package has become the mainstream. At present, flash memory and SRAM (Static Random Access Memory), which are nonvolatile semiconductor memory devices, or flash memory and pseudo SRAM are mounted in the same package, and are mounted on almost all mobile phone devices.

  FIG. 22 is a block diagram showing an internal configuration example of a conventional flash memory which is a nonvolatile semiconductor memory device.

  In FIG. 22, a conventional flash memory 10 includes a nonvolatile memory array 11 as a storage unit, a write state machine 12 for controlling the algorithm when the nonvolatile memory array 11 is programmed or erased, An address pad 13 for obtaining address data when programming or erasing the memory array 11, a data pad 14 for obtaining write data when programming the nonvolatile memory array 11, and a write enable signal WE as a control signal And a control pad 15 for obtaining an output enable signal OE #.

  The write state machine 12 plays a major role in threshold control of memory cells, such as selection of each memory cell in the nonvolatile memory array 11, control and determination of verification, programming to each memory cell, and application of an erase pulse.

  Therefore, an address bus 16 for obtaining address data from the address pad 13 and a data bus 17 for obtaining write data from the data pad 14 are connected to the write state machine 12. In the write state machine 12, address decoding and data decoding of the nonvolatile memory array 11 are performed, and the address decoder and data decoder are controlled using these bus data.

  When a post-assembly test is performed on a semiconductor device in which two or more types of such semiconductor memory devices are mounted in one package, the test is usually sequentially performed by a tester corresponding to the semiconductor memory device to be tested. Is done. For example, in the case of a semiconductor device in which flash memory and SRAM are mounted in one package, first, a post-assembly test is performed on the flash memory, and after completion of the assembly, the tester is replaced and the SRAM is assembled. Tests are performed. A semiconductor device that has passed these two tests is regarded as a good product and shipped.

For example, Patent Document 1 proposes a technique that enables data to be moved from one memory to the other between two types of memories.
Japanese Utility Model Publication No. 60-131056

  Conventionally, a test after assembly for a semiconductor device in which a plurality of semiconductor memory devices are mounted in one package has been performed for each semiconductor memory device by replacing the tester.

  In this test method, each time a test of the semiconductor memory device is performed, it is necessary to perform the test using a tester suitable for the semiconductor memory device. In addition, when the test time of one semiconductor memory device is long, the throughput deteriorates and the occupancy rate of the tester increases, so that there is a problem that the test cost increases. Furthermore, for a system LSI in which a nonvolatile semiconductor memory device and other semiconductor memory devices are configured on the same chip, a tester suitable for each semiconductor memory device is required, and throughput is deteriorated. was there.

  As described above, Patent Document 1 proposes a control technique for moving data from an internal memory to an external memory. This is a non-volatile semiconductor memory device that tests other semiconductor memory devices. It is not a test method to do.

  The present invention solves the above-described conventional problems. In a semiconductor device in which a plurality of semiconductor memory devices are mounted in one package or configured on the same chip, another semiconductor memory device can be used. An object of the present invention is to provide a semiconductor device that can be tested with less labor and cost by performing a test of the semiconductor memory device, a test method thereof, and an electronic information device such as a personal computer or a mobile phone device using the semiconductor device. To do.

  A semiconductor device of the present invention includes a plurality of semiconductor memory devices mounted in one package, and a test control circuit for testing another semiconductor memory device in one semiconductor memory device of the plurality of semiconductor memory devices Is built in, thereby achieving the above object.

  Preferably, in the semiconductor device of the present invention, an address bus, a data bus, and a part of control signal lines are provided in common among the plurality of semiconductor memory devices, and the one semiconductor memory device has an address The nonvolatile semiconductor memory device can control signals, data signals, and control signals by an internal control circuit, and the other semiconductor memory device has the common address bus, data bus, and control signal line. Through the control circuit of the non-volatile semiconductor memory device, and using the control circuit of the non-volatile semiconductor memory device as the test control circuit, the address signal of the other semiconductor memory device The data signal and the control signal are controlled, and the data is read from the storage unit of the nonvolatile semiconductor memory device. Is read from the other semiconductor memory device, the data is read from the other semiconductor memory device, and the data is written to the storage unit of the nonvolatile semiconductor memory device. The device can be tested.

  A semiconductor device according to the present invention includes a plurality of semiconductor memory devices configured on the same chip, and a test control circuit for testing one of the plurality of semiconductor memory devices with another semiconductor memory device Is built in, thereby achieving the above object.

  Further preferably, the one semiconductor memory device in the semiconductor device of the present invention comprises a nonvolatile semiconductor memory device capable of controlling an address signal, a data signal, and a control signal by an internal control circuit, and the nonvolatile semiconductor memory device An address bus, a data bus, and a control signal line for controlling the other semiconductor memory device from the nonvolatile semiconductor memory device are provided between the other semiconductor memory device and the test control circuit Using the control circuit of the non-volatile semiconductor memory device, the address signal, data signal and control signal of the other semiconductor memory device are controlled to read out data from the memory unit of the non-volatile semiconductor memory device, and the other semiconductor Write data to the memory device and read data from the other semiconductor memory device By writing data in the storage unit of the semiconductor memory device, and can perform the testing of the other semiconductor memory device.

  Further preferably, the nonvolatile semiconductor memory device in the semiconductor device of the present invention is provided with an input / output pad capable of inputting / outputting an address signal, a data signal and a control signal to the outside.

  Further preferably, in the semiconductor device of the present invention, an address pad, a data pad and a control pad are provided as the input / output pads, and a control signal for a control signal which is connected to the control pad and can be controlled by the control circuit. An address bus for an address signal that is connected to the address pad for sending address data to the outside and can be controlled by the control circuit, and for taking data from the outside into the control circuit and for receiving data from the control circuit A data signal data bus for connecting the data pad for transmission to the outside and the control circuit is provided.

  Further preferably, the test result information for storing and storing at least the test result information among the test result information and the defect content information of the other semiconductor memory device in the nonvolatile semiconductor memory device in the semiconductor device of the present invention. A storage area is provided.

  Further preferably, the failure content information in the semiconductor device of the present invention is fail address data.

  Further, preferably, a non-volatile semiconductor memory device in the semiconductor device of the present invention is provided with a rewritable test sequence information storage area capable of storing a test sequence program corresponding to the test contents.

  Further, preferably, the operating frequency of the test control circuit in the semiconductor device of the present invention can be changed.

  Further, preferably, the semiconductor device of the present invention further includes output means for outputting test completion information and test result information of another semiconductor memory device.

  Further preferably, in the semiconductor device of the present invention, a first memory selection to switch to a semiconductor memory device to be used among a plurality of other semiconductor memory devices in accordance with a test result of the other semiconductor memory devices. It further has a control circuit.

  Further preferably, the first memory selection control circuit in the semiconductor device of the present invention is a test result storage flash memory capable of setting each test result information respectively corresponding to a plurality of the other semiconductor memory devices, A chip enable signal switching control circuit for switching to any one of the other semiconductor memory devices in accordance with the test result information set in the test result storage flash memory.

  Still preferably, in a semiconductor device according to the present invention, the first memory selection control circuit has a test result storage flash memory capable of setting each test result information corresponding to each of the plurality of other semiconductor memory devices. Then, according to the test result information set in the test result storage flash memory, switching to any one of the other semiconductor memory devices is performed.

  Further preferably, in the semiconductor device of the present invention, a second memory selection control circuit for switching to the semiconductor memory device to be used is selected from the plurality of other semiconductor memory devices according to the number of times of use and / or usage time information. Also have.

  Further preferably, the second memory selection control circuit in the semiconductor device of the present invention is for switching setting that allows setting of the number of times of use and / or the time of use corresponding to each of a plurality of other semiconductor memory devices. A flash memory, and a chip enable signal switching control circuit for switching to any one of the other semiconductor memory devices in accordance with the number of use times and / or usage time information set in the switching setting flash memory.

  Further, preferably, in the semiconductor device of the present invention, among the plurality of other semiconductor memory devices, the other semiconductor memory device is used according to the test result and the number of times of use and / or usage time information. A third memory selection control circuit for switching to the semiconductor memory device is further included.

  Further preferably, the third memory selection control circuit in the semiconductor device of the present invention is a test result storage flash memory capable of setting each test result information respectively corresponding to a plurality of the other semiconductor memory devices, A switching setting flash memory capable of setting usage counts and / or usage time information respectively corresponding to a plurality of other semiconductor memory devices, test result information set in the test result storage flash memory, and the test result information A chip enable signal switching control circuit for switching to any one of the other semiconductor memory devices in accordance with the number of times of use and / or usage time information set in the flash memory for switching setting.

  Further preferably, the flash memory for storing test results in the semiconductor device of the present invention comprises one or a plurality of bits of flash memory cells capable of setting test result information corresponding to each of the plurality of other semiconductor memory devices. Each has.

  Further preferably, the switching setting flash memory in the semiconductor device of the present invention has one or a plurality of bits that can set the number of times of use and / or the time of use corresponding to each of the plurality of other semiconductor memory devices. Each has a flash memory cell.

  Further preferably, in the semiconductor device of the present invention, switching between using any one of the plurality of other semiconductor storage devices or using a plurality or all of the semiconductor storage devices simultaneously is preferable. It further has a flash memory for switching setting.

  Further preferably, the flash memory for switching setting in the semiconductor device of the present invention is one or more capable of setting information indicating whether it is any one semiconductor memory device or a plurality or all of the semiconductor memory devices. It has a multi-bit flash memory cell.

  Further preferably, the chip enable signal switching control circuit in the semiconductor device of the present invention is a circuit for decoding the value of the flash memory cell.

  The method for testing a semiconductor device of the present invention performs a data write and read test on the one semiconductor memory device using the test control circuit of the one semiconductor memory device with respect to the semiconductor device of the present invention, Using the test control circuit, the other semiconductor memory device is controlled, data is read from the memory unit of the one semiconductor memory device, data is written to the other semiconductor memory device, and the other semiconductor memory device is read. By reading data from the device and writing the data to the storage portion of the one semiconductor memory device, the data writing and reading tests of the other semiconductor memory device are performed, thereby achieving the above object.

  The electronic information device of the present invention stores data in the semiconductor device of the present invention, thereby achieving the above object.

  The operation of the present invention will be described below with the above configuration.

  In the present invention, in a semiconductor device in which a plurality of semiconductor memory devices are mounted in one package or configured on the same chip, one semiconductor memory device among the plurality of semiconductor memory devices is replaced with another semiconductor memory device. A test control circuit for testing the semiconductor memory device is built in, and other semiconductor memory devices are tested using the test control circuit. Other semiconductor memory devices can be tested simply by testing a semiconductor memory device with a built-in test control circuit from an external tester, so that the throughput of the tester is improved, and one inexpensive tester is provided. Thus, it is possible to perform a series of tests on one semiconductor memory device after assembly and another semiconductor memory device.

  For example, the address bus, data bus, and control signal can be controlled by a nonvolatile semiconductor memory device that can control the address bus, data bus, and control signal by an internal control circuit (write state machine). Controlling address signals, data signals and control signals of other semiconductor memory devices via the line, reading data from the storage unit of the nonvolatile semiconductor memory device, writing data to other semiconductor memory devices, By reading data from another semiconductor memory device and writing data to the storage unit of the nonvolatile semiconductor memory device, it is possible to perform writing and reading tests of the other semiconductor memory device.

  In addition, a test result information storage area for storing and storing test results and defect contents of other semiconductor memory devices is provided in the nonvolatile semiconductor memory device, and the test results and defect contents are written during the test to complete the test. It becomes possible to know the test result by reading the data later. Furthermore, data can be read after the test is completed and used for analysis of defect contents and analysis for yield improvement. Furthermore, since this data is written for each apparatus, test log management by a tester is not required.

  Further, by providing a test sequence information storage area that can store and rewrite a test sequence program according to the test contents in the nonvolatile semiconductor memory device, the type of memory of the semiconductor memory device to be tested (SRAM, pseudo SRAM, etc.) ), A test program corresponding to the capacity and the memory array configuration can be stored. Further, the test program can be changed even after the semiconductor memory device is mounted on a mobile phone device or the like, and it is possible to cope with deterioration of the semiconductor memory device due to a change with time.

  Furthermore, by making it possible to change the operating frequency of the test control circuit, it is possible to use it for testing AC characteristics, such as guaranteeing access time.

  Furthermore, it is possible to output test completion information and test result information of a semiconductor device by observing the status of a control circuit, for example, a write state machine, from a specific terminal, and observe whether the test is being executed or the test has been completed. It is possible to discriminate between non-defective products and defective products immediately after the end of the test.

  Furthermore, a semiconductor memory device of a plurality of chips connected by an address bus, a data bus, and a control signal so as to be controllable from the nonvolatile semiconductor memory device (a plurality of other semiconductor memory devices) ) In a single package, for example, one chip is used among a plurality of semiconductor memory devices, and the remaining semiconductor memory devices are reserved. For example, each time the power is turned on, the semiconductor memory device is tested by a non-volatile semiconductor memory device having a test function, and the test result and the switching setting value of a plurality of semiconductor memory devices are stored in the non-volatile memory in the non-volatile semiconductor memory device. If saved, the semiconductor memory device of this device can be made to be a highly reliable device by switching between using and not using the semiconductor memory device in the package based on the information of the switching setting value. It becomes possible.

  As described above, according to the present invention, in a semiconductor device (device) in which a plurality of types of semiconductor memory devices are mounted in one package or configured on the same chip, one of the semiconductor memory devices is a test. A control circuit is built in, and the test control circuit is used to control an address signal, a data signal, and a control signal to test other semiconductor memory devices, so that a test control circuit is built in from an external tester. By testing only the semiconductor memory device, other semiconductor memory devices can be tested, the tester throughput can be improved, and the post-assembly test can be performed with an inexpensive tester.

  Further, by providing a rewritable test sequence storage area in the nonvolatile semiconductor memory device, a test corresponding to the type, capacity, and memory array configuration of the semiconductor memory device to be tested can be performed.

  Further, the test sequence program can be changed even after the semiconductor memory device is mounted on a mobile phone device or the like, and it is possible to cope with deterioration of the semiconductor memory device due to a change with time.

  Furthermore, in a device in which semiconductor memory devices of a plurality of chips are encapsulated in one package, one chip of a plurality of semiconductor memory devices (a plurality of other semiconductor memory devices) is used, and the remaining semiconductor memory devices are left as spares. Keep it. For example, each time the power is turned on, the semiconductor memory device is tested by a non-volatile semiconductor memory device having a test function, and the test result and the switching setting value of a plurality of semiconductor memory devices are stored in the non-volatile memory in the non-volatile semiconductor memory device If saved, the semiconductor memory device of this device can be specified as a highly reliable device by switching between using and not using the semiconductor memory device in the package based on the information of this switching setting value. it can.

Embodiments 1 to 10 of a semiconductor device and a test method thereof according to the present invention will be described below in detail with reference to the drawings. In the following, one semiconductor memory device that controls the test is a flash memory that is a nonvolatile semiconductor memory device, the other semiconductor memory device to be tested is an SRAM, and a write state machine in the flash memory is used as a test control circuit. An example will be described. However, the present invention is not limited to these semiconductor memory devices as long as it includes a plurality of semiconductor memory devices. Further, the number of semiconductor memory devices is not limited to two, and may be three or more (plural).
(Embodiment 1)
FIG. 1 is a perspective view schematically showing a configuration example of a main part of a semiconductor device according to Embodiment 1 of the present invention.

  In FIG. 1, the semiconductor device 20 according to the first embodiment includes an SRAM 40 arranged on a flash memory 30 and mounted in one package, and includes an address pad 21, a data pad 22, a control pad 23, and the flash memory 30 and Wire bondings 24 are provided that connect the respective pads of the SRAM 40. This type of semiconductor device is now widely used and is a common bonding form.

  FIG. 2 is a block diagram for explaining the connection state of the control signals, the address bus, and the data bus between the flash memory 30 and the SRAM 40 mounted on the semiconductor device 20 of FIG.

  As shown in FIG. 2, chip enable signal lines (F_CE # 31 and S_CE # 41) serving as enable signals for both semiconductor storage devices (flash memory 30 and SRAM 40) are independent, but other control signal lines (write The enable signal line WE # 25 and the output enable signal line OE # 26), the address bus 27, and the data bus 28 are shared.

  FIG. 3 is a block diagram showing an internal configuration example of the flash memory 30 of FIG.

  In FIG. 3, a flash memory 30 includes a nonvolatile memory array 32 as a storage unit, a write state machine 33 as a control circuit for controlling the algorithm when the nonvolatile memory array 32 is programmed or erased, An address pad 34 for obtaining address data when programming or erasing the nonvolatile memory array 32, a data pad 35 for obtaining write data when programming the nonvolatile memory array 32, and a write enable as a control signal Control pads 36a to 36c for obtaining a signal WE #, an output enable signal OE #, and a chip enable signal F_CE #.

  The write state machine 33 is connected to an address bus 37 for obtaining address data from the address pad 34 and a data bus 38 for obtaining write data from the data pad 35. The write state machine 33 performs address decoding and data decoding of the nonvolatile memory array 32 using these bus data, and controls the address decoder and data decoder. Further, the write state machine 33 controls the algorithm when the nonvolatile memory array is programmed or erased. The write state machine 33 selects each memory cell of the nonvolatile memory array, controls the verify, and performs the verify pass / verify fail. This circuit plays a large role in threshold control of the memory cell, such as determination of the memory cell, programming to each memory cell, and application of an erase pulse.

  In order to perform these controls, the write state machine 33 is provided with a bus for obtaining address information for programming or erasing from the address pad and a bus for obtaining write data information when programming from the data pad. It is enough to be there.

  This is because if the bus memory can be used to perform address decoding and data decoding of the flash memory array, the write state machine 33 can perform the intended operation.

  In the first embodiment, in order to send a control signal to the outside, control signal lines (write enable signal line 39a and output enable signal line 39b) that can be controlled by the write state machine 33 are provided, and control pads 36a and 36b are provided. Connected with. In addition, an address bus 37a that can be controlled by the write state machine 33 is provided to connect the address pad 34 to send address data to the outside. Further, a data bus 38a that can be controlled by the write state machine 33 is provided and connected to the data pad 35 in order to capture data from the outside into the write state machine 33 and send the data from the write state machine 33 to the outside. Yes.

  In the conventional flash memory 10 shown in FIG. 22 described above, an address bus 16 for the write state machine 12 to obtain address data from the address pad 13 and a data bus 17 for obtaining write data from the data pad 14 are provided. However, in the first embodiment, the write state machine 33 can be used to output address signals and control signals (write enable signal WE # and output enable signal OE #). Data signals can also be input / output using the write state machine 33. As shown in FIG. 2, the SRAM 40 includes a flash memory 30 via a common address bus 27, data bus 28, and control signal lines (write enable signal line WE # 25 and output enable signal line OE # 26). It is controlled by.

  A test method for the semiconductor device 20 according to the first embodiment will be described below with the above configuration.

  First, after the pass / fail test of the flash memory 30 is performed, the SRAM 40 is tested using the write state machine 33 of the flash memory 30. The test of the flash memory 30 is performed by testing the pass / fail of the flash memory 30 by writing predetermined data to a predetermined address in the non-volatile memory array 32 using the write state machine 33, reading it, and collating it with an expected value externally.

  The quality test of the SRAM 40 is performed by controlling the write state machine 33 that is a test control circuit by a tester used in the quality test of the flash memory 30.

  In the first embodiment, the write state machine 33 that is a control circuit of the flash memory 30 is used as a test control circuit for testing the SRAM 40, and the address signal, data signal, and control signal of the SRAM 40 are controlled by the write state machine 33. Then, the SRAM 40 is tested by writing data to and reading data from the nonvolatile memory array 32 of the flash memory 30.

  FIG. 4 is a flowchart showing a data write sequence operation to the SRAM 40 in FIG. 2, and FIG. 5 is a flowchart showing a data read sequence operation from the SRAM 40 in FIG.

  In the semiconductor device 20 according to the first embodiment, the chip enable signal (S_CE #) of the SRAM 40 cannot be controlled by the flash memory 30. Therefore, during the test, the SRAM 40 is previously controlled to be enabled from the outside.

  The write state machine 33 in the flash memory 30 controls the control signal, address signal, and data signal of the SRAM 40 to execute a write algorithm as shown in FIG.

  As shown in FIG. 4, first, when the address of the SRAM 40 is set via the address buses 37a and 27 by the write state machine 33 in step S1, the write state machine 33 passes through the data buses 38a and 28 in step S2. Data is written into the memory cell corresponding to the address of the SRAM 40. Further, if it is not the last address in step S3 (NO), the address is incremented in step S4, and the processes in steps S1 to S3 are repeated for the next address. In this way, the processes in steps S1 to S3 are repeated until the final address. If it is the last address in step S3 (YES), the data writing process ends. As a result, predetermined test data is written in the SRAM 40.

  Next, the control signal and address signal of the SRAM 40 are controlled by the write state machine 33 in the flash memory 30 with respect to the SRAM 40 in this state, and a read algorithm as shown in FIG. 5 is executed.

  As shown in FIG. 5, first, when the address of the SRAM 40 is set via the address buses 37a and 27 by the write state machine 33 in step S11, the write state machine 33 passes through the data buses 38a and 28 in step S12. Data written in the memory cell corresponding to the address of the SRAM 40 is read out. In step S13, the write state machine 33 compares the expected value data that would have been written to the memory cell at that address with the actually read data. If the comparison result shows that the data match in step S13 (YES), the process proceeds to step S14, and it is determined in step S14 whether it is the final address. If it is not the last address in step S14 (NO), the address is incremented in step S15, and the processes in steps S11 to S14 are repeated. If the data do not match in step S13 (NO), a test failure occurs in step S16, the SRAM 40 is detected as a defective test product, and the data reading process ends. In step S14, the processes in steps S11 to S14 are repeated until the final address. If the final address is determined in step S14 (YES), the data of all the addresses has been tested. The data read process is completed after the test is detected as non-defective.

As described above, according to the first embodiment, in the semiconductor device 20 in which the flash memory 30 and the SRAM 40 are mounted in one package, the write state machine 33 of the flash memory 30 is used as a test control device. By controlling the address signal, the data signal, and the control signal, the SRAM 40 can be tested in series after the flash memory 30A test.
(Embodiment 2)
In the first embodiment, a semiconductor device in which a plurality of semiconductor memory devices are mounted in one package has been described. In the second embodiment, a semiconductor device in which a plurality of semiconductor memory devices are configured on the same chip is described. To do.

  FIG. 6 is a block diagram showing a configuration example of a main part of a semiconductor device according to Embodiment 2 of the present invention.

  In FIG. 6, the semiconductor device 20A of the second embodiment is a system LSI in which a flash memory 30A and an SRAM 40A are configured on the same chip.

  As in the case of the flash memory 30 of the first embodiment, the flash memory 30A is provided with a write state machine that can control an address signal, a data signal, and a control signal.

  Further, between the flash memory 30A and the SRAM 40A, in order to control the SRAM 40A from the flash memory 30A, an address bus 27A, a data bus 28A, a WE signal line 25A as a control signal line, an OE signal line 26A, and a CE signal line 29A. Is provided.

In the second embodiment, a write state machine that is a control circuit of the flash memory 30A is used as a test control circuit for testing the SRAM 40A, and the address signal, data signal, and control signal of the SRAM 40A are processed by the write state machine of the flash memory 30A. 4 and 5 are sequentially executed to write data to the SRAM 40A and read data from the nonvolatile memory array of the flash memory 30A. Thus, the test of the SRAM 40A can be performed in series after the test of the flash memory 30A.
(Embodiment 3)
In the third embodiment, test result information storage for storing and storing test results and defect contents (for example, fail address data) of the other semiconductor memory device to be tested in one semiconductor memory device that controls the test A configuration example provided with regions will be described.

  FIG. 7 is a block diagram showing an example of the internal configuration of the flash memory 30B in the semiconductor device of the third embodiment.

  In FIG. 7, the flash memory 30B has a test result information storage area 51 for storing and storing test results and defect contents in addition to the configuration of the flash memory 30 shown in FIG. The test result information storage area 51 may be provided in the nonvolatile memory array, or a separate memory area may be provided.

  Further, the control signal line 52 from the write state machine 33B is connected to the test result information storage area 51 so that the test result storage area 51 can be controlled by the write state machine 33B.

Using the flash memory 30B configured as described above, the SRAM 40 mounted in the same package as in the first embodiment or the SRAM 40A configured on the same chip as in the second embodiment. If the test fails (step S15 in FIG. 5) or the test passes the test (step S16 in FIG. 5) during the execution of the test, the test result is sent from the write state machine 33B via the control signal line 52. The test result information storage area 51 can be written as a fail flag or a pass flag. Further, after the test is completed, the test result can be used by reading this flag. Further, by writing data such as a fail address in the test result information storage area 51 made of a nonvolatile memory during the test, the data is read after the test is completed, and analysis for defect contents and analysis for improving the yield are performed. It can be useful for implementation. Furthermore, since this data is written for each semiconductor device, it is not necessary to manage a test log by a tester.
(Embodiment 4)
In the fourth embodiment, a configuration example in which a test sequence information storage area capable of storing and rewriting a test sequence program according to the test contents of the other semiconductor storage device to be tested is provided in one semiconductor storage device that controls the test. Will be described.

  FIG. 8 is a block diagram showing an example of the internal configuration of the flash memory 30C in the semiconductor device according to the fourth embodiment.

  8, the flash memory 30C has a test sequence information storage area 61 in which a test sequence program can be stored and rewritten in addition to the configuration of the flash memory 30 shown in FIG. The test sequence information storage area 61 may be provided in the nonvolatile memory array or may be provided separately.

  Further, a control signal line 62 from the write state machine 33C is connected to the test sequence information storage area 61 so that the test sequence information storage area 61 can be controlled by the write state machine 33C.

  Using the flash memory 30C configured as described above, the SRAM 40 mounted in the same package as in the first embodiment or the SRAM 40A configured on the same chip as in the second embodiment is used. On the other hand, the test is performed by the write state machine 33C according to the program in which the test sequence is expressed. The test sequence program is stored in a test sequence information storage area 61 composed of a rewritable nonvolatile memory (flash memory). By reading the test program from the test sequence information storage area 61 by the write state machine 33C, A test is run.

According to the fourth embodiment, by configuring the test sequence information storage area 61 with a rewritable nonvolatile memory, the test content corresponding to the semiconductor memory device to be tested by the flash memory 30C is written or the test content is written. It becomes possible to change. Further, when screening by a new test becomes necessary, the test sequence stored in the test sequence information storage area 61 composed of a rewritable nonvolatile memory even after a semiconductor device is mounted on a mobile phone device or the like By changing the contents of the program, it is possible to cope with the test.
(Embodiment 5)
In the fifth embodiment, an example of a test method will be described with reference to FIG. 9 when the present invention is used for an AC test such as access time guarantee.

  Normally, the write state machine operates according to an operation clock signal having a constant period. The writing to the SRAM and the reading operation from the SRAM are performed according to this clock signal.

  Therefore, the operating frequency of the write state machine can be changed, whereby the access time changes, and the delay time from data setting to data fetching changes. For example, as shown in FIG. 9, the operation clock cycle of the write state machine is set to 20 ns, and the data read test from the SRAM is performed at the timing as shown in FIG. When the read data matches the expected value, it is possible to guarantee a test specification of 80 ns for the access time when data is taken in from address setting, and an AC characteristic test can be performed. .

Further, by combining with the configuration provided with the test sequence information storage area 61 as shown in FIG. 8 above, for example, if the device has an AC characteristic that deteriorates with use time, the deterioration is mounted on a mobile phone device or the like. It becomes possible to test. In this case, a test sequence program for testing the AC characteristics is stored in the test sequence information storage area 61 of the flash memory, and a test for evaluating the AC characteristics when a predetermined operation such as power-on is performed is performed. If it is performed, it is possible to inform the user of the cellular phone device of the result of the AC characteristic.
(Embodiment 6)
In the sixth embodiment, a method of notifying the completion of the test of the other semiconductor memory device to be tested and whether the test is good or bad will be described with reference to FIGS. 10 and 11. FIG.

  As shown in FIG. 10, by outputting the state of the write state machine from a specific terminal, for example, RY / BY #, on time, it is possible to observe various information during the test execution and the test end.

  As shown in FIG. 11, immediately after the end of the test, for example, in the case of a non-defective product, the output from this terminal is toggled, so that a non-defective product or a defective product can be discriminated based on the presence or absence of the toggle. Here, the toggle “Yes” is identified as a defective product, and the “No” toggle is identified as a non-defective product.

In the following seventh to tenth embodiments, the case where the write state machine in the flash memory is used as a test control circuit will be described. By switching the enable control of a plurality of SRAMs in accordance with the test result, the test-passed SRAM is changed. The case where it is possible to select and control and maintain the high reliability of the SRAM will be sequentially described.
(Embodiment 7)
In the seventh embodiment, a case will be described in which a flash memory has a function of switching use / nonuse of a plurality of SRAMs according to a test result.

  FIG. 12 is a block diagram showing a connection state of a control signal, an address bus and a data bus of a flash memory and a plurality of SRAMs mounted in the semiconductor device according to the seventh embodiment, and an internal configuration example thereof.

  In FIG. 12, the semiconductor device 20D of the seventh embodiment has a flash memory 30D and a plurality of SRAMs 401 and 402 (two in this case), and control signal lines (WE #, CE # signal lines) between them. The address bus and the data bus are connected.

  In addition to the write state machine 33 described above, the flash memory 30D includes a test result storage flash memory 71 and a chip enable signal (CE) as a first memory selection control circuit 70D (or a chip selection control circuit) using a test result. ) A switching control circuit 72 is provided.

  The test result storage flash memory 71 can set the test result information of the SRAMs 401 and 402.

  The CE switching control circuit 72 is a circuit for switching to one of the SRAMs 401 and 402 according to the test result information of the SRAMs 401 and 402 set in the test result storage flash memory 71.

  FIG. 13 is a circuit block diagram showing a connection relationship between the test result storing flash memory 71 and the CE switching control circuit 72 and the SRAMs 401 and 402 in FIG.

  In FIG. 13, the test result storage flash memory 71 includes test result information (non-defective product state “0”, defective product state “1”) of the SRAM 401 and test result information (non-defective product) of the SRAM 402. A flash memory cell 71b capable of setting a state “0” and a defective product state “1”).

  The CE switching control circuit 72 includes inverters 72a to 72c and NANDs 72d and 72e, and is a circuit that decodes the values of the flash memory cells 71a and 71b.

  The chip enable signal pad S_CE # is connected to one input terminal of the NAND 72d and one input terminal of the three inputs of the NAND 72e via the inverter 72a. The flash memory cell 71a is connected to the other input terminal of the NAND 72d via the inverter 72b and another one input terminal of the three inputs of the NAND 72e without passing through the inverter 72b. The flash memory cell 71b is connected to the remaining one input terminal of the three inputs via the inverter 72c. The output terminal of the NAND 72d is connected to the chip enable signal pad CE # of the SRAM 401 via the chip enable signal pad S1_CE #. The output terminal of the NAND 72e is connected to the chip enable signal pad CE # of the SRAM 402 via the chip enable signal pad S2_CE #.

  In this example, the chip enable pads connected to the chip enable pads of the SRAMs 401 and 402 are used to receive S1_CE # and S2_CE # which are used / not used chip enable signal pads and a chip enable signal for controlling the SRAM from the outside. A pad S_CE # is newly provided.

  In addition, a CE switching control circuit 72 is provided that is used when signals from the chip enable signal pads S_CE # to S1_CE # and S2_CE # are generated from the test result storage flash memory 71.

  Here, FIG. 14 shows a state in which control signals, address signals, and data signals are connected to both the flash memory and the SRAM when the flash memory and the SRAM are mounted in one package. This device is very popular now and is a common connection form.

  FIG. 14 is a block diagram showing a connection state of a control signal, an address bus and a data bus of a flash memory and a plurality of SRAMs mounted on a semiconductor device according to a modification of the seventh embodiment, and an internal configuration example thereof.

  In FIG. 14, a semiconductor device 20D-1 according to a modification of the seventh embodiment includes a flash memory 30D-1 and a plurality of SRAMs, and control signal lines (WE #, OE #, CE # signals) between them. Line), an address bus, and a data bus.

  In addition to the write state machine 33 described above, the flash memory 30D-1 has only the test result storage flash memory 71 as the first memory selection control circuit 70D-1 using the test results.

  In the seventh embodiment, a method for switching the control of a plurality of SRAMs (here, two) using this test result is described. However, the test operation is the same as that in the first embodiment. The explanation is omitted here.

  The operation of the seventh embodiment will be described with the above configuration.

  First, at the device shipment stage, the flash memory 30D for setting the usage status of the SRAMs 401 and 402 outputs “0” indicating the usage status.

  At this time, the external access signal S_CE # to the SRAMs 401 and 402 controls the signal S1_CE # for controlling the SRAM 401, and the signal S2_CE # for controlling the SRAM 402 is always disabled (not used).

  If the test algorithm of the SRAMs 401 and 402 is set in advance when the power to the device is turned on, the test of the SRAMs 401 and 402 is performed by the flash memory 30D by the method already described at the time of turning on the power. In this case, the output signal (the output signal from the CE switching control circuit 72 or the test result storage flash memory 71) is set to "1" by setting the flash memory cell 71a representing the use state of the SRAM 401 to the program state.

  Due to the change in the output signal, the external access signal S_CE # to the SRAMs 401 and 402 controls the signal S2_CE # that controls the SRAM 402, and the signal S1_CE # that controls the SRAM 401 always changes to a disabled (unused) state. .

  With the above algorithm, the SRAM chip access target is moved from the SRAM 401 to the SRAM 402.

Such a mechanism is very effective for parts that require high reliability, such as a car control device.
(Embodiment 8)
In the eighth embodiment, the number of times of use and / or the time of use is stored in advance, and when a preset number of times has been reached or when a preset time has elapsed, a plurality of SRAMs can be used. A case of switching to SRAM will be described.

  FIG. 15 shows a case where a flash memory cell capable of storing the number of uses for one SRAM is provided with 4 bits and a control circuit capable of decoding the value of the flash memory cell.

  FIG. 15 is a block diagram showing a connection state of a control signal, an address bus and a data bus of a flash memory and a plurality of SRAMs mounted on a semiconductor device according to the eighth embodiment, and an example of an internal configuration thereof.

  In FIG. 15, the semiconductor device 20E of the eighth embodiment has a flash memory 30E and a plurality of SRAMs 401 and 402 (two in this case), and control signal lines (WE #, OE # signal lines) between them. The address bus and the data bus are connected.

  In addition to the write state machine 33 described above, the flash memory 30E includes a CE switching control circuit 72E and a switching setting flash memory 73 as a second memory selection control circuit 70E (or chip selection control circuit) that performs memory selection. is doing.

  The switching setting flash memory 73 makes it possible to set the number of times of use and the use time of the SRAMs 401 and 402 in advance.

  The CE switching control circuit 72E is a circuit for switching to one of the SRAMs 401 and 402 in accordance with the number of use times and the usage time of the SRAMs 401 and 402 set in the switching setting flash memory 73.

  FIG. 16 is a circuit block diagram showing a connection relationship between the flash memory for switching setting and CE switching control circuit of FIG. 15 and a plurality of SRAMs 401 and 402.

  In FIG. 16, the switching setting flash memory 73 includes one or a plurality of bits (here, 4 bits) of flash memory cells 73 a capable of setting the number of times of use of one SRAM, eg, SRAM 401, and one SRAM, eg, SRAM 402. It has one or a plurality of bits (here, 4 bits) flash memory cell 73b that can set the number of times of use.

  The CE switching control circuit 72E includes NORs 72f and 72g and NANDs 72h to 72k in addition to the inverters 72a to 72c and the NANDs 72d and 72e, and is a circuit for decoding the value of the flash memory cell.

  The chip enable signal pad S_CE # is connected to one input terminal of the NAND 72d and one input terminal of the three inputs of the NAND 72e via the inverter 72a. Further, each output terminal of four (4 bits) flash memory cells 73a for the SRAM 401 is connected to each input terminal of each of the two-input NANDs 72h and 72i, and each output terminal of each NAND 72h and 72i is a two-input terminal. The output terminal of the NOR 72f is connected to the other input terminal of the NAND 72d via the inverter 72b and another input terminal of the three inputs of the NAND 72e without passing through the inverter 72b. Furthermore, each output terminal of four (4 bits) flash memory cells 73b for the SRAM 402 is connected to each input terminal of each of the two-input NANDs 72j and 72k, and each output terminal of each NAND 72j and 72k is a two-input terminal. The output terminal of the NOR 72g is connected to the remaining one input terminal of the three inputs via the inverter 72c. The output terminal of the NAND 72d is connected to the chip enable signal pad CE # of the SRAM 401 via the chip enable signal pad S1_CE #. The output terminal of the NAND 72e is connected to the chip enable signal pad CE # of the SRAM 402 via the chip enable signal pad S2_CE #.

  The operation of the eighth embodiment will be described with the above configuration.

  First, when every bit of power is turned on, writing to the flash memory cell (here, first, flash memory cell 73a for the SRAM 401) bit by bit, the SRAM 401 is first used in the eighth embodiment. However, if the number of times of use of the SRAM 401 is set to “4”, the output signal from the CE switching control circuit 72E (a logic circuit that switches at the fourth number of times of use) is switched at the fourth time of use. The SRAM 401 to be used is switched to the SRAM 402. When the SRAM 402 is used, each time the power is turned on, data is written bit by bit into the flash memory cell 73b for the SRAM 402. When a plurality of SRAMs are prepared, this is repeated a plurality of times.

  Next, regarding the switching of the SRAM with respect to the usage time, the usage time is counted by the write state machine 33 using an oscillation circuit (clock circuit) in the flash memory as in the above case, and at a certain specified time. When it reaches, the flash memory cell is sequentially written. Here, after writing to the flash memory cell 73a for the SRAM 401, after a predetermined time has elapsed, this is detected and writing to the flash memory cell 73b for the SRAM 402 is performed.

  In the eighth embodiment, since the setting flash memory cells 73a and 73b have 4 bits, the SRAM to be used is switched from the SRAM 401 to the SRAM 402 when used for (a prescribed time) × 4 bits.

By using the switching algorithm described above, it is possible to obtain high reliability of the SRAM.
(Embodiment 9)
In the ninth embodiment, a case will be described in which the SRAM is switched using both the test result and the information on the number of times of use and / or the time of use.

  FIG. 17 shows the case of switching to the SRAM to be used from among a plurality of SRAMs depending on the test result and the number of times of use or / and the time of use.

  FIG. 17 is a block diagram showing a connection state of a control signal, an address bus and a data bus of a flash memory and a plurality of SRAMs mounted in the semiconductor device according to the ninth embodiment, and an internal configuration example thereof.

  In FIG. 17, the semiconductor device 20F of the ninth embodiment has a flash memory 30F and a plurality of SRAMs 401 and 402 (two in this case), and control signal lines (WE #, OE # signal lines) between them. The address bus and the data bus are connected.

  In addition to the write state machine 33 described above, the flash memory 30F includes a test result storage flash memory 71, a CE switching control circuit 72F, and a switching setting as a memory selection control circuit 70F (or a chip selection control circuit) using a test result. A flash memory 73.

  The test result storage flash memory 71 can set the test result information of the SRAMs 401 and 402.

  The switching setting flash memory 73 makes it possible to set the number of times of use and the use time of the SRAMs 401 and 402 in advance.

  The CE switching control circuit 72F corresponds to the test result information of the SRAMs 401 and 402 set in the test result storing flash memory 71 and the number of times and the usage time of the SRAMs 401 and 402 set in the switching setting flash memory 73. , A circuit for switching to one of the SRAMs 401 and 402.

  FIG. 18 is a circuit block diagram showing a connection relationship between the test result storing flash memory 71, the switching setting flash memory 73 and the CE switching control circuit 72F and the plurality of SRAMs 401 and 402 in FIG.

  In FIG. 18, the test result storing flash memory 71 includes test result information (non-defective product state “0”, defective product state “1”) in the SRAM 401, and test result information (non-defective product) in the SRAM 402. A flash memory cell 71b capable of setting a state “0” and a defective product state “1”).

  The switching setting flash memory 73 includes a flash memory cell 73 a having a 4-bit flash memory cell that can set the number of times the SRAM 401 is used (4 bits; use state “0”, non-use state “1”); A 4-bit flash memory cell 73b that can set the number of times of use (4 bits; use state “0”, non-use state “1”).

  The CE switching control circuit 72F includes inverters 72m and 72n and NANDs 72p and 72q in addition to the inverters 72a to 72c, NANDs 72d and 72e, NOR 72f and 72g, and NANDs 72h to 72k described above, and decodes the values of the flash memory cells.

  The chip enable signal pad S_CE # is connected to one input terminal of the NAND 72d and one input terminal of the three inputs of the NAND 72e via the inverter 72a. The output terminals of the four flash memory cells 73a for the SRAM 401 are connected to the input terminals of the 2-input NANDs 72h and 72i, and the output terminals of the NANDs 72h and 72i are connected to the input terminals of the 2-input NOR 72f. The output terminal of the NOR 72f and the output terminal of the flash memory cell 71a via the inverter 72m are input to the NAND 72p, and the output terminal of the NAND 72p is connected to the other input terminal of the NAND 72d via the inverter 72b and the inverter 72b. Without being connected to one input terminal of the three inputs of the NAND 72e. Furthermore, the output terminals of the four flash memory cells 73b for the SRAM 402 are connected to the input terminals of the 2-input NANDs 72j and 72k, and the output terminals of the NANDs 72j and 72k are connected to the input terminals of the 2-input NOR 72g. The output terminal of the NOR 72g and the output terminal of the flash memory cell 71b through the inverter 72n are input to the NAND 72q, and the output terminal of the NAND 72q is connected to the remaining one input terminal of the three inputs through the inverter 72c. Yes. The output terminal of the NAND 72d is connected to the chip enable signal pad CE # of the SRAM 401 via the chip enable signal pad S1_CE #. The output terminal of the NAND 72e is connected to the chip enable signal pad CE # of the SRAM 402 via the chip enable signal pad S2_CE #.

With the above configuration, when the number of times of use exceeds the specified number of times, or when the test of the SRAM 401 using the flash memory results in a test failure, the SRAM to be used is switched from the SRAM 401 to the SRAM 402, and the SRAM is more highly reliable. It becomes possible to achieve sexualization.
(Embodiment 10)
In the tenth embodiment, a case of switching between the high reliability use mode and the large capacity use mode in a plurality of SRAM usage methods will be described.

  FIG. 19 shows the case of a semiconductor memory device capable of switching between using one of a plurality of equivalent SRAMs or using all SRAMs simultaneously.

  FIG. 19 is a block diagram showing a connection state of a control signal, an address bus and a data bus of a flash memory and a plurality of SRAMs mounted in the semiconductor device according to the tenth embodiment, and an example of an internal configuration thereof.

  In FIG. 19, the semiconductor device 20G of the tenth embodiment has a flash memory 30G and a plurality of SRAMs 401 and 402 (two here), and control signal lines (WE #, OE # signal lines) between them. The address bus and the data bus are connected.

  In addition to the write state machine 33 described above, the flash memory 30G includes a test result storage flash memory 71 and a CE switching control circuit 72G as a fourth memory selection control circuit 70G (or a chip selection control circuit) using the test results. And a switching setting flash memory 73G.

  The test result storage flash memory 71 can set the test result information of the SRAMs 401 and 402.

  The switching setting flash memory cell 73G can set each switching information of the high reliability use mode and the large capacity use mode.

  The CE switching control circuit 72G includes test result information of the SRAMs 401 and 402 set in the test result storage flash memory 71, and switching information of the high reliability use mode or the large capacity use mode set in the switch setting flash memory 73G. This is a circuit for switching to one of the SRAMs 401 and 402 according to.

  FIG. 20 is a circuit block diagram showing a connection relationship between the test result storing flash memory 71, the switching setting flash memory 73G and the CE switching control circuit 72G and the plurality of SRAMs 401 and 402 in FIG.

  In FIG. 20, a test result storage flash memory 71 includes test result information (non-defective product state “0”, defective product state “1”) in the SRAM 401, and test result information (non-defective product) in the SRAM 402. A flash memory cell 71b capable of setting a state “0” and a defective product state “1”).

  The switching setting flash memory 73G is a high-reliability use mode that is any one of the semiconductor storage devices or a switching information (high-reliability) that is a large-capacity use mode that is a plurality or all of the semiconductor storage devices (SRAM 401 and 402 in this case). 1 or a plurality of bits (here, 1 bit) of flash memory cells 73g that can set the use mode “0” and the large capacity use mode “1”).

  The CE switching control circuit 72G includes inverters 72r and 72s, OR 72t and 72u, and NAND 72v and 72w in addition to the inverters 72a to 72c and NANDs 72d and 72e described above, and is a circuit that decodes the value of the flash memory cell.

  The chip enable signal pad S (1) _CE # is connected to one input terminal of the NAND 72d through the inverter 72a. The chip enable signal pad S (1) _CE # is connected to one input terminal of the OR 72t. The flash memory cell 71a is connected to the other input terminal of the NAND 72d through the inverter 72a and is connected to the other input terminal of the NAND 72v through the inverter 72s. The flash memory cell 73g is connected to the other input terminal of the OR 72t, and is connected to one input terminal of each of the OR 72u and the NAND 72v via the inverter 72r. The chip enable signal pad S (2) _CE # is connected to the other input terminal of the OR 72u. Each output terminal of the OR 72t and 72u is connected to one input terminal of three inputs of the NAND 72e through the NAND 72w. The output terminal of the NAND 72v is connected to another input terminal of the three inputs of the NAND 72e. Further, the flash memory cell 71b is connected to the remaining one input terminal of three inputs via the inverter 72c. The output terminal of the NAND 72d is connected to the chip enable signal pad CE # of the SRAM 401 via the chip enable signal pad S1_CE #. The output terminal of the NAND 72e is connected to the chip enable signal pad CE # of the SRAM 402 via the chip enable signal pad S2_CE #.

  As described above, together with the flash memory cells 71a and 71b for setting the test results of the SRAMs 401 and 402, the flash memory cell 73g for setting the switching information between the high reliability use mode and the large capacity use mode, and these flash memories A CE switching control circuit 72G for decoding each information of the cells 71a, 71b and 73g and a chip enable signal to the SRAMs 401 and 402 is provided.

  With the above configuration, in the high-reliability use mode, the flash memory test is performed when the power is turned on, and either the SRAM 401 or the SRAM 402 is used according to the result, so the chip enable signal for accessing the SRAM is S (1). It is sufficient to input only to _CE #. At this time, a memory map like the high reliability mode as shown in FIG.

  On the other hand, by setting the output of the use mode switching setting flash memory 73G to “1”, a large capacity use mode as shown in FIGS. 21B and 21C can be obtained.

  In this large capacity use mode, both the SRAM 401 and the SRAM 402 are used, and the capacity of the SRAM area is increased, so that the chip enable signal for accessing the SRAM is S1_CE # for the SRAM 401 and S2_CE # for the SRAM 402. Sometimes the memory map is as in the large capacity mode (1) of FIG.

  Further, if the use mode switching setting flash memory 73G is rewritten, it can be used again in the high reliability mode (the output of the switching setting flash memory 73G is set to "0").

  By changing the control circuit that decodes the chip enable signal to the SRAM, a memory map like the large capacity mode (2) of FIG.

  As described above, according to the first to tenth embodiments, the flash memory 30 (or 30A) and the SRAM 40 (or 40A) in which the address bus 27, the data bus 28, and part of the control signal lines 25 and 26 are shared are combined. In the semiconductor device 20 (or 20A) mounted in one package or configured on the same chip, the SRAM 40 using the write state machine 33 (or 33A) of the flash memory 30 (or 30A) as a test control circuit. The address signal, data signal, and control signal of (or 40A) are controlled, and data is written to and read from the flash memory 30 (or 30A) to the SRAM 40 (or 40A) to test the SRAM 40 (or 40A). be able to. The SRAM 40 (or 40A) can be tested simply by testing the flash memory 30 (or 30A) from an external tester. This allows testing with less effort and expense.

  Also, each time the power is turned on, a test of the semiconductor memory device (flash memory and SRAM) is performed by a nonvolatile semiconductor memory device having a test function, and the test result and switching setting of a plurality of semiconductor memory devices (SRAM) are nonvolatile. If the information is stored in a nonvolatile memory (flash memory) in the semiconductor memory device, use / non-use of the semiconductor memory device in the package can be switched based on this information. As a result, even if one of the SRAMs has a problem, it can be used by switching to the other SRAM, so that the semiconductor memory device of this device can be specified as a highly reliable device.

  Furthermore, it is possible to switch to a semiconductor memory device (SRAM) that can be used among a plurality of semiconductor memory devices (SRAM) according to a preset use time or use frequency.

  Furthermore, it can switch to the semiconductor memory device which can be used among several semiconductor memory devices (SRAM) according to a test result, use time, and use frequency.

  Furthermore, switching between a highly reliable device specification and a large capacity specification can be performed.

  As mentioned above, although this invention has been illustrated using preferable Embodiment 1-10 of this invention, this invention should not be limited and limited to this Embodiment 1-10. It is understood that the scope of the present invention should be interpreted only by the scope of the patent claims. It is understood that those skilled in the art can implement an equivalent range based on the description of the present invention and the common general technical knowledge from the description of specific preferred embodiments 1 to 10 of the present invention. Patents, patent applications, and documents cited in this specification should be incorporated by reference as if the contents themselves were specifically described in the present specification. Understood.

  The present invention is used in mobile devices such as personal computers and mobile phones, and a semiconductor device in which a plurality of semiconductor memory devices are mounted in one package or configured on the same chip, and a test method therefor, In the field of electronic information equipment such as personal computers and mobile phone devices used, by testing the other semiconductor memory device by controlling the address signal, data signal and control signal by the test control circuit of one semiconductor memory device By simply testing a semiconductor memory device with a built-in test control circuit from an external tester, other semiconductor memory devices can be tested, tester throughput can be improved, and an inexpensive tester can be used for post-assembly testing. It becomes possible. Furthermore, by providing a rewritable test sequence storage area in the nonvolatile semiconductor memory device, it is possible to perform a test according to the type, capacity, and memory array configuration of the semiconductor memory device to be tested. Further, the test sequence program can be changed even after the semiconductor memory device is mounted on a mobile phone or the like, and it is possible to cope with the deterioration of the semiconductor memory device due to a change with time.

  Further, in a device in which semiconductor memory devices of a plurality of chips are encapsulated in one package, one chip among the plurality of semiconductor memory devices is used, and the remaining semiconductor memory devices are left as spares.

  For example, each time the power is turned on, the semiconductor memory device is tested with a nonvolatile semiconductor memory device having a test function, and the test results and switching settings of a plurality of semiconductor memory devices are stored in the nonvolatile memory in the nonvolatile semiconductor memory device. In this case, the semiconductor memory device of the present device can be set as a highly reliable device by switching the use / non-use of the semiconductor memory device in the package based on this information.

  Furthermore, the semiconductor memory device to be used can be switched among a plurality of semiconductor memory devices according to the usage time or / and the number of times of use.

  Furthermore, a semiconductor memory device to be used can be switched among a plurality of semiconductor memory devices according to the test result and the usage time or / and the number of times of use.

  Furthermore, switching between a highly reliable device specification and a large capacity specification can be performed.

It is a perspective view which shows typically the example of a principal part structure of the semiconductor device which concerns on Embodiment 1 of this invention. FIG. 2 is a block diagram for explaining a connection state of a control signal, an address bus, and a data bus of a flash memory and an SRAM mounted on the semiconductor device of FIG. 1. FIG. 2 is a block diagram illustrating an internal configuration example of the flash memory of FIG. 1. 3 is a flowchart showing a data write sequence operation to the SRAM of FIG. 2. 3 is a flowchart showing a data read sequence operation from the SRAM of FIG. 2. It is a block diagram which shows the principal part structural example of the semiconductor device which concerns on Embodiment 2 of this invention. It is a block diagram which shows the internal structural example of the flash memory of the semiconductor device which concerns on Embodiment 3 of this invention. It is a block diagram which shows the internal structural example of the flash memory in the semiconductor device which concerns on Embodiment 4 of this invention. It is a signal waveform diagram for demonstrating the test example of AC characteristic about the test method of the semiconductor device which concerns on Embodiment 5 of this invention. It is a figure which shows an example of the output waveform which shows during a test and a non-defective test about the semiconductor device concerning Embodiment 6 of this invention. It is a figure which shows another example of the output waveform which shows the inside of a test, and a test good product about the semiconductor device which concerns on Embodiment 6 of this invention. It is a block diagram which shows the connection state of the control signal of the flash memory mounted in the semiconductor device which concerns on this Embodiment 7, and several SRAM, an address bus | bath, and a data bus, and its internal structure example. FIG. 13 is a circuit block diagram showing a connection relationship between the test result storage flash memory and the CE switching control circuit of FIG. 12 and two SRAMs; It is a block diagram which shows the connection state of the control signal of the flash memory mounted in the semiconductor device which concerns on the modification of this Embodiment 7, and several SRAM, an address bus, and a data bus, and its internal structure example. FIG. 20 is a block diagram illustrating a connection state of a control signal, an address bus and a data bus of a flash memory and a plurality of SRAMs mounted on a semiconductor device according to an eighth embodiment, and an example of an internal configuration thereof. FIG. 16 is a circuit block diagram showing a connection relationship between the switching setting flash memory and the CE switching control circuit of FIG. 15 and a plurality of SRAMs; FIG. 20 is a block diagram illustrating a connection state of a control signal, an address bus, and a data bus of a flash memory and a plurality of SRAMs mounted on a semiconductor device according to a ninth embodiment, and an internal configuration example thereof. FIG. 18 is a circuit block diagram showing a connection relationship between the test result storing flash memory, the switching setting flash memory and the CE switching control circuit of FIG. 17 and a plurality of SRAMs; It is a block diagram which shows the connection state of the control signal of the flash memory mounted in the semiconductor device which concerns on this Embodiment 10, and several SRAM, an address bus, and a data bus, and its internal structure example. FIG. 20 is a circuit block diagram illustrating a connection relationship between the test result storage flash memory, the switching setting flash memory, and the CE switching control circuit of FIG. 19 and a plurality of SRAMs. FIG. 20 is a schematic diagram for comparing memory maps in the high reliability use mode and the large capacity use mode in the semiconductor device of FIG. 19. It is a block diagram which shows the example of an internal structure of the conventional flash memory which is a non-volatile semiconductor memory device.

Explanation of symbols

20, 20A, 20D, 20D-1, 20E, 20F, 20G Semiconductor device 21 Address pad 22 Data pad 23 Control pad 24 Wire bonding 25, 25A, 26, 26A Control signal line 27, 27a, 38a Address bus 28, 28a, 38a Data bus 30, 30A, 30B, 30C, 30D, 30D-1, 30E, 30F, 30G Flash memory 32 Non-volatile memory array 33, 33A, 33B, 33C Write state machine 34 Address pad 35 Data pad 36a-36c Control pad 39a, 39b Control signal lines 40, 40A, 401, 402 SRAM
51 Test result information storage area 61 Test sequence information storage area 70D, 70D-1, 70E, 70F, 70G Memory selection control circuit 71 Test result storage flash memory 72, 72E, 72F, 72G CE switching control circuit 73 Switch setting flash Memory 71a, 71b, 73a, 73b, 73g Flash memory cell

Claims (25)

Multiple semiconductor memory devices are mounted in one package,
A semiconductor device in which a test control circuit for testing another semiconductor memory device is built in one of the plurality of semiconductor memory devices. An address bus, a data bus, and some control signal lines are provided in common among the plurality of semiconductor memory devices,
The one semiconductor memory device comprises a nonvolatile semiconductor memory device capable of controlling an address signal, a data signal, and a control signal by an internal control circuit,
The other semiconductor memory device includes a semiconductor memory device that can be controlled by a control circuit of the nonvolatile semiconductor memory device via the common address bus, the data bus, and the control signal line.
Using the control circuit of the nonvolatile semiconductor memory device as the test control circuit, the address signal, data signal, and control signal of the other semiconductor memory device are controlled, and data is stored from the memory unit of the nonvolatile semiconductor memory device. Reading and writing data to the other semiconductor memory device, reading data from the other semiconductor memory device and writing data to the storage unit of the nonvolatile semiconductor memory device, the other semiconductor memory device The semiconductor device according to claim 1, wherein the test can be performed. A plurality of semiconductor memory devices are configured on the same chip,
A semiconductor device in which a test control circuit for testing another semiconductor memory device is built in one of the plurality of semiconductor memory devices. The one semiconductor memory device comprises a nonvolatile semiconductor memory device capable of controlling an address signal, a data signal, and a control signal by an internal control circuit,
An address bus, a data bus, and a control signal line for controlling the other semiconductor memory device from the nonvolatile semiconductor memory device are provided between the nonvolatile semiconductor memory device and the other semiconductor memory device. ,
Using the control circuit of the nonvolatile semiconductor memory device as the test control circuit, the address signal, data signal, and control signal of the other semiconductor memory device are controlled, and data is stored from the memory unit of the nonvolatile semiconductor memory device. Reading and writing data to the other semiconductor memory device, reading data from the other semiconductor memory device and writing data to the storage unit of the nonvolatile semiconductor memory device, the other semiconductor memory device The semiconductor device according to claim 3, wherein the test can be performed.   3. The semiconductor device according to claim 2, wherein the nonvolatile semiconductor memory device is provided with an input / output pad capable of inputting / outputting an address signal, a data signal and a control signal to the outside.   An address pad, a data pad, and a control pad are provided as the input / output pads, a control signal line for a control signal that is connected to the control pad and can be controlled by the control circuit, and the address pad for sending address data to the outside An address bus for an address signal that is connected to the control circuit and can be controlled by the control circuit, and the data pad and the control circuit for taking data from the outside into the control circuit and sending the data from the control circuit to the outside 6. The semiconductor device according to claim 5, further comprising a data bus for connecting data signals.   3. The test result information storage area for storing and storing at least the test result information of the test result information and defect content information of the other semiconductor memory device is provided in the nonvolatile semiconductor memory device. Or the semiconductor device according to 4;   The semiconductor device according to claim 7, wherein the defect content information is fail address data.   8. The semiconductor device according to claim 2, 4 or 7, wherein the nonvolatile semiconductor memory device is provided with a rewritable test sequence information storage area capable of storing a test sequence program corresponding to a test content.   The semiconductor device according to claim 1, wherein an operating frequency of the test control circuit is changeable.   4. The semiconductor device according to claim 1, further comprising an output unit capable of outputting test completion information and test result information of the other semiconductor memory device.   5. The semiconductor memory device according to claim 2, further comprising: a first memory selection control circuit configured to switch to a semiconductor memory device to be used among a plurality of the other semiconductor memory devices in accordance with a pass / fail result of the test of the other semiconductor memory device. Semiconductor device.   The first memory selection control circuit is set in a test result storage flash memory capable of setting each test result information respectively corresponding to a plurality of the other semiconductor memory devices, and the test result storage flash memory. 13. The semiconductor device according to claim 12, further comprising: a chip enable signal switching control circuit that switches to any one of the other semiconductor memory devices according to the test result information.   The first memory selection control circuit has a test result storage flash memory capable of setting each test result information respectively corresponding to a plurality of the other semiconductor memory devices, and the test result storage flash memory 13. The semiconductor device according to claim 12, wherein the semiconductor device is switched to one of a plurality of other semiconductor memory devices according to the set test result information.   5. The semiconductor device according to claim 2, further comprising: a second memory selection control circuit that switches to a semiconductor memory device to be used in accordance with use frequency or / and usage time information among a plurality of the other semiconductor memory devices. .   The second memory selection control circuit includes a switching setting flash memory capable of setting the number of times of use and / or usage time information corresponding to each of the plurality of other semiconductor memory devices, and the switching setting flash memory. The semiconductor device according to claim 15, further comprising: a chip enable signal switching control circuit that switches to any one of the other semiconductor memory devices in accordance with the number of times of use and / or usage time information set in the above.   A third memory selection control circuit for switching to the semiconductor memory device to be used according to the result of the test of the other semiconductor memory device among the plurality of other semiconductor memory devices and the number of times of use or / and the time of use. The semiconductor device according to claim 2, further comprising:   The third memory selection control circuit includes a test result storage flash memory capable of setting each test result information corresponding to each of the plurality of other semiconductor memory devices, and each of the plurality of other semiconductor memory devices. Switching setting flash memory capable of setting the usage count and / or usage time information corresponding to each of the test results, the test result information set in the test result storage flash memory, and the usage set in the switching setting flash memory 18. The semiconductor device according to claim 17, further comprising a chip enable signal switching control circuit that switches to any one of the other semiconductor memory devices in accordance with the number of times and / or usage time information.   15. The test result storage flash memory has one or a plurality of bits of flash memory cells that can set test result information respectively corresponding to a plurality of the other semiconductor memory devices. The semiconductor device according to any one of 18 and 18.   The switching setting flash memory has one or a plurality of bits of flash memory cells each capable of setting use frequency and / or use time information corresponding to each of the plurality of other semiconductor memory devices. Item 19. A semiconductor device according to Item 16 or 18.   And further comprising a switching setting flash memory for switching between use of any one of the plurality of other semiconductor storage devices and use of a plurality or all of the semiconductor storage devices simultaneously. , 12, 15 and 17.   The switching setting flash memory has one or a plurality of bits of flash memory cells capable of setting information indicating whether it is any one semiconductor memory device or a plurality or all of the semiconductor memory devices. The semiconductor device according to claim 21.   19. The semiconductor device according to claim 13, wherein the chip enable signal switching control circuit is a circuit that decodes a value of a flash memory cell. The semiconductor device according to claim 1,
Using the test control circuit of the one semiconductor memory device, a data write and read test of the one semiconductor memory device is performed,
Using the test control circuit, the other semiconductor memory device is controlled, data is read from the memory section of the one semiconductor memory device, data is written to the other semiconductor memory device, and the other semiconductor memory device is read. A test method for a semiconductor device which performs data write and read tests of another semiconductor memory device by reading data from the memory device and writing data to a memory portion of the one semiconductor memory device.   An electronic information device for storing data in the semiconductor device according to claim 1.

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