JP4882633B2 - Memory test apparatus and memory test method - Google Patents

Description

  The present invention relates to a memory test apparatus and a memory test method, and more particularly to a memory test method in which a test signal can be simultaneously written to, read from, or deleted from a plurality of devices under test (DUT) in units of memory blocks.

  Conventionally, a disk memory is generally used as a large-capacity data storage means such as a computer. However, non-volatile semiconductor memory with high data reading speed increases storage capacity per unit area, reduces power consumption, and lowers its price, so it can be used not only for personal computers but also for mobile phones and digital cameras. Semiconductor memory has become widely used.

  As one type of semiconductor memory, flash memory (Flash-Memory) is known as a read-only memory capable of batch erasing and electrical erasing and writing. There are NAND cell type flash memory and NOR type flash memory as nonvolatile memory flash memories. Each of the flash memories has characteristics, but the former has a smaller circuit scale than the latter. It is possible to adapt to large capacity. Although the writing speed and the erasing speed are relatively high, the data access contacts are shared by a plurality of bits, and the occupied area per bit is reduced, so that random access to data is performed in units of blocks.

  In a NAND cell type flash memory, as a circuit configuration (memory cell configuration) necessary for storing 1-bit information, an N layer is formed so as to sandwich a P layer on a semiconductor substrate, and floating on the P layer. A gate is formed, and a control gate is further provided thereon. The floating gate is blocked by an insulator such as an oxide film. Data is stored by regarding the state where electrons are present in the floating gate as information “0” and the state where electrons are not present as information “1”. In writing data into the flash memory, the N layer is grounded, a drive voltage is applied to the control gate, and electrons are drawn into the floating gate by FN tunneling and injected. Data is erased by applying a driving voltage to the P layer and extracting electrons from the floating gate. Since the electrons in the floating gate are held by an insulator covering the floating gate, data can be held without supplying power.

FIG. 9 is a diagram showing an address configuration of a 2 Gbit NAND cell flash memory.
This 2G-bit (256M × 8-bit) flash memory is composed of 8-bit I / O with 8 data input / output bit lines in one chip on the wafer, and each bit has 2048 blocks. Each block is composed of 64 pages, and each page is composed of 2048-bit memory cells.

  As described above, since a bit line necessary for driving a memory cell is shared by a plurality of cells, data writing and reading are in units of pages, and erasing is a unit called a block in which 64 pages are combined. It is done in a lump. Therefore, the NAND cell type flash memory basically includes three operations: page write, page read, and block erase.

  For users who purchase such a flash memory from a semiconductor manufacturer and incorporate it into an electronic device, it is generally necessary to ensure the reliability of the product by performing a memory test. In that case, a conventional memory test apparatus is used. However, in the memory test of the flash memory, since writing / reading is performed in units of blocks, a block having at least one cell that cannot be written / read is defined as a defective block (hereinafter referred to as a bad block). For example, the flash memory shown in FIG. 9 is shipped as a non-defective memory even if there are 40 bad blocks in the 2048 blocks. This is because it is defined that the flash memory can be shipped as a non-defective product even if there are less than the specified number of bad blocks.

  In the NAND cell type flash memory, the bad block is set at the time of a manufacturer shipping test. Since most of the failure modes are failures in which “1” data changes to “0”, “0” data is written in the bad block and all remaining good blocks are set to “1” data. Therefore, a technique for managing bad blocks is necessary on the host side using the flash memory.

FIG. 10 is a diagram illustrating an example of a conventional memory test procedure using a bad block identification value.
First, the data in all the memory cells of the flash memory to be tested (hereinafter referred to as DUT) is read to the external memory, and the flash memory embedded system is checked while confirming the identification value indicating the bad block set by the manufacturer at the shipping test. The address table is created on the side and stored in the bad block file 100 (step S101). At this time, up to 40 bad blocks may exist.

  Next, predetermined test data is written in units of memory blocks, and read tests and erase tests are performed on the memory cells of all non-defective blocks (good blocks) except for blocks that are made bad blocks (steps S101 to S106). ). Note that “1” data is recorded in all the memory cells of pages 1 to 64 in the good block. The bad block file 100 also stores the pass / fail test results. Here, since block 2 is a bad block and all pages in the bad block are write / read prohibited, the test is not performed in step S103.

  As for the similar memory test, for example, in Patent Document 1, when a large number of flash memories are subjected to a shipping test at the same time, the memory in which the bad block is detected is interrupted and the test of the other memory is continued. Thus, an invention in which the test time is shortened is described.

Patent Document 2 describes an invention in which defective block address information is stored in a ROM and shipped, and a block management table is constructed by referring to this information. This is because when a plurality of memories are tested at the same time, an operation for verifying and reading the write result becomes unnecessary, and the test time can be shortened.
JP 2001-319493 A JP 2001-273798 A

  A conventional memory test apparatus has a plurality of slots so that a plurality of memories can be simultaneously connected to perform a write / read test and an erase test. Generally, it differs for each memory unit. That is, if the DUTs are not measured one by one as in the memory test shown in FIG. 10, the “0” data indicating the bad block is erased by the memory test on the user side. Therefore, on the user side, when a large amount of flash memory is accepted, there is a problem that the test time for testing the quality becomes long.

  In particular, since a large memory unit having a capacity of 2 Gbits requires a long test time, it has been desired to simultaneously test a plurality of memories having different bad block addresses.

  The present invention has been made in view of these points, and an object thereof is to provide a memory test apparatus and a memory test method capable of simultaneously executing a plurality of memory tests with simple address management.

  In the present invention, in order to solve the above problem, in a memory test apparatus capable of simultaneously writing, reading, or erasing test signals in units of memory blocks to a plurality of devices under test (DUT), First storage means for recording an identification value for identifying a bad block, and second storage means for recording logical product data obtained by performing a logical product operation with reference to the identification value for each DUT memory block unit And reading out the identification value from the first storage means to read out whether the bad block exists in the DUT and reading out the logical product data from the second storage means. A block determination unit that determines whether or not the bad block exists in any of the DUTs, and the bad determination unit In a memory block that is determined to have a lock, a memory test is performed in which only the DUT in which the bad block does not exist is sequentially selected by the device identification unit, and the test signal is written, read, and erased. A memory test apparatus is provided.

  In the present invention, when a memory test is performed on a plurality of devices under test (DUT), a bad block can be avoided and a test can be performed efficiently only on a good block.

  According to the present invention, since a plurality of flash memories can be measured simultaneously by simple address management, the test time can be shortened.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a system configuration diagram illustrating a memory test apparatus according to an embodiment.
This memory test apparatus includes a test processor 1 to which a plurality of devices under test (DUT) can be connected, and to which test signals can be simultaneously written, read, or erased in units of memory blocks. A block determination unit 2 and a DUT number identification unit 3 are connected to the test processor 1, and a first memory 4 in which an identification value for identifying a bad block of each DUT is recorded is connected to the DUT number identification unit 3. .

  The first memory 4 stores the maximum DUT values connectable to the memory test apparatus, for example, 32 block files 41, 42... Corresponding to DUT1 to DUT32. The DUT number identifying unit 3 configures a device identifying unit that reads each identification value from the first memory 4 and identifies the DUT in which the bad block exists.

  A second memory 5 is connected to the block determination unit 2, and the second memory 5 is logically ANDed with reference to the identification values in units of memory blocks DUT1 to DUT32 connected to the memory test apparatus. The calculated logical product data is recorded as an AND value file. The block determination unit 2 reads logical product data from the second memory 5 and determines whether or not a bad block exists in any one of the DUT 1 to DUT 32.

  Therefore, when it is determined by the block determination unit 2 that there is no bad block in the corresponding memory block of each DUT1 to DUT32, the test processor 1 writes and reads test signals to all connected DUT1 to DUT32. And an erasing test are performed simultaneously. For the memory block in which a bad block is determined to be present by the block determination unit 2, only the DUT that is not a bad block is selected by the DUT number identification unit 3, and the test processor 1 sequentially performs the test.

Next, the test sequence in the memory test apparatus described above will be described.
FIG. 2 is a flowchart illustrating a memory test method according to the embodiment. Here, the simultaneous measurement of two DUT1 and DUT2 is demonstrated as an example.

  Initially, the test processor 1 reads each memory cell of the connected DUT 1 and searches for the block number of the bad block contained therein (step S1). Next, a bad block file of DUT 1 is created and stored in the first memory 4 (step S2).

  Similarly, each memory cell of DUT2 is read, the block number of the bad block contained therein is searched (step S3), a bad block file of DUT2 is created and stored in the first memory 4 (step S3). S4).

  Next, with reference to the two bad block files stored in the first memory 4, the logical product of the identification values corresponding to the respective memory blocks is calculated (step S5). Then, AND value files of DUT1 and DUT2 are created and stored in the second memory 5 (step S6).

  In order to test each memory block by the test processor 1, the test block number B is designated. Here, the test is started from block number B = 1 (step S7). Next, the block determination unit 2 refers to the AND value file in the second memory 5 (step S8), and checks “AND value of DUT1 and DUT2” (hereinafter simply referred to as an AND value) (step S9).

  At this time, if the AND value is the logical value “1”, the process proceeds to step S10, and a simultaneous test is performed on the two DUT1 and DUT2. Although details of this test will be described later, a write test, a read test, and an erase test are sequentially executed, and good and bad of the memory block of the DUT are recorded as test results (step S11).

  Next, the test block number B is updated to B + 1 (step S12), and the process proceeds to the next step S13. Here, if the updated test block exceeds the maximum value Bmax, the test ends. If not, the process returns to step S8 to refer to the AND value file again. If the logical value of the AND value file is “0”, the process proceeds to step S14, where the DUT number identification unit 3 refers to the bad block file of DUT1 in the first memory 4 and checks the identification value (step S15).

  If the identification value is the logical value “1”, the DUT1 test is performed in step S16, and if the logical value is “0”, the test is not performed and the process proceeds to the next step S17. Here, the DUT number identification unit 3 refers to the bad block file of the DUT 2 in the first memory 4 to check the identification value (step S18). Similarly, if the identification value is the logical value “1”, the step In S19, the DUT2 test is performed. If the logical value is "0", the test is not performed.

  In this manner, by calling the bad block files of DUT 1 and DUT 2 in order from the first memory 4 and referring to the identification values corresponding to the respective block numbers, it is possible to perform tests on memory blocks other than the bad block. Those test results are recorded in the same manner as the results of the simultaneous test in step S11.

Next, cell data written in the memory cell of the bat block will be described.
FIG. 3 is a diagram showing the memory cell configuration of the unit block and the recorded contents of the cell data.
In the 2 Gbit NAND flash memory, as shown in FIG. 9 described above, the unit block is divided into 64 pages, and each page is composed of 2048 bit memory cells. In such a flash memory, a maximum of 40 bad blocks may exist. Therefore, a semiconductor device manufacturer writes “1” as bit data of each memory cell at the time of a shipping test. Thus, the bad block is set. That is, when the memory cells at address 0 of page 1 and address 1 of page 2 do not operate normally, they are shipped with bit data “0” written to them as shown in FIG. Thereby, a bad block can be specified on the user side of the flash memory.

  Therefore, it is sufficient to search the bad block number by reading the cell data from all the blocks on the user side, and independently perform the writing and reading tests in the other blocks. FIG. 3B shows the recorded contents of the cell data in the non-defective block. In this case, “1” data is written in all pages 1 to 64.

FIG. 4 is a diagram showing a procedure for creating an AND value file for simultaneous test measurement of two DUTs.
By reading the cell data of the corresponding memory block from the two DUTs 1 and 2 and checking whether the bit data “0” is included, the identification values of the corresponding block files 41 and 42 are determined. ing. Here, a logical value “0” is written as identification value data in the case of a bad block, and a logical value “1” is written in the case of a good block. In FIG. 4, block numbers up to 5 are shown, and the identification values of the subsequent block numbers are omitted.

  Next, with reference to the block files 41 and 42 of DUT1 and DUT2, AND data of identification values is calculated for each block number 1 to 5, and an AND value is determined. Thus, the AND value file 51 of DUT1 and DUT2 is generated in advance and stored in the second memory 5 shown in FIG. In the AND value file 51, the logical value “1” is defined as having no bad block, and the logical value “0” is defined as having a bad block.

  That is, when the second block of DUT1 is a bad block and the fourth block of DUT2 is a bad block, logical value “0” is recorded as an AND value in block numbers 2 and 4 in AND value file 51, and otherwise The AND value corresponding to the block number is the logical value “1”. Here, the case where there are two DUTs has been described, but for all the DUTs connected to the memory test apparatus, AND values are determined by referring to the respective identification values in units of memory blocks, and the AND value file 51 is stored. Need to create.

  For all of the flash memories to be tested, when there is no bad block, the AND value becomes a logical value “1”. Therefore, in the memory test apparatus shown in FIG. 1, the DUT 1 to DUT 32 connected thereto are simultaneously connected. Write and read tests can be performed. However, when a bad block exists in any one of DUT1 to DUT32, the AND value becomes a logical value “0”. Then, the DUT except for the DUT in which the bad block exists is sequentially selected, and the write / read test is performed.

Next, a memory test procedure using the identification value of the AND value file 51 will be described.
FIG. 5 is a diagram illustrating an example of a test procedure using an AND value file.
In the memory test, logical product data is read from the AND value file 51 of the second memory 5, and if the logical value is “1”, the simultaneous test of DUT1 and DUT2 is performed. Further, when the logical value is “0” as in the test of block 2 or block 4, identification is made by referring to the block files 41 and 42 of the individual DUT 1 and DUT 2 from the first memory 4. Only for the DUT having the value “1”, the test signal is written and read one by one, and the memory test is performed.

FIG. 6 is a diagram illustrating a hardware configuration of the memory test apparatus according to the embodiment.
N DUTs are connected to the test head unit 11. A test signal is simultaneously supplied to each DUT from the driver unit 12, and the same test pattern is written in a predetermined memory block of each DUT. The driver unit 12 is connected to a test pattern generating unit 13 that generates various test patterns.

  A test pattern generation unit 13 is connected to the comparator unit 14, and the test patterns written in the respective DUTs are simultaneously read in the subsequent read test. Therefore, the comparator unit 14 can specify the bad block of each DUT. Note that a test item setting file 15 is connected to the test pattern generator 13.

  The bad block file generation unit 16 is connected to the test pattern generation unit 13 and generates bad block files 1 to n of n DUTs based on the result of the memory test for writing, reading, and erasing test signals. . The memory 17 in which the generated n bad block files are stored corresponds to the first memory 4 in FIG.

  The AND value file generator 18 is connected to the memory 17 and generates an AND value file 51 as shown in FIG. The generated AND value file 51 is stored in the second memory 5 as shown in FIG.

  The DUT selection unit 19 is connected to the test head unit 11 and selects a DUT to be tested among the DUTs 1 to n connected to the test head unit 11. The DUT selection unit 19 is connected to the memory 17 and the AND value file generation unit 18 and is further managed by the block number management unit 20. As a result, if all of the DUTs 1 to n are non-defective in the designated memory block, a test signal is written, read, or erased at the same time in memory block units. Then, in the memory block determined to have a bad block, only a DUT having no bad block is sequentially selected, and a memory test for writing, reading, and erasing a test signal is performed.

Next, cell data write and read operations performed on a DUT in memory block units will be described.
FIG. 7 is a waveform diagram showing timings of a write operation and a read operation of the NAND cell type flash memory.

  In FIG. 5A, data writing is instructed as an input / output control signal (I / O signal) at the timing when the first command control signal (CC signal) is supplied to the selected DUT. Next, address data such as the block number and page number of the memory block of the DUT is read at the timing of the address control signal (AC signal). Thereafter, data 1 to N (for example, N = 2048) supplied in synchronization with the write control signal (WC signal) are serially input from the I / O terminal. Finally, a write end command is input. During this read operation, the read control signal (RC signal) is fixed at a high level.

  In FIG. 7B, the selected DUT is instructed to read data as an input / output control signal (I / O signal) at the timing when the first command control signal (CC signal) is supplied. Next, address data such as the block number and page number of the memory block of the DUT is read at the timing of the address control signal (AC signal), and a read start command is input. Thereafter, the cell data 1 to N (for example, N = 2048) are serially output from the I / O terminal from the designated page in synchronization with the read control signal (RC signal).

Next, the effect of the simultaneous measurement test by the memory test apparatus described above will be described.
FIG. 8 is a diagram illustrating a test time in the standard operation mode in the memory test method according to the embodiment.

  The first step S21 is a bad block read step. In this step S21, assuming that the read / write time per memory cell is 60 ns, when this test cycle is executed in a 2 Gbit (2048 blocks × 64 pages × 2048 bits) flash memory, it is 16 (seconds).

  In the next step S22, the write operation of the test signal (test pattern (table)) of the table pattern is executed. Here, the test cycle is 16 (seconds) as in step S21. However, since 700 (μs) is required for the program waiting time for each page unit, a 2 Gbit (2048 blocks × 64 pages) flash is required. The program waiting time of the memory is 91 (seconds), which is 107 (seconds) as a whole.

In the next step S23, a test pattern (table) reading operation is performed. Here, the test cycle is 16 (seconds) as in step S21.
In the next step S24, the data erasing operation of each memory cell is executed. Here, since the test cycle is erased in batches in units of 180 (ns), it is 16 (seconds) in a 2 Gbit (2048 block) flash memory, but the erase waiting time is 3 (1) per block. ms), so that the total is 22 (seconds).

  The above steps S22 to S24 are test cycles based on a test pattern (table) in which “1” data is written, a write / read test is performed, and a function test of the memory cell is performed. In addition to the writing of the logical value “1”, a test cycle using a test pattern (back) corresponding to the test signal of the back pattern is also performed.

  That is, in the test cycle by the test pattern (back side) in which “0” data is written in the memory cell and the write and read tests are performed, the test pattern (back side) write operation in step S25 is 107 (seconds), and the test in step S26 The pattern (back) reading operation is 16 (seconds), and the data erasing operation of each memory cell in step S27 is 22 (seconds). Therefore, in the conventional memory test apparatus, in the case where the electrical test of the flash memory is performed even though the test for a plurality of DUTs can be performed at the same time, the writing is performed because the bad block exists. / The readout test was performed for each DUT for about 5 minutes (306 seconds).

  On the other hand, as in the memory test apparatus described above, if, for example, two DUTs are simultaneously tested and no bad block exists, one test can be performed in 5 minutes. Therefore, compared with the case where each DUT is performed separately, a test time of 1/2 is simply required.

  Further, as shown in FIG. 1, when testing each of 32 DUTs 1 to 32, even if 40 bad blocks exist in different numbers of memory blocks, bad DUTs 1 to 32 There are quite a few memory blocks that are not blocks. That is, in 1280 blocks of 2048 blocks, each DUT 1 to 32 is sequentially selected and a memory test is performed, but the remaining 768 memory blocks can be tested with 32 DUTs at the same time. The efficiency of the memory test can be improved.

  As described above, the test time of one 2 Gbit flash memory is about 5 minutes, and can be greatly shortened by simultaneously performing measurement tests on a plurality of DUTs.

1 is a system configuration diagram showing a memory test apparatus according to an embodiment. It is a flowchart which shows the memory test method which concerns on embodiment. It is a figure which shows the memory cell structure of a unit block, and the recording content of cell data. It is a figure which shows the preparation procedure of the AND value file for carrying out simultaneous test measurement of two DUT. It is a figure which shows an example of the test procedure using an AND value file. It is a figure which shows the hardware constitutions of the memory test apparatus which concerns on embodiment. FIG. 5 is a waveform diagram showing timings of a write operation and a read operation of a NAND cell flash memory. It is a figure which shows the test time of the standard operation mode in the memory test method which concerns on embodiment. FIG. 3 is a diagram showing an address configuration of a 2 Gbit NAND cell flash memory. It is a figure which shows an example of the conventional memory test procedure using the identification value of a bad block.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Test processor 2 Block determination part 3 DUT number identification part 4 1st memory 5 2nd memory 11 Test head part 12 Driver part 13 Test pattern generation part 14 Comparator part 15 Test item setting file 16 Bad block file generation part 17 Memory 18 AND Value file generator 19 DUT selector 20 Block number manager 41, 42 ... Block file

Claims (8)

In a memory test apparatus capable of simultaneously writing, reading, or erasing test signals in units of memory blocks to a plurality of devices under test (DUT)
First storage means for recording an identification value for identifying a bad block of each DUT;
Second storage means for recording logical product data obtained by performing a logical product operation with reference to the identification value in units of memory blocks of each DUT;
A device identification unit that reads out the identification value from the first storage unit and identifies whether or not the bad block exists in the DUT;
A block determination unit that reads the logical product data from the second storage unit and determines whether or not the bad block exists in any one of the DUTs;
With
In the memory block in which the bad block is determined to be present by the block determination unit, only the DUT in which the bad block does not exist is sequentially selected by the device identification unit, and the test signal is written, read, and erased A memory test apparatus for performing a test.   2. The memory test apparatus according to claim 1, wherein the DUT is a semiconductor memory device in which cell data is written, read, or erased in units of memory blocks.   2. The identification value in the first storage means is updated if there is a memory block in the DUT in which written cell data and read cell data do not match. Memory test equipment.   A means for retrieving the bad block from each of the DUTs in units of memory blocks and writing a logical signal “0” to the bad block as the identification value in the first storage means is provided. Item 1. A memory test apparatus according to Item 1. In a memory test method capable of simultaneously writing, reading, or erasing test signals in units of memory blocks to a plurality of devices under test (DUT),
A first step of searching for a bad block of each DUT and recording its identification value;
A second step of referring to the identification value and performing a logical product operation on a memory block basis of each DUT and recording logical product data;
A third step of determining whether or not the bad block exists for each corresponding memory block of each DUT based on the logical product data recorded in the second step;
For the memory block determined to have a bad block in the third step, the DUT in which the bad block does not exist is sequentially selected based on the identification value recorded in the first step, A fourth step of simultaneously writing, reading, and erasing the test signal for each of the DUTs for a memory block determined to have no bad block in the third step;
And a memory test method, respectively.   6. The memory test method according to claim 5, wherein the DUT is a semiconductor memory device in which cell data is written, read or erased in units of memory blocks.   6. The memory test method according to claim 5, wherein if there is a memory block in which the written cell data does not match the read cell data in the DUT, the identification value is updated.   6. The memory test method according to claim 5, wherein a logic signal "0" is written as an identification value recorded in the first step.

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