JP2006304430A - Power circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power circuit which can use a plurality of DSPs in combination so as to individually control a plurality of switching elements. <P>SOLUTION: This power unit is provided with a power block which includes a plurality of power stages, a first group of detecting circuits which detect the current, etc. on a first power stage, a second group of detecting circuits which detect the current, etc. on a second power stage, a first DSP71 which controls the first power stage, based on the detection data of the detecting circuits in the first group, a second DSP72 which controls the second power stage, based on the detection data of the detecting circuits in the second group, and a communication circuit 73 which is provided to perform communication between the first DSP and the second DSP. The second DSP determines the load state, based on the detection data output from at least one of the detecting circuits in the second group, and sends the mode information corresponding to the load state to the first DSP. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention generally relates to a power supply circuit used in an electronic apparatus, and more particularly to a power supply circuit that performs step-up or step-down or generates an alternating voltage by a switching operation.

  In recent years, with the reduction in size and weight of electronic devices, switching power supplies that step up or step down by switching operations and inverters that generate AC voltage by switching operations are widely used as power sources that are small and light and can efficiently extract power. in use. In a power supply that performs such a switching operation, high-speed and high-precision control is required for the switching element, and control using a digital circuit is being considered instead of control using a conventional analog circuit.

  Although there is a demerit that the frequency band of the control signal is limited or a quantization error occurs by using the digital circuit, by integrating the control circuit as a DSP (digital signal processor), It is easy to downsize the control circuit. Also, since the control circuit can be generalized by generalizing the control algorithm, the same control circuit can be combined with a plurality of types of switching elements having different capabilities according to various requirements for the power supply circuit. It becomes easy. Further, when a plurality of switching elements are used in the power supply circuit, a combination of a plurality of DSPs may be considered in order to individually control each switching element.

  As a related technique, Japanese Patent Application Laid-Open No. H10-228667 discloses a relatively small method for rotating an image by a desired angle by manipulating the reading order of image data when reading two-dimensional image data stored in a frame memory. An image rotation control method is disclosed in which a frame memory having a storage capacity can be used, and image writing can be performed without causing congestion in data writing and reading to the frame memory.

In this control method, in parallel with the reading of the two-dimensional image data from the frame memory by the second DSP, a writing order is set in the same manner as the reading order, and new two-dimensional image data is stored in the frame memory by the first DSP. Write. The image rotation angle by the read order operation is stored in the data memory, and then when the new two-dimensional image data is read, the CPU calculates the desired image rotation angle and the rotation angle stored in the data memory. The sum is obtained, and the image rotation angle by the image data reading order operation is set to the sum angle. However, Patent Document 1 does not disclose that a plurality of DSPs are used in combination in order to control a power supply circuit using a plurality of switching elements.
Japanese Patent Laid-Open No. 5-128246 (first page, FIG. 1)

  Therefore, in view of the above points, the present invention can use a combination of a plurality of DSPs in order to individually control each switching element when a plurality of switching elements are used in a power supply circuit. An object of the present invention is to provide a power supply circuit that can be used.

  In order to solve the above problems, a power supply circuit according to a first aspect of the present invention includes a power block including a plurality of power stages that perform step-up or step-down or generate an alternating voltage from a direct-current voltage, and a first power stage. A first group of detection circuits that detect current / voltage or temperature at a predetermined location and A / D-convert the detection signal, and a predetermined location of a second power stage that is positioned after the first power stage. A second group of detection circuits that detect current or voltage or temperature and A / D-convert the detection signal, and a digital signal processing based on the detection data output from the first group of detection circuits allows the first The second power is obtained by performing digital signal processing based on detection data output from the first digital signal processor for controlling the power stage and the second group of detection circuits. A second digital signal processor comprising: a second digital signal processor for controlling the stage; and a communication line provided for communicating between the first digital signal processor and the second digital signal processor. Determines a load state based on detection data output from at least one of the second group of detection circuits, and transmits mode information corresponding to the load state to the first digital signal processor.

  A power supply circuit according to a second aspect of the present invention includes a power block including a plurality of power stages that perform step-up or step-down using a switching element or generate an AC voltage from a DC voltage, and a first power stage. A first group of detection circuits that detect current / voltage / temperature at a predetermined location and A / D-convert the detection signal; and a detection signal by detecting current / voltage / temperature at a predetermined location of the second power stage. A second group of detection circuits for A / D-converting the signal and a digital signal processing based on detection data output from the first group of detection circuits to drive the switching element of the first power stage, and A first digital signal processor for generating a first synchronization signal synchronized with a pulse current generated by a switching operation in one power stage; The switching element of the second power stage is driven by performing digital signal processing based on the detection data output from the two groups of detection circuits, and is synchronized with the pulse current generated by the switching operation in the second power stage. A second digital signal processor for generating a second synchronization signal; a communication line provided for communicating between the first digital signal processor and the second digital signal processor; And the second digital signal processor transmit the first and second synchronization signals to each other, so that the first digital signal processor determines the detection result of the first group of detection circuits based on the second synchronization signal. Period masking and / or a second digital signal processor based on the first synchronization signal Out for a predetermined period of time masking the detection result of the circuit.

  According to the first aspect of the present invention, the second digital signal processor determines a load state based on detection data output from at least one of the second group of detection circuits, and responds to the load state. By transmitting the mode information to be transmitted to the first digital signal processor, a plurality of digital signal processors can perform smooth interlocking upon occurrence of an abnormality, switching to a standby mode, characteristic evaluation, or trial operation. Here, the load state means what state the load of the power supply circuit is in, including a state where the load is heavy or light, a state where the load is not connected, and the like.

  According to the second aspect of the present invention, the first and second digital signal processors transmit the first and second synchronization signals to each other, and the first digital signal processor converts the second synchronization signal to the second synchronization signal. Based on the detection result of the first group of detection circuits for a predetermined period, and / or the second digital signal processor determines the detection result of the second group of detection circuits based on the first synchronization signal for a predetermined period. By masking, a plurality of digital signal processors can perform their switching control safely and reliably.

The best mode for carrying out the present invention will be described below in detail with reference to the drawings. The same constituent elements are denoted by the same reference numerals, and the description thereof is omitted.
FIG. 1 is a diagram showing a configuration of a power supply circuit according to the first embodiment of the present invention. The power supply circuit includes a power block including a plurality of power stages (in FIG. 1, a PFC stage 20 and a DC / DC converter stage 40) that perform step-up or step-down or generate an AC voltage from a DC voltage, and a PFC stage. A first group of detection circuits 61 to 63 that detect current or voltage or temperature at 20 predetermined locations and A / D-convert detection signals; and current or voltage or temperature at predetermined locations of the DC / DC converter stage 40. And a second group of detection circuits 64 to 66 for A / D converting the detection signal, and a control block 70 for controlling the power block.

  The power block converts the AC voltage supplied from the input terminals 1 and 2 into a DC voltage, and combines the waveform and phase of the input voltage and input current to improve the power factor PFC (power factor controller) Control) stage 20, capacitor 30 that smoothes the voltage output from PFC stage 20, DC / DC converter stage 40 that outputs a DC voltage by stepping up or down the DC voltage smoothed by capacitor 30, DC / DC And a capacitor 50 for smoothing the voltage output from the DC converter stage 40. The capacitor 50 is connected to DC voltage output terminals 3 and 4.

  The PFC stage 20 is switched based on a drive signal A, for example, a rectifier circuit 10 configured by a diode bridge, an inductor 21, a switching element 22 that switches a voltage supplied from the rectifier circuit 10 through the inductor 21, and the like. A driver 23 for driving the element 22 and a diode 24 for rectifying an AC voltage generated by switching are included. As the switching element, a relay or various actuators can be used in addition to a MOSFET that performs a switching operation between a drain and a source when a drive signal is applied to the gate. The capacitor 30 smoothes the voltage rectified by the diode 24 and generates a DC voltage.

  The first group of detection circuits includes a current detection circuit 61, a voltage detection circuit 62, and a temperature sensor 63. The current detection circuit 61 detects the input current of the rectifier circuit 10 and outputs detection data by A / D converting the detection signal. The voltage detection circuit 62 detects the voltage rectified by the rectification circuit 10, and outputs detection data by A / D converting the detection signal. The temperature sensor 63 detects the temperature of the PFC stage 20, and outputs detection data by A / D converting the detection signal. Note that the type and number of detection circuits can be changed as needed.

  The DC / DC converter stage 40 is connected in series to a transformer 41 that boosts or steps down a primary-side rectangular wave voltage generated by switching and outputs the voltage to the secondary side, and a primary winding of the transformer. Switching element 42 for passing current to the primary winding of the transformer, a driver 43 for driving switching element 42 based on drive signal B, and an AC voltage generated in the secondary winding of the transformer in half. And a diode 44 for wave rectification. The capacitor 50 smoothes the voltage rectified by the diode 44 and generates a DC voltage.

  In the flyback type DC / DC converter stage 40 as shown in FIG. 1, the primary side winding and the secondary side winding of the transformer 41 have a reverse polarity relationship, and the switching element 42 is turned on. During the operation, the primary side current of the transformer 41 increases, but since the secondary side of the transformer 41 is reverse-biased by the diode 44, the secondary side current does not flow. The transformer 41 stores energy in the core when the switching element 42 is on.

  Next, when the switching element 42 is turned off, the magnetic field tries to maintain the current, so that the voltage polarity of the transformer 41 is reversed and a current flows on the secondary side of the transformer 41. The secondary current of the transformer 41 is charged in the capacitor 50 via the diode 44 connected in series, thereby generating a DC voltage between the output terminals 3 and 4.

  The second group of detection circuits includes a current detection circuit 64, a voltage detection circuit 65, and a temperature sensor 66. The current detection circuit 64 detects the current flowing through the primary side winding of the transformer 41, A / D converts the detection signal, and outputs detection data. The voltage detection circuit 65 detects the voltage smoothed by the capacitor 50, and outputs detection data by A / D converting the detection signal. The temperature sensor 63 detects the temperature of the DC / DC converter stage 40 and A / D converts the detection signal to output detection data. Note that the type and number of detection circuits can be changed as needed.

  In order to improve the response to a dynamically changing load, high gain feedback control is required. However, in the conventional analog power supply circuit, the amplifier circuit becomes complicated and the operation is difficult to realize this. There was a risk of instability. On the other hand, by using the DSP, the feedback control is realized by high-speed arithmetic processing, so that the responsiveness is improved and the amplifier circuit is unnecessary, and the stability is also improved. In addition, the control in the conventional analog power supply circuit is either performed based on the detected voltage or based on the detected current, but the power supply circuit is based on the detected power by using digital signal processing. It is also possible to perform control.

  In the present embodiment, a plurality of switching elements 22 provided in the PFC stage 20 and a switching element 42 provided in the DC / DC converter stage 40 are individually controlled (PWM control, PFM control, etc.). The DSP is provided exclusively. On the other hand, when an abnormality occurs or switches to the standby mode, the DSPs communicate with each other so that smooth linkage is performed.

  The control block 70 includes a first DSP 71 that controls the PFC stage 20 by performing digital signal processing based on detection data output from the first group of detection circuits 61 to 63, and a second group of detection circuits 64 to 64. A second DSP 72 that controls the DC / DC converter stage 40 by performing digital signal processing based on the detection data output from 66, and a communication line 73 provided for communication between the DSP 71 and the DSP 72. Including. As the communication line 73, a line for the first DSP 71 to transmit a signal to the second DSP 72 and a line for the first DSP 71 to receive a signal from the second DSP 72 are provided separately. Alternatively, a general-purpose bus line may be used.

  FIG. 2 is a diagram illustrating a state in which the components of the control block are mounted on the substrate. As shown in FIG. 2, the circuit board 78 has a first DSP 71 that generates a drive signal A for driving the switching element 22 of the PFC stage 20 shown in FIG. 1 and detection of the first group in the PFC stage 20. An A / D converter portion 74 of the circuits 61 to 63, an output circuit 75 that outputs a drive signal A to the driver 23 of the PFC stage 20, and a drive signal B for driving the switching element 42 of the DC / DC converter stage 40. The drive signal B is output to the second DSP 72 that generates the signal, the A / D converter portion 76 of the second group of detection circuits 64 to 66 in the DC / DC converter stage 40, and the driver 43 of the DC / DC converter stage 40. An output circuit 77 is mounted.

  The DSPs 71 and 72 are molded into individual packages and can be exchanged independently. The flash memories 71a and 72a as nonvolatile storage circuits storing software (control program) and various threshold values, and data RAMs 71b and 72b for temporary storage are incorporated. The DSPs 71 and 72 are connected to the 5V and 3.3V power supply potential lines and to the 0V reference potential (ground potential) line. Alternatively, different power supply potentials may be supplied to the first DSP 71 and the second DSP 72.

  Blank signals are supplied from the DSPs 71 and 72 to the A / D converters 74 and 76, respectively, in order to mute the analog detection signals input to the A / D converters 74 and 76 when switching noise occurs. The DSPs 71 and 72 are connected to an external control terminal used for controlling the DSPs 71 and 72 from the outside.

  The second DSP 72 that controls the DC / DC converter stage 40 corresponds to a load to which the power supply circuit is connected based on detection data output from at least one of the second group of detection circuits 64 to 66. The operation state of the DC / DC converter stage 40 is determined as one of the normal mode and the standby mode, or the operation state of the DC / DC converter stage 40 is determined. And any one of the normal mode and the stop mode, or any one of the normal mode and the test mode, and mode information (mode switching signal and / or mode) corresponding to the load state. Switching information) is transmitted to the first DSP 71.

  Specifically, the second DSP 72 uses a threshold value stored in the flash memory 72a as a value represented by detection data output from at least one of the second group of detection circuits 64-66. The load state is determined by comparison.

  Further, the first DSP 71 sets the operation mode of the PFC stage 20 to one of the normal mode and the standby mode, or the normal mode and the stop mode according to the mode information transmitted from the second DSP 72. Or any one of the normal mode and the test mode. Here, when shifting from one mode to another mode, the control program stored in the flash memory 71a of the first DSP 71 is the operation mode of the PFC stage 20 according to the mode information transmitted from the second DSP 72. The first DSP 71 includes a procedure for changing the information, a procedure for performing an operation for controlling the PFC stage 20 in the newly set operation mode, and a procedure for storing information on the previous setting state and the new setting state. The sequence operation is performed by causing the CPU to execute the operation.

  Incidentally, the switching operation in the power stage is accompanied by generation of switching noise. When multiple DSPs perform switching control of multiple power stages in parallel, noise generated by the switching operation in one power stage adversely affects the analog detection signal in the other power stage, and normal switching control can be performed. There is a risk of disappearing.

  Therefore, in the present embodiment, each of the DSPs 71 and 72 generates a synchronization signal (pulse signal) associated with the switching operation and transmits it to each other, thereby A / D conversion connected to the other DSP. A blank signal is supplied to the units 76 and 74, and the detection result in the other power stage is masked (or blanked or inhibited).

  That is, when the first DSP 71 drives the switching element 22 of the PFC stage 20 by performing digital signal processing based on detection data output from the first group of detection circuits 61 to 63, the PFC stage 20 The first blank signal is generated in synchronization with the pulse current generated by the switching operation at.

  Further, when the second DSP 72 drives the switching element 42 of the DC / DC converter stage 40 by performing digital signal processing based on the detection data output from the detection circuits 64 to 66 of the second group, A second blank signal synchronized with the pulse current generated by the switching operation in the DC / DC converter stage 40 is generated.

  Further, the DSPs 71 and 72 transmit the first and second blank signals to each other. The first DSP 71 supplies the second blank signal received from the DSP 72 to the A / D converter 74, thereby muting the analog detection signal input to the A / D converter 74. As a result, the detection results of the first group of detection circuits 61 to 63 are masked for a predetermined period based on the second blank signal. In addition to or instead of this, the second DSP 72 supplies the first blank signal received from the DSP 71 to the A / D converter 76, whereby the analog detection signal input to the A / D converter 76. May be muted. As a result, the detection results of the second group of detection circuits 64 to 66 are masked for a predetermined period based on the first blank signal. Thereby, when a plurality of DSPs perform switching control of a plurality of power stages in parallel, each switching control can be performed safely and reliably.

  Here, the first DSP 71 generates a first drive signal having the first frequency and supplies it to the switching element 22 of the PFC stage 20, and the second DSP 72 has the second frequency having the second frequency. When the drive signal is generated and supplied to the switching element 42 of the DC / DC converter stage 40, the ratio of these frequencies is set so that the first frequency is an integral multiple of the second frequency, and the DSPs 71 and 72 are used. However, you may make it produce | generate the 1st and 2nd blank signal each synchronized with the 1st drive signal. In that case, the noise generation timing can be made uniform in the PFC stage 20 and the DC / DC converter stage 40, and the frequencies of the first and second blank signals can be unified.

Next, a first operation example of the power supply circuit shown in FIG. 1 will be described with reference to FIGS. FIG. 3 is a flowchart showing a first operation example of the power supply circuit shown in FIG.
As shown in FIG. 3, first, in step S11, the second DSP 72 compares the value represented by the detection data of the DC / DC converter stage 40 with the first threshold value and is represented by the detection data. Whether the value exceeds the first threshold value. When it is determined that the value represented by the detection data does not exceed the first threshold value, step S11 is repeated, and the value represented by the detection data exceeds the first threshold value. If it is determined, the process proceeds to step S12.

  In step S <b> 12, the second DSP 72 stops operation of the DC / DC converter stage 40 and transmits mode information to the first DSP 71. In response to this, in step S13, the first DSP 71 activates a control program stored in advance in the flash memory 71a.

  In step S <b> 14, the second DSP 72 compares the value represented by the detection data with the second threshold value, and determines whether or not it is only necessary to stop the operation of the DC / DC converter stage 40. If it is determined that it is only necessary to stop the operation of the DC / DC converter stage 40, the process proceeds to step S15, and if it is determined that the operation stop of the DC / DC converter stage 40 is not sufficient. The process proceeds to step S17.

  In step S <b> 15, the second DSP 72 transmits mode information indicating continuation of operation of the PFC stage 20 to the first DSP 71. The first DSP 71 executing the control program continues the operation of the PFC stage 20 according to the mode information. Further, in step S16, the second DSP 72 compares the value represented by the detection data (for example, temperature data) with the third threshold value according to the command supplied to the external control terminal. Then, it is determined whether or not the operation of the DC / DC converter stage 40 is resumed.

  If it is determined that the operation of the DC / DC converter stage 40 is to be resumed, the processing returns to step S11 after the second DSP 72 resumes the operation of the DC / DC converter stage 40 in step S17. On the other hand, if it is determined not to resume the DC / DC converter stage 40, step S16 is repeated.

  If it is determined in step S14 that the operation stop of the DC / DC converter stage 40 is not sufficient, the second DSP 72 transmits mode information indicating the operation stop of the PFC stage 20 to the first DSP 71. . The first DSP 71 executing the control program performs a sequence operation for stopping the operation of the PFC stage 20 according to the mode information (step S18). As a result, in step S19, the first DSP 71 stops the operation of the PFC stage 20 after the second DSP 72.

Next, a second operation example of the power supply circuit shown in FIG. 1 will be described with reference to FIGS. FIG. 4 is a flowchart showing a second operation example of the power supply circuit shown in FIG.
As shown in FIG. 4, first, in step S21, the first DSP 71 compares the value represented by the detection data of the PFC stage 20 with the fourth threshold value, and the value represented by the detection data is determined. It is determined whether or not the fourth threshold value is exceeded. If it is determined that the value represented by the detection data does not exceed the fourth threshold value, step S21 is repeated, and the value represented by the detection data exceeds the fourth threshold value. If it is determined, the process proceeds to step S22.

  If the value represented by the detection data exceeds the fourth threshold value, it is unclear whether it is caused by an abnormality in the power supply circuit or spike noise or the like superimposed on the AC line from the outside. Therefore, the warning operation of the power supply circuit is continued for a predetermined period without immediately stopping the operation of the power supply circuit. At this time, in order to make an emergency copy of the control information of the first DSP 71 to the second DSP 72, the first DSP 71 transmits the control information of the first DSP 71 to the second DSP 72 (step S22). The first DSP 71 continues the warning operation based on the latest data instead of the detection data (abnormal data) exceeding the first threshold value in a predetermined period (step S23).

  In step S24, the first DSP 71 determines whether or not the abnormal state continues. If it is determined that the abnormal state is still continuing, the process proceeds to step S25. If it is determined that the abnormal state has ended, the process proceeds to step S28.

  In step S25, the first DSP 71 issues a warning and shifts the operation of the PFC stage 20 to the alarm operation. In step S <b> 26, the first DSP 71 compares the value represented by the detection data with the fifth threshold value and determines whether to resume normal operation of the PFC stage 20. If it is determined to resume normal operation of the PFC stage 20, the process proceeds to step S27. If it is determined not to resume normal operation of the PFC stage 20, step S26 is repeated.

  In step S27, based on the request of the first DSP 71, the second DSP 72 returns the control information of the first DSP 71 to the first DSP 71. Further, in step S28, the first DSP 71 resumes normal operation of the PFC stage 20. Thereafter, the process returns to step S21.

  If it is determined in step S24 that the abnormal state has ended, in step S29, the second DSP 72 returns the control information of the first DSP 71 to the first DSP 71 based on the request of the first DSP 71. . Further, in step S30, the first DSP 71 resets the warning operation of the PFC stage 20 and resumes the normal operation. Thereafter, the process returns to step S21.

Next, a second embodiment of the present invention will be described.
FIG. 5 is a diagram showing a configuration of a power supply circuit according to the second embodiment of the present invention. The power supply circuit includes a power block including a plurality of power stages (in FIG. 1, a PFC stage 20 and an inverter stage 80) that perform step-up or step-down or generate an AC voltage from a DC voltage, and a predetermined PFC stage 20 The first group of detection circuits 61 to 63 that detect the current, voltage, or temperature at the location and A / D-convert the detection signal, and detect the current or temperature at a predetermined location of the inverter stage 80 to obtain the detection signal as A A second group of detection circuits 67 and 68 for / D conversion and a control block 70 for controlling the power block are included.

  The power block converts the AC voltage supplied from the input terminals 1 and 2 into a DC voltage, and combines the waveform and phase of the input voltage and input current to improve the power factor PFC (power factor controller) Control) stage 20, a capacitor 30 for smoothing the voltage output from PFC stage 20, and a DC voltage smoothed by capacitor 30 is switched to output a three-phase AC voltage for driving the motor to output terminals 5-7. And an inverter stage 80 to be supplied.

  The inverter stage 80 includes switching elements 81 and 82 connected to the U-phase output terminal 5, switching elements 83 and 84 connected to the V-phase output terminal 6, and switching connected to the W-phase output terminal 7. Elements 85 and 86 and a driver 87 for supplying a driving signal to the switching elements 81 to 86 are included. The switching elements 81 to 86 perform a switching operation between the input DC voltage and the U-phase to W-phase output terminals 5 to 7 in accordance with the respective drive signals, so that the output terminals 5 to 7 have a three-phase AC current. Supply voltage. As these switching elements, for example, an IGBT (Insulated Gate Bipolar Transistor) in which a diode is connected in parallel can be used.

  The second group of detection circuits includes a current detection circuit 67 and a temperature sensor 68. The current detection circuit 67 detects a current input to the inverter stage 80, A / D converts the detection signal, and outputs detection data. The temperature sensor 68 detects the temperature of the inverter stage 80 and outputs detection data by A / D converting the detection signal. Note that the type and number of detection circuits can be changed as needed.

  In the present embodiment, a plurality of switching elements 22 provided in the PFC stage 20 and switching elements 81 to 86 provided in the inverter stage 80 are individually controlled (PWM control, PFM control, etc.). A DSP is provided exclusively. On the other hand, when an abnormality occurs or switches to the standby mode, the DSPs communicate with each other so that smooth linkage is performed.

  The control block 70 includes a first DSP 71 that controls the PFC stage 20 by performing digital signal processing based on detection data output from the first group of detection circuits 61 to 63, a second group of detection circuits 67, and 68 includes a second DSP 72 that controls the inverter stage 80 by performing digital signal processing based on detection data output from 68, and a communication line 73 provided for communication between the DSP 71 and the DSP 72. It is out.

  2, a circuit board 78 includes a first DSP 71 that generates a drive signal A for driving the switching element 22 of the PFC stage 20 illustrated in FIG. 1, and a first group of detection circuits 61 to 61 in the PFC stage 20. 63, an A / D converter portion 74, an output circuit 75 that outputs a drive signal A to the driver 23 of the PFC stage 20, and a drive signal B for driving the switching elements 81 to 86 of the inverter stage 80. 2, a second group of DSPs 72, an A / D converter portion 76 of the second group of detection circuits 67 and 68 in the inverter stage 80, and an output circuit 77 that outputs a drive signal B to the driver 87 of the inverter stage 80. .

  In order to mute the analog detection signals input to the A / D converters 74 and 76, blank signals are supplied from the DSPs 71 and 72 to the A / D converters 74 and 76, respectively. The DSPs 71 and 72 are connected to an external control terminal used for controlling the DSPs 71 and 72 from the outside.

  In the present embodiment, each of the DSPs 71 and 72 generates a synchronization signal (pulse signal) associated with switching control and transmits it to each other, whereby the A / D converter 76 connected to the other DSP. And 74 are supplied as blank signals, and the detection result in the other power stage is masked.

FIG. 6 shows waveforms at various parts in the power supply circuit shown in FIG. The driver 87 of the inverter stage 80 outputs, for example, a drive signal having a frequency of about 20 kHz to 25 kHz to the switching element 82 as shown in FIG. As a result, the potential V ₈₂ on the output side of the switching element 82 changes as shown in FIG. Further, since the load of the power supply circuit is a motor winding and has an inductance component, the current I ₈₂ flowing through the switching element 82 changes as shown in FIG. As a result, as shown in (d) of FIG. 6, the switching noise is generated at the leading edge and / or trailing edge of the pulse of current I _82.

First DSP71, as shown in FIG. 6 (e), to generate a first blank signal synchronized with the rising portion and / or trailing edge of the pulse of current I _82. This first blank signal is activated in a period covering the switching noise generated by the pulse of the current _I82 .

Further, the driver 23 of the PFC stage 20 outputs a drive signal having a frequency of about 100 kHz to the switching element 22 as shown in FIG. Thus, the hot side of the potential V ₂₂ of the switching element 22 changes as shown in (g) in FIG. 6. Further, since the hot side of the switching element 22 the inductor 21 is connected, a current I ₂₂ flowing through the switching element 82 is changed as shown at (h) in FIG. 6. As a result, as shown in (i) of FIG. 6, the switching noise is generated at the leading edge and / or trailing edge of the pulse of current I _22.

The second DSP 72 generates a second blank signal synchronized with the rising portion and / or the falling portion of the pulse of the current I ₂₂ as shown in FIG. The second blank signal is activated during a period covering the switching noise generated by the pulse current I _22.

  In FIG. 2, DSPs 71 and 72 transmit the first and second blank signals to each other. The first DSP 71 supplies the second blank signal received from the DSP 72 to the A / D converter 74, thereby muting the analog detection signal input to the A / D converter 74. As a result, the detection results of the first group of detection circuits 61 to 63 are masked for a predetermined period based on the second blank signal. In addition to or instead of this, the second DSP 72 supplies the first blank signal received from the DSP 71 to the A / D converter 76, whereby the analog detection signal input to the A / D converter 76. May be muted. As a result, the detection results of the second group of detection circuits 67 and 68 are masked for a predetermined period based on the first blank signal. Thereby, when a plurality of DSPs perform switching control of a plurality of power stages in parallel, each switching control can be performed safely and reliably.

  Here, the first DSP 71 generates a first drive signal having the first frequency and supplies it to the switching element 22 of the PFC stage 20, and the second DSP 72 has the second frequency having the second frequency. When the drive signal is generated and supplied to the switching element 42 of the inverter stage 80, the ratio of these frequencies is set so that the first frequency is an integral multiple of the second frequency. The first and second blank signals may be generated in synchronization with one drive signal. For example, when the frequency of the drive signal generated by the driver 23 of the PFC stage 20 is 100 kHz, the frequency of the drive signal generated by the driver 87 of the inverter stage 80 is 25 kHz, which is 1/4 of 100 kHz, or 100 kHz. 20 kHz which is 1/5 of. In that case, the noise generation timing can be made uniform in the PFC stage 20 and the inverter stage 80, and the frequencies of the first and second blank signals can be unified.

  The present invention can be used in a power supply circuit that performs step-up or step-down or generates an alternating voltage by a switching operation.

It is a figure which shows the structure of the power supply circuit which concerns on the 1st Embodiment of this invention. It is a figure which shows the state by which the component of the control block was mounted in the board | substrate. 3 is a flowchart illustrating a first operation example of the power supply circuit illustrated in FIG. 1. 6 is a flowchart illustrating a second operation example of the power supply circuit illustrated in FIG. 1. It is a figure which shows the structure of the power supply circuit which concerns on the 2nd Embodiment of this invention. It is a figure which shows the waveform of each part in the power supply circuit shown in FIG.

Explanation of symbols

1, 2 AC input terminals 3, 4 DC output terminals 5-7 3 phase AC output terminals 10 Rectifier circuit 20 PFC stage 21 Inductors 22, 42, 81-86 Switching elements 23, 43, 87 Drivers 24, 44 Diodes 30, 50 Capacitor 40 DC / DC converter stage 41 Transformer 61, 64, 67 Current detection circuit 62, 65 Voltage detection circuit 63, 66, 68 Temperature sensor 70 Control block 71, 72 DSP
71a, 72a Flash memory 71b, 72b RAM
73 Communication line 74, 76 A / D converter 75 Output circuit for drive signal A 77 Output circuit for drive signal B 78 Circuit board 80 Inverter stage

Claims (7)

A power block including a plurality of power stages that perform step-up or step-down or generate an AC voltage from a DC voltage;
A first group of detection circuits for detecting a current or voltage or temperature at a predetermined location of the first power stage and A / D converting a detection signal;
A second group of detection circuits for detecting a current, voltage, or temperature at a predetermined location of the second power stage located after the first power stage and A / D converting a detection signal;
A first digital signal processor for controlling the first power stage by performing digital signal processing based on detection data output from the first group of detection circuits;
A second digital signal processor for controlling the second power stage by performing digital signal processing based on detection data output from the second group of detection circuits;
A communication line provided for communicating between the first digital signal processor and the second digital signal processor;
And the second digital signal processor determines a load state based on detection data output from at least one of the second group of detection circuits, and provides mode information corresponding to the load state. A power supply circuit for transmitting to a first digital signal processor.   The second digital signal processor determines a load condition by comparing a value represented by detection data output from at least one of the second group of detection circuits to a threshold value. The power supply circuit according to 1.   In accordance with mode information transmitted from the second digital signal processor, the first digital signal processor sets the operation mode of the first power stage to one of a normal mode and a standby mode, or The power supply circuit according to claim 1, wherein the power supply circuit is set to any one of a normal mode and a stop mode, or any one of a normal mode and a test mode.   The first digital signal processor changes the operation mode of the first power stage according to the mode information transmitted from the second digital signal processor, and the first digital signal processor in the newly set operation mode. The storage means for storing a control program for causing the CPU to execute a procedure for performing a calculation for controlling the power stage and a procedure for storing information on the previous setting state and the new setting state. Power supply circuit. A power block including a plurality of power stages that perform step-up or step-down using a switching element or generate an AC voltage from a DC voltage;
A first group of detection circuits for detecting a current or voltage or temperature at a predetermined location of the first power stage and A / D converting a detection signal;
A second group of detection circuits for detecting a current or voltage or temperature at a predetermined location of the second power stage and A / D converting the detection signal;
Pulses generated by the switching operation of the first power stage while driving the switching element of the first power stage by performing digital signal processing based on detection data output from the detection circuit of the first group A first digital signal processor for generating a first synchronization signal synchronized to the current;
Pulses generated by the switching operation of the second power stage while driving the switching element of the second power stage by performing digital signal processing based on detection data output from the detection circuit of the second group A second digital signal processor for generating a second synchronization signal synchronized to the current;
A communication line provided for communicating between the first digital signal processor and the second digital signal processor;
And the first and second digital signal processors transmit the first and second synchronization signals to each other so that the first digital signal processor is based on the second synchronization signal. And / or the second digital signal processor masks the detection results of the second group of detection circuits for a predetermined period based on a first synchronization signal. A power circuit characterized by. The first digital signal processor generates a first drive signal having a first frequency and supplies the first drive signal to a switching element of the first power stage;
The second digital signal processor generates a second drive signal having a second frequency and supplies the second drive signal to the switching element of the second power stage;
A first frequency is an integer multiple of a second frequency, and the first and second digital signal processors respectively generate first and second synchronization signals synchronized with a first drive signal;
The power supply circuit according to claim 5.   The power supply circuit according to any one of claims 1 to 6, wherein each of the first and second digital signal processors is molded in a separate package and is independently replaceable.

Images