JP2006303342A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a test element group, with the influence of actual difference in levels on a real device reflected in the wiring width, while saving a space. <P>SOLUTION: An active region R1 forming a test element group for evaluating characteristics is provided on a semiconductor substrate 1. A gate electrode 4 is formed via a gate insulating film 3 on the active region R1, and source/drain layers 7a and 7b are formed respectively via LDD layers 6a and 6b, thereby forming a field effect transistor in the element group. A line width detecting wiring layer 9c, provided to extend across the level difference of an interlayer insulating film 8, is formed on the test element group for evaluating the characteristics with the field effect transistor formed. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device, and is particularly suitable for application to a method for inspecting variations in wiring width caused by a base step.

In the conventional semiconductor device, the wiring width varies due to the level difference or shape of the base, and the wiring is thinned. For this reason, it is carried out by examining the wafer with an optical microscope or a defect inspection apparatus to find out how thin the wiring is and whether there are any abnormal parts.
Further, for example, in Patent Document 1, in order to detect a delicate disconnection of a wiring formed in a stepped portion with high sensitivity, four sets of resistors having the same shape, the same size, and the same resistance value are used. A method for forming an Easton bridge in a stepped portion is disclosed.

Further, for example, in Patent Document 2, in order to reliably detect the danger of a short circuit between wirings in a semiconductor integrated circuit, an etching residue is generated in an upper wiring layer due to a step generated by a lower wiring layer, thereby causing a short circuit between wirings. A method of forming a test element group for indicating the presence or absence of the test is disclosed.
Japanese Patent Laid-Open No. 10-107109 JP 2000-260842 A

  However, in the method of thoroughly inspecting the wafer with an optical microscope or a defect inspection apparatus, even in the same process, there are places where the level difference is high or low depending on the model. There was a problem that inspection could take a long time and there were many oversights of abnormal parts. Even when a defect inspection system is used, even if the process is the same, there are places where the level difference is high or low depending on the model, so appropriate inspection conditions such as the focus point cannot be uniquely determined. There was a problem that it was difficult to set and high-precision inspection could not be performed.

  In addition, since the method disclosed in Patent Document 1 uses the Wheatstone bridge, four pad electrodes are required respectively at the four corners of the Wheatstone bridge, and the arrangement of the Wheatstone bridge is restricted. Since it is necessary to form a base step separately from the actual device, there is a problem that it is necessary to separately secure a space for arranging the Wheatstone bridge. Further, since the base step is formed separately from the actual device, it is difficult to reflect the effect of the actual step of the actual device, and there is a problem that an abnormal part may be detected erroneously.

  Further, in the method disclosed in Patent Document 2, it is necessary to newly form a test element group for generating an etching residue in the upper wiring layer due to a step generated by the lower wiring layer, and for arranging the test element group There was a problem that it was necessary to secure a new space. Further, since the base step is formed separately from the actual device, it is difficult to reflect the effect of the actual step of the actual device, and there is a problem that an abnormal part may be detected erroneously.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device and a semiconductor device manufacturing method capable of forming a test element group in which the effect of an actual step of an actual device is reflected in the wiring width while saving space. It is to be.

In order to solve the above-described problem, according to a semiconductor device of one embodiment of the present invention, a characteristic evaluation test element group formed on a semiconductor substrate and a step existing on the characteristic evaluation test element group are provided. And a line width detecting wiring layer arranged as described above.
As a result, the line width detection wiring layer can be arranged on the characteristic evaluation test element group, and the inspection region can be limited to a specific location. For this reason, it is possible to reduce the time required for the inspection, and it is possible to reduce oversight of abnormal parts.

  In addition, by forming the line width detection wiring layer on the characteristic evaluation test element group, it is not necessary to separately secure a space for arranging the test element group in which the line width detection wiring layer is formed. It is possible to arrange the line width detection wiring layer on the base step having the same shape and dimensions as the actual device. For this reason, it is possible to save space and to reflect the effect of the actual step of the actual device on the line width detection wiring layer, and to detect the abnormal part with high accuracy.

In the semiconductor device according to one aspect of the present invention, the line width detection wiring layer is configured such that at least one of a wiring width and a wiring interval changes.
Thereby, it is possible to collectively inspect the thinning or disconnection of the wiring layer due to the base step for a plurality of wiring widths and wiring intervals without preparing a plurality of test element groups. For this reason, it is possible to efficiently inspect an abnormal portion caused by the base step while saving space.

  According to the semiconductor device of one embodiment of the present invention, the test element group for characteristic evaluation is formed on the semiconductor substrate so as to sandwich the gate electrode formed on the semiconductor substrate. A source / drain layer, an interlayer insulating layer formed on the semiconductor substrate so as to cover the gate electrode, and a wiring layer for characteristic evaluation disposed on the interlayer insulating layer and connected to the source / drain layer The line width detection wiring layer is disposed on the interlayer insulating layer so as to straddle the gate electrode, and is composed of the same wiring layer as the characteristic evaluation wiring layer. .

  Thus, by forming a line width detection wiring layer on the test element group for characteristic evaluation, the line width detection wiring layer is arranged on the base step having the same shape and size as the actual field-effect transistor. This makes it possible to accurately estimate the thinness or disconnection of the wiring layer formed on the field effect transistor without inspecting the entire surface of the wafer, and the wiring layer for detecting the line width is formed. It is not necessary to separately secure a space for arranging the test element group, and space saving can be achieved.

Also, by configuring the line width detection wiring layer and the characteristic evaluation wiring layer with the same wiring layer, the line width detection wiring layer and the characteristic evaluation wiring layer can be formed in a lump. The line width detecting wiring layer can be arranged on the test element group in which the field effect transistor is formed without increasing the number.
According to the semiconductor device of one embodiment of the present invention, the first pad electrode connected to the gate electrode and the second pad connected to the source / drain layer via the characteristic evaluation wiring layer, respectively. An active region in which the source / drain layer is formed and the first to third pad electrodes are arranged side by side on the same straight line, and an electrode and a third pad electrode connected to the line width detecting wiring layer. It is characterized by being.

  As a result, even when the line width detection wiring layer is disposed on the test element group in which the field effect transistor is formed, the test element group can be inspected for the characteristics of the line width detection wiring layer. Thus, it is possible to inspect the characteristics of the field-effect transistor formed in this manner, and it is possible to accurately estimate the thinning or disconnection of the wiring layer while saving space. Further, by arranging the pad electrodes side by side on the same straight line, the test element group can be formed on the scribe line, and the wafer can be effectively used.

  According to the semiconductor device of one embodiment of the present invention, the test element group for characteristic evaluation is formed on the semiconductor substrate so as to sandwich the gate electrode formed on the semiconductor substrate. A source / drain layer, a first interlayer insulating layer formed on the semiconductor substrate so as to cover the gate electrode, and a lower layer disposed on the first interlayer insulating layer and connected to the source / drain layer A wiring layer; and a second interlayer insulating layer disposed on the lower wiring layer, wherein the line width detecting wiring layer is disposed on the first interlayer insulating layer so as to straddle the gate electrode, A first line width detecting wiring layer composed of the same wiring layer as the lower wiring layer, and a second line width detecting wiring layer composed of an upper wiring layer disposed on the second interlayer insulating layer; Characterized by comprising

  As a result, the line width detection wiring layer is formed in multiple layers on the test element group for characteristic evaluation, so that the line width detection wiring layer is multilayered on the base step having the same shape and dimensions as the actual field effect transistor. It is possible to arrange the test element group, and it is possible to accurately estimate the thinning and disconnection of the multilayer wiring layer without thoroughly inspecting the wafer, and the line width detection wiring layer is formed in multiple layers. Therefore, it is not necessary to separately secure a space for disposing the space, and space can be saved.

  According to the semiconductor device of one embodiment of the present invention, the first pad electrode connected to the gate electrode and the second pad connected to the source / drain layer via the characteristic evaluation wiring layer, respectively. An electrode; a third pad electrode connected to the first line width detection wiring layer; and a fourth pad electrode connected to the second line width detection wiring layer, wherein the source / drain layer is formed The formed active region and the first to fourth pad electrodes are arranged on the same straight line.

  As a result, even when the line width detection wiring layer is arranged in multiple layers on the test element group in which the field effect transistor is formed, it is possible to inspect the characteristics of the line width detection wiring layer. The characteristics of the field effect transistors formed in the group can be inspected, and it is possible to accurately estimate the thinning or disconnection of the multilayer wiring layer while saving space. Further, by arranging the pad electrodes side by side on the same straight line, a test element group in which a multilayer wiring layer is formed can be formed on a scribe line, and the wafer can be effectively used.

  According to the semiconductor device of one aspect of the present invention, the test element group for characteristic evaluation includes an emitter layer formed on the semiconductor substrate, a base layer formed on the semiconductor substrate, and the semiconductor A collector layer formed on the substrate; a lower wiring layer connected to the emitter layer, the base layer, and the collector layer; and an interlayer insulating layer disposed on the lower wiring layer, the line width detecting The wiring layer is composed of an upper wiring layer disposed on the interlayer insulating layer so as to straddle the lower wiring layer.

  As a result, by forming the line width detection wiring layer on the characteristic test element group, it is possible to arrange the line width detection wiring layer on the underlying step having the same shape and dimensions as the actual bipolar transistor. Therefore, it is possible to accurately estimate the thinning or disconnection of the wiring layer formed on the bipolar transistor without thoroughly inspecting the wafer, and the test element group in which the wiring layer for detecting the line width is formed. It is not necessary to separately secure a space for arrangement, and space saving can be achieved.

  According to the semiconductor device of one aspect of the present invention, the test element group for characteristic evaluation is formed on the semiconductor substrate so as to cover the resistance layer formed on the semiconductor substrate and the resistance layer. An interlayer insulating layer and a characteristic evaluation wiring layer disposed on the interlayer insulating layer and connected to the resistance layer, the line width detecting wiring layer straddling the resistance layer. It is arranged on an insulating layer and is composed of the same wiring layer as the characteristic evaluation wiring layer.

  As a result, by forming the line width detection wiring layer on the characteristic test element group, it is possible to place the line width detection wiring layer on the base step having the same shape and dimensions as the actual resistance layer. Therefore, it is possible to accurately estimate the thinness or disconnection of the wiring layer formed on the resistance layer without thoroughly inspecting the wafer, and the test element group in which the wiring layer for detecting the line width is formed. It is not necessary to separately secure a space for arrangement, and space saving can be achieved.

  According to the semiconductor device of one aspect of the present invention, the test element group for characteristic evaluation includes a lower electrode formed on the semiconductor substrate and an upper electrode disposed so as to face the lower electrode. And a dielectric film disposed between the lower electrode and the upper electrode, an interlayer insulating layer formed on the semiconductor substrate so as to cover the upper electrode, and disposed on the interlayer insulating layer, A wiring layer for characteristic evaluation connected to each of the lower electrode and the upper electrode, and the line width detecting wiring layer is disposed on the interlayer insulating layer so as to straddle the lower electrode and the upper electrode, It is characterized by comprising the same wiring layer as the characteristic evaluation wiring layer.

  As a result, by forming the line width detection wiring layer on the characteristic evaluation test element group, it becomes possible to place the line width detection wiring layer on the underlying step having the same shape and dimensions as the actual capacitor. It is possible to accurately estimate the thinning or disconnection of the wiring layer formed on the capacitor without thoroughly inspecting the wafer, and a test element group in which the wiring layer for detecting the line width is formed is arranged. For this reason, it is not necessary to secure a separate space for saving the space.

According to the method for manufacturing a semiconductor device of one aspect of the present invention, the step of forming the characteristic evaluation test element group on the semiconductor substrate and the step existing on the characteristic evaluation test element group are applied. And a step of forming the arranged line width detection wiring layer.
This makes it possible to place a wiring layer for line width detection on the test element group for characteristic evaluation, and to detect a thinning or disconnection of the wiring layer without thoroughly inspecting the wafer. In addition to shortening the time required for inspection, it is possible to reduce oversight of abnormal parts.

In addition, it is not necessary to secure a separate space for arranging the test element group in which the wiring layer for detecting the line width is formed, so that space saving can be achieved and the shape and dimensions are the same as those of the actual device. A line width detecting wiring layer can be disposed on the base step, and an abnormal part can be detected with high accuracy.
According to the method for manufacturing a semiconductor device of one embodiment of the present invention, a step of forming a gate electrode on a semiconductor substrate and a source / drain layer disposed so as to sandwich the gate electrode are formed on the semiconductor substrate. Forming an interlayer insulating layer on the semiconductor substrate so as to cover the gate electrode, forming an opening in the interlayer insulating layer to expose the source / drain layers, Forming a conductive film on the interlayer insulating layer; and patterning the conductive film to form a characteristic evaluation wiring layer connected to the source / drain layer through the opening on the interlayer insulating layer. And forming a line width detecting wiring layer disposed so as to straddle the gate electrode on the interlayer insulating layer.

  This eliminates the need for a separate space for arranging the test element group in which the wiring layer for detecting the line width is formed, thereby enabling space saving and the actual field effect transistor and shape. In addition, it is possible to dispose the line width detecting wiring layer on the base step having the same dimensions, and it is possible to accurately estimate the thinning or disconnection of the wiring layer formed on the field effect transistor.

  According to the method for manufacturing a semiconductor device of one embodiment of the present invention, a step of forming a gate electrode on a semiconductor substrate and a source / drain layer disposed so as to sandwich the gate electrode are formed on the semiconductor substrate. Forming a first interlayer insulating layer on the semiconductor substrate so as to cover the gate electrode, and forming an opening in the first interlayer insulating layer to expose the source / drain layers. A step of forming a first conductive film on the first interlayer insulating layer, and patterning the first conductive film, thereby evaluating characteristics connected to the source / drain layers through the openings. Forming a wiring layer on the first interlayer insulating layer, and forming a first line width detecting wiring layer disposed on the first interlayer insulating layer so as to straddle the gate electrode; Forming a second interlayer insulating layer on the semiconductor substrate so as to cover the characteristic evaluation wiring layer and the first line width detecting wiring layer; and a second conductive film on the second interlayer insulating layer. And patterning the second conductive film to form a second line width detection wiring layer disposed over the first line width detection wiring layer on the second interlayer insulating layer. And a forming step.

  As a result, it is not necessary to secure a separate space for arranging the test element group in which the wiring layers for detecting the line width are formed in multiple layers, so that space saving can be achieved and an actual field effect transistor can be realized. It is possible to arrange multi-layered wiring layers for line width detection on the same base level and shape and size, and it is possible to accurately estimate the thinness and disconnection of the multi-layer wiring layer formed on the field effect transistor. Become.

  According to the method for manufacturing a semiconductor device of one embodiment of the present invention, the step of forming the first impurity diffusion layer serving as the emitter layer on the semiconductor substrate and the second impurity diffusion layer serving as the base layer on the semiconductor substrate are provided. Forming a third impurity diffusion layer serving as a collector layer on the semiconductor substrate, forming a lower wiring layer connected to the emitter layer, the base layer, and the collector layer, and the lower wiring Forming a wiring layer for line width detection composed of an interlayer insulating layer disposed on the semiconductor substrate and an upper wiring layer disposed so as to straddle the lower wiring layer. And a step of forming on the insulating layer.

  This eliminates the need for a separate space for arranging the test element group in which the wiring layer for detecting the line width is formed, thereby enabling space saving and the shape and size of the actual bipolar transistor. However, it is possible to arrange the line width detecting wiring layer on the same base step, and it is possible to accurately estimate the thinning or disconnection of the wiring layer formed on the bipolar transistor.

  According to the method for manufacturing a semiconductor device of one embodiment of the present invention, a step of forming a resistance layer on the semiconductor substrate, and an interlayer insulating layer disposed to cover the resistance layer are formed on the semiconductor substrate. A step of forming an opening exposing the resistance layer in the interlayer insulating layer, a step of forming a conductive film in the interlayer insulating layer, and patterning the conductive film, thereby forming the opening through the opening. Forming a characteristic evaluation wiring layer connected to the resistance layer on the interlayer insulating layer, and forming a line width detecting wiring layer disposed across the resistance layer on the interlayer insulating layer. It is characterized by providing.

  As a result, it is not necessary to separately secure a space for arranging the test element group in which the wiring layer for detecting the line width is formed, and the space can be saved, and the actual resistance layer, shape and dimensions can be achieved. However, it is possible to arrange the line width detecting wiring layer on the same base step, and it is possible to accurately estimate the thinning or disconnection of the wiring layer formed on the resistance layer.

  In addition, according to the method for manufacturing a semiconductor device according to one aspect of the present invention, a step of forming a lower electrode on a semiconductor substrate, a step of forming a dielectric film on the lower electrode, and a step through the dielectric film Forming an upper electrode disposed so as to face the lower electrode; forming an interlayer insulating layer disposed on the semiconductor substrate so as to cover the upper electrode; and the lower electrode and the upper electrode Forming an opening in each of the interlayer insulating layers for exposing the electrodes; forming a conductive film in the interlayer insulating layer; and patterning the conductive film to form the lower electrode and the lower electrode through the openings. A characteristic evaluation wiring layer connected to each of the upper electrodes is formed on the interlayer insulating layer, and a line width detection wiring layer arranged so as to straddle the lower electrode and the upper electrode. Characterized in that it comprises a step of forming the interlayer insulating layer.

  As a result, it is not necessary to secure a separate space for arranging the test element group in which the wiring layer for detecting the line width is formed, it is possible to save space, and the actual capacitor, shape, and dimensions can be reduced. The line width detecting wiring layer can be disposed on the same base step, and the thinning or disconnection of the wiring layer formed on the capacitor can be accurately estimated.

Hereinafter, a semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be described with reference to the drawings.
1A is a cross-sectional view showing a schematic configuration of the semiconductor device according to the first embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along the line A1-A1 ′ of FIG. is there.
In FIG. 1, an element isolation insulating film 2 is formed on a semiconductor substrate 1, and an active region R <b> 1 isolated by the element isolation insulating film 2 is provided. The element isolation insulating film 2 may have a LOCOS (Local Oxidation of Silicon) structure or an STI (Shallow Trench Isolation) structure. Moreover, a test element group for characteristic evaluation can be formed in the active region R1, and the active region R1 can be arranged on a scribe line of a semiconductor wafer, for example.

A gate electrode 4 is formed in the active region R1 on the semiconductor substrate 1 with a gate insulating film 3 interposed therebetween. Sidewalls 5 are formed on the side walls of the gate electrode 4, and source / drain layers 7a and 7b are formed on the semiconductor substrate 1 through LDD (Lightly Doped Drain) layers 6a and 6b, respectively. Yes.
An interlayer insulating film 8 is formed on the semiconductor substrate 1 so as to cover the gate electrode 4. The interlayer insulating film 8 has an opening K1 that exposes the surfaces of the source / drain layers 7a and 7b. , K2 is formed. On the interlayer insulating film 8, wiring layers 9a and 9b connected to the source / drain layers 7a and 7b through the openings K1 and K2, respectively, are formed, and the step of the interlayer insulating film 8 is applied. A line width detecting wiring layer 9c arranged in this manner is formed.

  When the line width detection wiring layer 9 c is disposed so as to cover the step of the interlayer insulating film 8, the line width detection wiring layer 9 c can be folded over the gate electrode 4. The line width detection wiring layer 9c may be configured such that at least one of the wiring width and the wiring interval changes at the folded portion. The wiring layers 9a and 9b and the line width detecting wiring layer 9c can be formed by patterning the same wiring material formed on the interlayer insulating film 8. Further, as the material of the wiring layers 9a and 9b and the line width detecting wiring layer 9c, for example, Al can be used.

As a result, the line width detection wiring layer 9c can be arranged on the characteristic evaluation test element group, and the thinness or disconnection of the line width detection wiring layer 9c can be found without thoroughly inspecting the semiconductor wafer. Therefore, it is possible to reduce the time required for the inspection, and it is possible to reduce oversight of abnormal parts.
Further, by forming the line width detecting wiring layer 9c on the characteristic evaluation test element group, the line width detecting wiring layer 9c is arranged on the base step having the same shape and size as the actual field effect transistor. Therefore, it is possible to accurately estimate the thinning or disconnection of the wiring layer formed on the field effect transistor without inspecting the entire surface of the wafer, and the wiring width detecting wiring layer 9c is formed. Therefore, it is not necessary to separately secure a space for arranging the test element group on the wafer, and space can be saved.

  In addition, by configuring the line width detection wiring layer 9c so that at least one of the wiring width and the wiring interval changes, a plurality of wiring widths and With regard to the wiring interval, it becomes possible to inspect collectively the thinness or disconnection of the width detection wiring layer 9c caused by the underlying step. For this reason, it is possible to efficiently inspect an abnormal portion caused by the base step while saving space.

Furthermore, by forming the wiring layers 9a, 9b and the line width detecting wiring layer 9c on the same wiring layer, the wiring layers 9a, 9b and the line width detecting wiring layer 9c can be formed at once. The line width detecting wiring layer 9c can be arranged on the test element group in which the field effect transistor is formed without increasing the number of processes.
In the embodiment of FIG. 1, the field effect transistor having the LDD layers 6a and 6b has been described as an example. However, the field effect transistor without the LDD layers 6a and 6b may be applied.

FIG. 2 is a plan view showing a method for arranging pad electrodes of the semiconductor device of FIG.
In FIG. 2, the pad electrodes P1 to P5 and the active region R1 of FIG. 1 are arranged in a line. The gate electrode 4 in FIG. 1 is connected to the pad electrode P1 so as to bypass the pad electrodes P2 and P3. Further, both ends of the line width detection wiring layer 9c are connected to the pad electrodes P2 and P5 so as to bypass the pad electrodes P3 and P4, respectively. Furthermore, the wiring layers 9a and 9b connected to the source / drain layers 7a and 7b are connected to the pad electrodes P3 and P4, respectively.

When evaluating the characteristics of the field effect transistor formed in the characteristic evaluation test element group, the probe is brought into contact with the pad electrodes P1, P3, and P4, and a voltage is applied to the gate electrode 4 through the pad electrode P1. However, the current flowing through the source / drain layers 7a and 7b via the pad electrodes P3 and P4 can be detected.
When evaluating the characteristics of the line width detection wiring layer 9c formed on the characteristic evaluation test element group, the probe is brought into contact with the pad electrodes P1 and P5, and the line width is detected via the pad electrodes P1 and P5. The resistance value of the line width detecting wiring layer 9c can be measured by detecting the current flowing through the line width detecting wiring layer 9c while applying a voltage to the wiring layer 9c for use.

  As a result, even when the line width detection wiring layer 9c is arranged on the test element group in which the field effect transistor is formed, the characteristics of the line width detection wiring layer 9c can be inspected while being tested. It becomes possible to inspect the characteristics of the field effect transistors formed in the element group, and it is possible to accurately estimate the thinning or disconnection of the wiring layer while saving space. Further, by arranging the pad electrodes P1 to P5 side by side on the same straight line, it becomes possible to form a test element group on which the line width detecting wiring layer 9c is arranged on the scribe line, thereby effectively using the semiconductor wafer. It becomes possible to plan.

3A is a cross-sectional view showing a schematic configuration of a semiconductor device according to the second embodiment of the present invention, and FIG. 3B is a cross-sectional view taken along the line A2-A2 ′ of FIG. 3A. is there.
In FIG. 3, an element isolation insulating film 12 is formed on a semiconductor substrate 11, and an active region R <b> 2 isolated by the element isolation insulating film 12 is provided. Note that a characteristic evaluation test element group can be formed in the active region R2, and the active region R2 can be disposed on, for example, a scribe line of a semiconductor wafer.

A gate electrode 14 is formed in the active region R <b> 2 on the semiconductor substrate 11 via a gate insulating film 13. A side wall 15 is formed on the side wall of the gate electrode 14, and source / drain layers 17a and 17b are formed on the semiconductor substrate 11 through LDD layers 16a and 16b, respectively.
An interlayer insulating film 18 is formed on the semiconductor substrate 11 so as to cover the gate electrode 14, and the interlayer insulating film 18 has an opening K11 that exposes the surfaces of the source / drain layers 17a and 17b. , K12 is formed. On the interlayer insulating film 18, wiring layers 19a and 19b connected to the source / drain layers 17a and 17b through the openings K11 and K12, respectively, are formed, and the step of the interlayer insulating film 18 is applied. A line width detection wiring layer 19c arranged in this manner is formed.

  Further, an interlayer insulating film 20 is formed on the wiring layers 19a and 19b and the line width detecting wiring layer 19c, and the line width detection arranged on the interlayer insulating film 20 so as to cover the step of the interlayer insulating film 20 is performed. A wiring layer 21 is formed. In the case where the line width detection wiring layer 21 is arranged so as to cover the step of the interlayer insulating film 20, the line width detection wiring layer 21 may be folded back so as to straddle the line width detection wiring layer 19c. it can. Further, the line width detecting wiring layer 21 may be configured such that at least one of the wiring width and the wiring interval changes at the folded portion.

  As a result, the line width detection wiring layers 19c and 21 are formed in multiple layers on the test element group for characteristic evaluation, so that the line width detection wiring is formed on the underlying step having the same shape and dimensions as the actual field effect transistor. The layers 19c and 21 can be arranged in multiple layers, and it is possible to accurately estimate the thinning and breakage of the multilayer wiring layer without thoroughly inspecting the wafer, and the line width detection wiring layers 19c and 21 can be estimated. However, it is not necessary to separately secure a space for arranging test element groups formed in multiple layers on the wafer, and space saving can be achieved.

FIG. 4 is a plan view showing a method for arranging pad electrodes of the semiconductor device of FIG.
In FIG. 4, the pad electrodes P11 to P17 and the active region R2 of FIG. 3 are arranged in a line. The gate electrode 14 in FIG. 3 is connected to the pad electrode P11 so as to bypass the pad electrodes P12 and P13. Further, both ends of the line width detection wiring layer 19c are connected to the pad electrodes P12 and P15 so as to bypass the pad electrodes P13 and P14, respectively. Further, the wiring layers 19a and 19b connected to the source / drain layers 17a and 17b are connected to the pad electrodes P13 and P14, respectively. Further, both ends of the line width detection wiring layer 21 are connected to pad electrodes P16 and P17 so as to bypass the pad electrodes P11 to P15, respectively.

  When evaluating the characteristics of the field effect transistor formed in the test element group for characteristic evaluation, a probe is brought into contact with each of the pad electrodes P11, P13, and P14, and a voltage is applied to the gate electrode 14 through the pad electrode P11. However, the current flowing through the source / drain layers 17a and 17b via the pad electrodes P13 and P14 can be detected.

  When evaluating the characteristics of the line width detecting wiring layer 19c formed on the characteristic evaluation test element group, the probe is brought into contact with the pad electrodes P11 and P15, and the line width is detected via the pad electrodes P11 and P15. The resistance value of the line width detection wiring layer 19c can be measured by detecting the current flowing through the line width detection wiring layer 19c while applying a voltage to the wiring wiring layer 19c.

  When evaluating the characteristics of the line width detecting wiring layer 21 formed on the characteristic evaluation test element group, the probe is brought into contact with the pad electrodes P16 and P17, and the line width is detected via the pad electrodes P16 and P17. The resistance value of the line width detection wiring layer 21 can be measured by detecting the current flowing through the line width detection wiring layer 21c while applying a voltage to the wiring layer 21 for use.

  Thereby, even when the line width detecting wiring layers 19c and 21 are arranged in a multilayer on the test element group in which the field effect transistor is formed, the characteristics of the line width detecting wiring layers 19c and 21 are inspected. In addition, the characteristics of the field effect transistors formed in the test element group can be inspected, and thinning and disconnection of the multilayer wiring layer can be accurately estimated while saving space. Also, by arranging the pad electrodes P11 to P17 side by side on the same straight line, it becomes possible to form a test element group in which the line width detecting wiring layers 19c and 21 are formed on the scribe line, thereby effectively using the wafer. Can be achieved.

FIG. 5A is a cross-sectional view showing a schematic configuration of a semiconductor device according to the third embodiment of the present invention, and FIG. 5B is a cross-sectional view taken along the line A3-A3 ′ of FIG. is there.
In FIG. 5, an N well 33 is formed in a semiconductor substrate 31, and an N ⁺ buried layer 32 is buried in the N well 33. An element isolation insulating film 34 is formed in the N well 33, and active regions R3a to R3c that are element-isolated by the element isolation insulating film 34 are provided. Note that a characteristic evaluation test element group can be formed in the active regions R3a to R3c, and the active regions R3a to R3c can be arranged on, for example, a scribe line of a semiconductor wafer.

In the N well 33, a P ⁺ diffusion layer 35a disposed so as to cover the active regions R3a and R3b is formed. In the P ⁺ diffusion layer 35a, an N ⁺ diffusion layer disposed in the active region R3b is formed. 35b is formed. In the N well 33, an N ⁺ diffusion layer 35c arranged in the active region R3c is formed. On the semiconductor substrate 31, lower wiring layers 36a to 36c connected to the P ⁺ diffusion layer 35a and the N ⁺ diffusion layers 35b and 35c are formed.

An interlayer insulating film 37 is formed on the semiconductor substrate 31 so as to cover the lower wiring layers 36 a to 36 c, and is disposed on the interlayer insulating film 37 so as to cover the step of the interlayer insulating film 37. A line width detecting wiring layer 38 is formed.
When the line width detecting wiring layer 38 is disposed so as to cover the step of the interlayer insulating film 37, the line width detecting wiring layer 38 can be folded back so as to straddle the lower wiring layers 36a to 36c. . The line width detection wiring layer 38 may be configured such that at least one of the wiring width and the wiring interval changes at the folded portion. Moreover, as a material of the lower wiring layers 36a to 36c and the line width detecting wiring layer 38, for example, Al can be used.

  Thus, by forming the line width detecting wiring layer 38 on the test element group for characteristic evaluation, the line width detecting wiring layer 38 is arranged on the base step having the same shape and size as the actual bipolar transistor. Therefore, it is possible to accurately estimate the thinness or disconnection of the wiring layer formed on the bipolar transistor without inspecting the wafer thoroughly, and the test in which the wiring layer 38 for detecting the line width is formed. It is not necessary to separately secure a space for arranging the element group on the wafer, and space saving can be achieved.

In the embodiment of FIG. 5, the method of forming the line width detection wiring layer 38 on the characteristic evaluation test element group in which the NPN bipolar transistor is formed has been described as an example. However, the PNP bipolar transistor is formed. The line width detection wiring layer 38 may be formed on the characteristic evaluation test element group.
6A is a cross-sectional view showing a schematic configuration of a semiconductor device according to the fourth embodiment of the present invention, FIG. 6B is a cross-sectional view taken along the line A4-A4 ′ of FIG. FIG. 6C is a cross-sectional view taken along line B4-B4 ′ of FIG.

  In FIG. 6, a resistance layer 43 is formed on a semiconductor substrate 41 via a base insulating film 42. The resistance layer 43 can form a test element group for characteristic evaluation, and the resistance layer 43 can be disposed, for example, on a scribe line of a semiconductor wafer. Then, an interlayer insulating film 44 is formed on the semiconductor substrate 41 so as to cover the resistance layer 43, and openings K 41 and K 42 that expose both ends of the resistance layer 43 are formed in the interlayer insulating film 44. Has been. On the interlayer insulating film 44, wiring layers 45 a and 45 b respectively connected to the resistance layer 43 through the openings K 41 and K 42 are formed, and are arranged so as to cover the steps of the interlayer insulating film 44. A line width detecting wiring layer 45c is formed.

  When the line width detection wiring layer 45 c is disposed so as to cover the step of the interlayer insulating film 44, the line width detection wiring layer 45 c can be folded over the resistance layer 43. Further, the line width detection wiring layer 45c may be configured such that at least one of the wiring width and the wiring interval changes at the folded portion. The wiring layers 45a and 45b and the line width detecting wiring layer 45c can be formed by patterning the same wiring material formed on the interlayer insulating film 44. As the material of the resistance layer 43, for example, polycrystalline silicon can be used, and as the material of the wiring layers 45a and 45b and the line width detecting wiring layer 45c, for example, Al can be used.

  Thus, by forming the line width detection wiring layer 45c on the characteristic evaluation test element group, the line width detection wiring layer 45c is arranged on the base step having the same shape and size as the actual resistance layer. This makes it possible to accurately estimate the thinness or disconnection of the wiring layer formed on the resistance layer without thoroughly inspecting the wafer, and the test in which the line width detecting wiring layer 45c is formed. It is not necessary to separately secure a space for arranging the element group on the wafer, and space saving can be achieved.

Further, by forming the wiring layers 45a and 45b and the line width detecting wiring layer 45c on the same wiring layer, the wiring layers 45a and 45b and the line width detecting wiring layer 45c can be formed at once. The line width detection wiring layer 45c can be disposed on the test element group in which the resistance layer 43 is formed without increasing the number of processes.
FIG. 7A is a cross-sectional view showing a schematic configuration of a semiconductor device according to the fifth embodiment of the present invention, FIG. 7B is a cross-sectional view taken along the line A5-A5 ′ of FIG. FIG.7 (c) is sectional drawing cut | disconnected by B5-B5 'line of Fig.7 (a).

  In FIG. 7, a lower electrode 53 is formed on a semiconductor substrate 51 through a base insulating film 52. An upper electrode 55 is formed on the lower electrode 53 so as to face the dielectric film 54. Note that the lower electrode 53 and the upper electrode 55 with the dielectric film 54 sandwiched therebetween can form a test element group for characteristic evaluation, and the lower electrode 53 and the upper electrode 55 are, for example, scribe lines of a semiconductor wafer. Can be placed on top.

  An interlayer insulating film 56 is formed on the semiconductor substrate 51 so as to cover the upper electrode 55, and the interlayer insulating film 56 has openings that expose end portions of the lower electrode 53 and the upper electrode 55, respectively. K51 and K52 are formed. On the interlayer insulating film 56, wiring layers 57a and 57b connected to the lower electrode 53 and the upper electrode 55 through the openings K51 and K52, respectively, are formed, and the step of the interlayer insulating film 56 is applied. A line width detection wiring layer 57c arranged in this manner is formed.

  When the line width detection wiring layer 57 c is disposed so as to cover the step of the interlayer insulating film 56, the line width detection wiring layer 57 c may be folded over the lower electrode 53 and the upper electrode 55. it can. Further, the line width detection wiring layer 57c may be configured such that at least one of the wiring width and the wiring interval changes at the folded portion. Further, the wiring layers 57 a and 57 b and the line width detecting wiring layer 57 c can be formed by patterning the same wiring material formed on the interlayer insulating film 56. As the material of the lower electrode 53 and the upper electrode 55, for example, polycrystalline silicon can be used, and as the material of the wiring layers 57a, 57b and the line width detecting wiring layer 57c, for example, Al is used. it can.

  Thus, by forming the line width detection wiring layer 57c on the characteristic evaluation test element group, the line width detection wiring layer 57c can be disposed on the base step having the same shape and size as the actual capacitor. This makes it possible to accurately estimate the thinning or disconnection of the wiring layer formed on the capacitor without inspecting the wafer thoroughly, and to create a test element group with a wiring layer for detecting the line width. It is not necessary to separately secure a space for placement on the wafer, and space can be saved.

  Further, by forming the wiring layers 57a and 57b and the line width detecting wiring layer 57c on the same wiring layer, the wiring layers 57a and 57b and the line width detecting wiring layer 57c can be formed at once. The line width detection wiring layer 57c can be arranged on the test element group in which the capacitor is formed without increasing the number of processes.

1 is a diagram showing a schematic configuration of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a plan view showing a method for arranging pad electrodes in the semiconductor device of FIG. 1. The figure which shows schematic structure of the semiconductor device which concerns on 2nd Embodiment of this invention. FIG. 4 is a plan view showing a method for arranging pad electrodes of the semiconductor device of FIG. 3. The figure which shows schematic structure of the semiconductor device which concerns on 3rd Embodiment of this invention. The figure which shows schematic structure of the semiconductor device which concerns on 4th Embodiment of this invention. The figure which shows schematic structure of the semiconductor device which concerns on 5th Embodiment of this invention.

Explanation of symbols

1, 11, 31, 41, 51 Semiconductor substrate, 2, 12, 34 Element isolation insulating film, 3, 13 Gate insulating film, 4, 14 Gate electrode, 5, 15 Side wall, 6a, 6b, 16a, 16b LDD layer 7a, 7b, 17a, 17b Source / drain layer, 8, 18, 20, 37, 44, 56 Interlayer insulating film, 9a-9c, 45a-45c, 57a-57c Wiring layer, 19a-19c, 36a-36c Lower layer Wiring layer, R1, R2, R3a to R3c Active region, K1, K2, K11, K12, K41, K42 openings, P1 to P5, P11 to P17 pad electrodes, 21, 38 Upper wiring layer, 32 N ⁺ buried layer, 33 N-well, 35b, 35c N ⁺ diffusion layer, 35a P ⁺ diffusion layer, 42 and 52 the base insulating film, 43 the resistance layer, 53 a lower electrode, 54 a dielectric film, 55 upper Very

Claims (15)

A test element group for characteristic evaluation formed on a semiconductor substrate;
A semiconductor device comprising: a line width detection wiring layer disposed so as to cover a step existing on the characteristic evaluation test element group.   2. The semiconductor device according to claim 1, wherein the line width detecting wiring layer is configured such that at least one of a wiring width and a wiring interval changes. The test element group for characteristic evaluation is
A gate electrode formed on the semiconductor substrate;
A source / drain layer formed on the semiconductor substrate so as to sandwich the gate electrode;
An interlayer insulating layer formed on the semiconductor substrate so as to cover the gate electrode;
A wiring layer for characteristic evaluation disposed on the interlayer insulating layer and connected to the source / drain layer;
The line width detecting wiring layer is disposed on the interlayer insulating layer so as to straddle the gate electrode, and is configured by the same wiring layer as the characteristic evaluation wiring layer. 2. The semiconductor device according to 2. A first pad electrode connected to the gate electrode;
A second pad electrode connected to the source / drain layer via the characteristic evaluation wiring layer;
A third pad electrode connected to the line width detection wiring layer,
4. The semiconductor device according to claim 3, wherein the active region in which the source / drain layers are formed and the first to third pad electrodes are arranged on the same straight line. The test element group for characteristic evaluation is
A gate electrode formed on the semiconductor substrate;
A source / drain layer formed on the semiconductor substrate so as to sandwich the gate electrode;
A first interlayer insulating layer formed on the semiconductor substrate so as to cover the gate electrode;
A lower wiring layer disposed on the first interlayer insulating layer and connected to the source / drain layer;
A second interlayer insulating layer disposed on the lower wiring layer,
The line width detecting wiring layer is
A first line width detecting wiring layer disposed on the first interlayer insulating layer so as to straddle the gate electrode and configured by the same wiring layer as the lower wiring layer;
3. The semiconductor device according to claim 1, further comprising: a second line width detection wiring layer configured by an upper wiring layer disposed on the second interlayer insulating layer. A first pad electrode connected to the gate electrode;
A second pad electrode connected to the source / drain layer via the characteristic evaluation wiring layer;
A third pad electrode connected to the first line width detection wiring layer;
A fourth pad electrode connected to the second line width detection wiring layer,
6. The semiconductor device according to claim 5, wherein the active region in which the source / drain layers are formed and the first to fourth pad electrodes are arranged on the same straight line. The test element group for characteristic evaluation is
An emitter layer formed on the semiconductor substrate;
A base layer formed on the semiconductor substrate;
A collector layer formed on the semiconductor substrate;
A lower wiring layer connected to each of the emitter layer, the base layer and the collector layer;
An interlayer insulating layer disposed on the lower wiring layer,
3. The semiconductor device according to claim 1, wherein the line width detection wiring layer is configured by an upper wiring layer disposed on the interlayer insulating layer so as to straddle the lower wiring layer. The test element group for characteristic evaluation is
A resistance layer formed on the semiconductor substrate;
An interlayer insulating layer formed on the semiconductor substrate so as to cover the resistance layer;
A wiring layer for characteristic evaluation disposed on the interlayer insulating layer and connected to the resistance layer;
The line width detection wiring layer is disposed on the interlayer insulating layer so as to straddle the resistance layer, and is configured by the same wiring layer as the characteristic evaluation wiring layer. 2. The semiconductor device according to 2. The test element group for characteristic evaluation is
A lower electrode formed on the semiconductor substrate;
An upper electrode arranged to face the lower electrode;
A dielectric film disposed between the lower electrode and the upper electrode;
An interlayer insulating layer formed on the semiconductor substrate so as to cover the upper electrode;
A wiring layer for characteristic evaluation disposed on the interlayer insulating layer and connected to the lower electrode and the upper electrode, respectively.
The line width detection wiring layer is disposed on the interlayer insulating layer so as to straddle the lower electrode and the upper electrode, and is configured by the same wiring layer as the characteristic evaluation wiring layer. Item 3. The semiconductor device according to Item 1 or 2. Forming a test element group for characteristic evaluation on a semiconductor substrate;
And a step of forming a line width detection wiring layer arranged so as to cover a step existing on the characteristic evaluation test element group. Forming a gate electrode on the semiconductor substrate;
Forming on the semiconductor substrate a source / drain layer disposed so as to sandwich the gate electrode;
Forming an interlayer insulating layer disposed on the semiconductor substrate so as to cover the gate electrode;
Forming openings in the interlayer insulating layer to expose the source / drain layers,
Forming a conductive film on the interlayer insulating layer;
By patterning the conductive film, a characteristic evaluation wiring layer connected to the source / drain layer through the opening is formed on the interlayer insulating layer, and disposed so as to straddle the gate electrode. And a step of forming a line width detecting wiring layer on the interlayer insulating layer. Forming a gate electrode on the semiconductor substrate;
Forming on the semiconductor substrate a source / drain layer disposed so as to sandwich the gate electrode;
Forming a first interlayer insulating layer disposed on the semiconductor substrate so as to cover the gate electrode;
Forming openings in the first interlayer insulating layer to expose the source / drain layers,
Forming a first conductive film on the first interlayer insulating layer;
By patterning the first conductive film, a characteristic evaluation wiring layer connected to the source / drain layer through the opening is formed on the first interlayer insulating layer and straddles the gate electrode. Forming a first line width detecting wiring layer arranged on the first interlayer insulating layer;
Forming a second interlayer insulating layer disposed on the semiconductor substrate so as to cover the characteristic evaluation wiring layer and the first line width detection wiring layer;
Forming a second conductive film on the second interlayer insulating layer;
Forming a second line width detection wiring layer disposed on the second interlayer insulating layer so as to straddle the first line width detection wiring layer by patterning the second conductive film. A method for manufacturing a semiconductor device. Forming a first impurity diffusion layer as an emitter layer in a semiconductor substrate;
Forming a second impurity diffusion layer serving as a base layer in the semiconductor substrate;
Forming a third impurity diffusion layer serving as a collector layer in the semiconductor substrate;
Forming a lower wiring layer connected to each of the emitter layer, the base layer and the collector layer;
Forming an interlayer insulating layer disposed on the semiconductor substrate so as to cover the lower wiring layer;
Forming a line width detecting wiring layer constituted by an upper wiring layer disposed so as to straddle the lower wiring layer on the interlayer insulating layer. Forming a resistance layer on the semiconductor substrate;
Forming an interlayer insulating layer disposed on the semiconductor substrate so as to cover the resistive layer;
Forming an opening in the interlayer insulating layer to expose the resistance layer;
Forming a conductive film on the interlayer insulating layer;
By patterning the conductive film, a wiring layer for characteristic evaluation connected to the resistance layer through the opening is formed on the interlayer insulating layer, and a line width disposed so as to straddle the resistance layer And a step of forming a detection wiring layer on the interlayer insulating layer. Forming a lower electrode on the semiconductor substrate;
Forming a dielectric film on the lower electrode;
Forming an upper electrode disposed to face the lower electrode through the dielectric film;
Forming an interlayer insulating layer disposed on the semiconductor substrate so as to cover the upper electrode;
Forming an opening in the interlayer insulating layer to expose the lower electrode and the upper electrode, and
Forming a conductive film on the interlayer insulating layer;
By patterning the conductive film, a characteristic evaluation wiring layer connected to the lower electrode and the upper electrode through the opening is formed on the interlayer insulating layer, and the lower electrode and the upper electrode are formed. And a step of forming a wiring layer for detecting line width on the interlayer insulating layer so as to extend over the interlayer insulating layer.

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