JP2006303107A - Light-emitting device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a light-emitting device capable of being easily mounted by shrinking a mounting area while reducing a mounting cost. <P>SOLUTION: The light-emitting device LE1 has a plurality of semiconductor light-emitting elements 1 and a laminated chip varistor 11. The laminated chip varistor 11 has a varistor element assembly 21, and a plurality of second external electrodes 27 and 28 formed on the external surface of the varistor element assembly 21. In the varistor element assembly 21, a plurality of varistors with varistor layers and first and second internal electrodes 31 and 41 arranged so as to hold the varistor layers are arranged along the specified direction. The second external electrodes 27 are connected to the first internal electrodes 31, and the second external electrodes 28 are connected to the second internal electrodes 41. The semiconductor light-emitting elements 1 are disposed on the laminated chip varistor 11, and connected to the second corresponding external electrodes 27 and 28 respectively so as to be connected in parallel with the corresponding varistor sections. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a light emitting device.

As this type of light emitting device, a device including a semiconductor light emitting element and a varistor connected in parallel to the semiconductor light emitting element is known (for example, see Patent Document 1). In the light emitting device described in Patent Document 1, the semiconductor light emitting element is protected from an ESD (Electrostatic Discharge) surge by a varistor connected in parallel.
Japanese Patent Laid-Open No. 2001-15815

  In recent years, light-emitting devices including a plurality of semiconductor light-emitting elements as light sources have begun to spread. Examples of the lighting device include an automobile marker lamp, a vehicle lamp, a traffic light, a general lighting fixture that replaces a fluorescent lamp and an incandescent lamp.

  When the light-emitting device includes a plurality of semiconductor light-emitting elements, it is necessary to connect a varistor in parallel for each semiconductor light-emitting element in order to protect each semiconductor light-emitting element from an ESD surge. That is, a plurality of varistors are mounted corresponding to a plurality of semiconductor light emitting elements.

  However, when a plurality of varistors are mounted, the mounting area of the varistor becomes large, which becomes a factor that hinders downsizing of the light-emitting device described above. Further, since it is necessary to mount a plurality of varistors, the mounting cost increases and the mounting process becomes complicated.

  It is an object of the present invention to provide a light-emitting device that can be easily mounted while reducing the mounting area and the mounting cost.

  The light-emitting device according to the present invention includes a plurality of semiconductor light-emitting elements and a multilayer chip varistor, and the multilayer chip varistor sandwiches the varistor layer with a varistor layer that exhibits voltage nonlinear characteristics. A plurality of varistor portions each having a plurality of internal electrodes to be arranged are formed on a single outer surface parallel to a predetermined direction among a stacked body in which a plurality of varistor portions are arranged along a predetermined direction. And a plurality of first external electrodes that are electrically connected to corresponding internal electrodes among the plurality of internal electrodes, and an outer surface that faces the outer surface on which the plurality of first external electrodes are formed. And a plurality of second external electrodes that are electrically connected to corresponding internal electrodes among the plurality of internal electrodes, and the plurality of internal electrodes are between adjacent internal electrodes among the plurality of internal electrodes. In each other A first electrode portion that fits, and an outer surface on which the plurality of first external electrodes are formed and an outer surface on which the plurality of second external electrodes are formed are extracted from the first electrode portion so as to be exposed. A plurality of first external electrodes and a plurality of second external electrodes are electrically connected to the first electrode portions of the corresponding internal electrodes through the second electrode portions. A plurality of semiconductor light emitting elements are arranged on the multilayer chip varistor, and the second external electrode corresponding to the second external electrode is connected in parallel to the corresponding varistor part among the plurality of varistor parts. Each of the electrodes is connected to each other.

  In the light emitting device according to the present invention, each varistor portion is connected in parallel to the corresponding semiconductor light emitting element among the plurality of semiconductor light emitting elements, so that each semiconductor light emitting element can be protected from an ESD surge.

  In the multilayer chip varistor included in the light emitting device according to the present invention, the multilayer body includes a plurality of varistor portions, and the plurality of first external electrodes are parallel to a predetermined direction on the outer surface of the multilayer body. It is formed on the outer surface. The plurality of first external electrodes are electrically connected to corresponding internal electrodes through the second electrode portion. Therefore, by mounting the outer surface on which the plurality of first external electrodes are formed facing the mounting surface of the external substrate, external device, etc., the plurality of varistor portions are attached to the external substrate, external device, etc. Will be implemented. As a result, the mounting area can be reduced when mounting a plurality of varistor portions. Moreover, the mounting cost for mounting a plurality of varistor portions can be reduced and mounting can be easily performed.

  In the present invention, the plurality of second external electrodes are formed on the outer surface opposite to the outer surface on which the plurality of first external electrodes are formed. The plurality of second external electrodes are electrically connected to corresponding internal electrodes through the second electrode portion. Thereby, a plurality of semiconductor light emitting elements can be easily mounted so as to be connected in parallel with the varistor part using the outer surface on which the plurality of second external electrodes are formed.

  By the way, the semiconductor light emitting device emits heat during the light emitting operation. When the semiconductor light emitting element becomes high temperature, the light emitting operation is affected. For this reason, it is necessary to dissipate the generated heat efficiently. In the present invention, since the multilayer chip varistor has the second external electrode connected to the semiconductor light emitting element and the internal electrode connected to the second external electrode, the heat generated in the semiconductor light emitting element is mainly the second. Will be transmitted to and diffused to the external electrode and the internal electrode. Thereby, the heat radiation path of the heat generated in the semiconductor light emitting element is expanded, and the heat generated in the semiconductor light emitting element can be efficiently dissipated.

  Preferably, the outer surface on which the plurality of first external electrodes are formed and the outer surface on which the plurality of second external electrodes are formed extend in a direction parallel to the stacking direction of the stacked body. In this case, the plurality of internal electrodes are juxtaposed along the direction in which the outer surface extends with respect to the outer surface on which the plurality of first external electrodes are formed and the outer surface on which the plurality of second external electrodes are formed. Will be. Thereby, with respect to each internal electrode, a heat radiation path from the internal electrode to the outer surface of the multilayer chip varistor is shortened, and heat can be more efficiently dissipated from the internal electrode.

  Preferably, the varistor layer contains ZnO as a main component. ZnO has a thermal conductivity comparable to that of alumina or the like normally used as a heat dissipation substrate, and has a relatively good thermal conductivity. Therefore, it is possible to suppress the heat dissipation from the internal electrode from being inhibited by the varistor layer.

Preferably, the varistor layer includes Pr, and the plurality of first external electrodes and the plurality of second external electrodes are formed on the outer surface of the multilayer body by co-firing with the multilayer body, and Pd It has an electrode layer containing. In this case, by simultaneous firing of the varistor element body and the electrode layer, an oxide of Pr and Pd, such as Pr ₂ Pd ₂ O ₅ or Pr ₄ PdO _7, is formed in the vicinity of the interface between the laminate and the external electrode. , Will exist. As a result, the adhesive strength between the laminate and the first and second external electrodes can be improved.

  The present inventors have conducted intensive research on a varistor capable of improving the adhesive strength between a varistor element body mainly composed of ZnO and an external electrode. As a result, depending on the material contained in the laminate (green body that becomes a laminate when fired) and the external electrode (conductive paste that becomes an external electrode when fired), the laminate and the external electrode It came to discover the new fact that adhesive strength changes.

  After the conductive paste is applied to the outer surface of the green body mainly composed of ZnO, these are fired to obtain a laminate and an external electrode. At this time, when the green body contains Pr (praseodymium) and the conductive paste contains Pd (palladium), the adhesive strength between the obtained varistor element body and the external electrode is improved.

  The effect of improving the adhesive strength between the laminate and the external electrode is considered to be caused by the following event during firing. When the green body and the conductive paste are fired, Pr contained in the green body moves near the surface of the green body, that is, near the interface between the green body and the conductive paste. And Pr which moved to the interface vicinity of a green body and an electrically conductive paste and Pd contained in an electrically conductive paste mutually diffuse. At this time, an oxide of Pr and Pd may be formed near the interface between the laminate and the external electrode. An anchor effect is produced by the oxide of Pr and Pd, and the adhesive strength between the laminate obtained by firing and the external electrode is improved.

  Preferably, the varistor layer includes Pr, and the plurality of first external electrodes and the plurality of second external electrodes are formed on the outer surface of the stacked body and have an electrode layer including Pd. An oxide of Pr contained in the varistor layer and Pd contained in the electrode layer exists in the vicinity of the interface between the body and the electrode layer. In this case, an oxide of Pr contained in the laminated body and Pd contained in the electrode layer is present in the vicinity of the interface between the laminated body and the external electrode, so that the laminated body, the first and second external electrodes, The adhesive strength can be improved.

  Preferably, the electrode layer is formed on the outer surface of the multilayer body by simultaneous firing with the multilayer body. In this case, an oxide of Pr contained in the varistor element body and Pd contained in the electrode layer can surely exist in the vicinity of the interface between the varistor element body and the first and second external electrodes.

  Preferably, the laminate has a substantially plate shape having a main surface of an outer surface on which a plurality of first external electrodes are formed and an outer surface on which a plurality of second external electrodes are formed. The distance between the outer surface on which the external electrode is formed and the outer surface on which the plurality of second external electrodes are formed is set smaller than the length in a predetermined direction of the laminate. In this case, the multilayer chip varistor can be reduced in height, and the light emitting device can be reduced in height.

  Preferably, the predetermined direction is a stacking direction of the varistor layers. Preferably, the predetermined direction is a direction parallel to the varistor layer.

  Preferably, the plurality of first external electrodes are two-dimensionally arranged on the outer surface on which the plurality of first external electrodes are formed, and the plurality of second external electrodes are the plurality of second external electrodes. Are two-dimensionally arranged on the outer surface.

  Preferably, each semiconductor light emitting element is disposed on the multilayer chip varistor by being bump-connected to the corresponding second external electrode. In this case, each semiconductor light emitting element can be mounted on the multilayer chip varistor very easily and simply.

  Preferably, the semiconductor light emitting element has a first conductivity type semiconductor region and a second conductivity type semiconductor region, and is applied between the first conductivity type semiconductor region and the second conductivity type semiconductor region. Emits light according to the applied voltage.

  The light-emitting device according to the present invention includes a plurality of semiconductor light-emitting elements and a multilayer chip varistor, and the multilayer chip varistor sandwiches the varistor layer exhibiting voltage nonlinear characteristics and the varistor layer. A plurality of varistor portions having a plurality of internal electrodes arranged in a predetermined direction, and a plurality of semiconductor light emitting elements are arranged on the multilayer chip varistor, Each of the varistor parts is connected in parallel to a corresponding varistor part.

  In the light emitting device according to the present invention, each varistor portion is connected in parallel to the corresponding semiconductor light emitting element among the plurality of semiconductor light emitting elements, so that each semiconductor light emitting element can be protected from an ESD surge.

  Further, in the multilayer chip varistor provided in the light emitting device according to the present invention, since the multilayer body includes a plurality of varistor portions, the mounting area can be reduced when mounting the plurality of varistor portions. Moreover, the mounting cost for mounting a plurality of varistor portions can be reduced and mounting can be easily performed.

  According to the present invention, it is possible to provide a light emitting device that can be easily mounted while reducing the mounting area and the mounting cost.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description, the same reference numerals are used for the same elements or elements having the same function, and redundant description is omitted.

  With reference to FIGS. 1-5, the structure of light-emitting device LE1 which concerns on this embodiment is demonstrated. FIG. 1 is a schematic top view showing the light emitting device according to this embodiment. FIG. 2 is a schematic bottom view showing the light emitting device according to this embodiment. FIG. 3 is a diagram for explaining a cross-sectional configuration along the line III-III in FIG. 1. FIG. 4 is a diagram for explaining a cross-sectional configuration along the line IV-IV in FIG. 1. FIG. 5 is a diagram for explaining a cross-sectional configuration along the line V-V in FIG. 1. FIG. 6 is a view for explaining a cross-sectional configuration along the line VI-VI in FIG.

  As shown in FIGS. 1 to 4, the light emitting device LE <b> 1 includes a plurality (four in the present embodiment) of semiconductor light emitting elements 1 and a multilayer chip varistor 11. Each semiconductor light emitting element 1 is arranged on a multilayer chip varistor 11.

  First, the configuration of the multilayer chip varistor 11 will be described. As shown in FIGS. 1 to 5, the multilayer chip varistor 11 includes a varistor element body 21 having a substantially rectangular plate shape, and a plurality (eight in the present embodiment) of first external electrodes 25, 26 and a plurality (eight in the present embodiment) of second external electrodes 27 and 28. Each of the first external electrodes 25 and 26 is formed on one main surface (outer surface) 22 of the varistor element body 21. Each of the second external electrodes 27 and 28 is formed on the other main surface (outer surface) 23 of the varistor element body 21. For example, the varistor element body 21 is set to have a length of about 2.0 mm, a width of about 1.0 mm, and a thickness of about 0.3 mm. The first external electrode 25 functions as an input terminal electrode of the multilayer chip varistor 11, and the first external electrode 26 functions as an output terminal electrode of the multilayer chip varistor 11. The second external electrodes 27 and 28 function as pad electrodes that are electrically connected to the semiconductor light emitting element 1 described later.

  The varistor element body 21 includes a plurality of varistor layers that exhibit voltage nonlinear characteristics (hereinafter referred to as “varistor characteristics”), and a plurality of first internal electrode layers 30 and second internal electrode layers 40, respectively. It is comprised as a laminated body. The first internal electrode layer 30 and the second internal electrode layer 40 of each layer are regarded as one internal electrode group, and the internal electrode group is in the varistor element body 21 in the stacking direction of the varistor layers (hereinafter simply referred to as “stacking direction”). A plurality (two in this embodiment) are arranged along the line. In each internal electrode group, the first internal electrode layer 30 and the second internal electrode layer 40 are arranged so that at least one varistor layer is interposed between the first internal electrode layer 30 and the second internal electrode layer 40. The electrode layers 40 are alternately arranged. Each internal electrode group is disposed so that at least one varistor layer is interposed between the internal electrode groups. In the actual multilayer chip varistor 11, the plurality of varistor layers are integrated so that the boundary between them cannot be visually recognized.

  The varistor layer contains ZnO (zinc oxide) as a main component and also includes rare earth metal elements, Co, group IIIb elements (B, Al, Ga, In), Si, Cr, Mo, alkali metal elements (K, K) as subcomponents. Rb, Cs) and simple earth metals such as alkaline earth metal elements (Mg, Ca, Sr, Ba) and element bodies containing these oxides. In the present embodiment, the varistor layer contains Pr, Co, Cr, Ca, Si, K, Al, and the like as subcomponents. As a result, the region of the varistor layer that overlaps the first internal electrode layer 30 and the second internal electrode layer 40 contains ZnO as a main component and Pr.

  In the present embodiment, Pr is used as the rare earth metal. Pr is a material for expressing varistor characteristics. The reason for using Pr is that voltage non-linearity is excellent and characteristic variation during mass production is small. Although content of ZnO in a varistor layer is not specifically limited, When the whole material which comprises a varistor layer is 100 mass%, it is 99.8-69.0 mass% normally. The thickness of the varistor layer is, for example, about 5 to 60 μm.

  As shown in FIG. 3, each first internal electrode layer 30 includes a plurality of (in this embodiment, two) first internal electrodes 31. Each first internal electrode 31 is formed at a predetermined distance from a side surface parallel to the stacking direction of the varistor element body 21 so as to be electrically insulated from each other. .

  Each first internal electrode 31 includes a first electrode portion 33 and second electrode portions 35a and 35b. The first electrode portion 33 overlaps a first electrode portion 43 of the second internal electrode 41 described later when viewed from the stacking direction. The first electrode portion 33 has a substantially rectangular shape. As shown in FIG. 5, the second electrode portion 35a is led out from the first electrode portion 33 so as to be exposed on the one main surface 22, and functions as a lead conductor. The second electrode portion 35 a is physically and electrically connected to the first external electrode 25.

  As shown in FIG. 5, the second electrode portion 35b is drawn out from the first electrode portion 33 so as to be exposed on the other main surface 23, and functions as a lead conductor. The second electrode portion 35 b is physically and electrically connected to the second external electrode 27. The first electrode portion 33 is electrically connected to the first external electrode 25 through the second electrode portion 35a and electrically connected to the second external electrode 27 through the second electrode portion 35b. Yes. The second electrode portions 35 a and 35 b are formed integrally with the first electrode portion 33.

  Each second internal electrode layer 40 includes a plurality of (in this embodiment, two) second internal electrodes 41 as shown in FIG. Each second internal electrode 41 is formed at a position having a predetermined distance from a side surface parallel to the stacking direction of the varistor element body 21 with a predetermined distance so as to be electrically insulated from each other. . As shown in FIG. 7, each second internal electrode 41 may be integrally formed so as to constitute one internal electrode. In this case, one external electrode 26 may be provided for each of the one internal electrode.

  Each second internal electrode 41 includes a first electrode portion 43 and second electrode portions 45a and 45b. The first electrode portion 43 overlaps the first electrode portion 33 of the first internal electrode 31 when viewed from the stacking direction. The first electrode portion 43 has a substantially rectangular shape. As shown in FIG. 6, the second electrode portion 45 a is drawn out from the first electrode portion 43 so as to be exposed on one main surface 22, and functions as a lead conductor. The second electrode portion 45 a is physically and electrically connected to the first external electrode 26.

  As shown in FIG. 6, the second electrode portion 45b is drawn out from the first electrode portion 43 so as to be exposed at the other main surface 23, and functions as a lead conductor. The second electrode portion 45 b is physically and electrically connected to the second external electrode 28. The first electrode portion 43 is electrically connected to the first external electrode 26 through the second electrode portion 45a and is electrically connected to the second external electrode 28 through the second electrode portion 45b. Yes. The second electrode portions 45 a and 45 b are formed integrally with the first electrode portion 43.

  The first and second internal electrodes 31 and 41 include a conductive material. Although it does not specifically limit as a electrically conductive material contained in the 1st and 2nd internal electrodes 31 and 41, It is preferable to consist of Pd or an Ag-Pd alloy. The thickness of the first and second internal electrodes 31 and 41 is, for example, about 0.5 to 5 μm.

  The first outer electrodes 25 and 26 are two-dimensionally arranged on one main surface 22 in M rows and N columns (each of the parameters M and N is an integer of 2 or more). In the present embodiment, the first external electrodes 25 and 26 are two-dimensionally arranged in 4 rows and 2 columns. The first external electrode 25 and the first external electrode 26 are arranged on one main surface 22 with a predetermined interval in a direction perpendicular to the stacking direction of the varistor layers and parallel to the other main surface 22. Has been. The first external electrodes 25 and 26 have a rectangular shape (in this embodiment, a square shape). For example, the length of each side of the first external electrodes 25 and 26 is set to about 300 μm, and the thickness is set to about 5 μm.

  The second external electrodes 27 and 28 are two-dimensionally arranged on one main surface 23 in M rows and N columns (each of parameters M and N is an integer of 2 or more). In the present embodiment, the second external electrodes 27 and 28 are two-dimensionally arranged in 4 rows and 2 columns. The second external electrode 27 and the second external electrode 28 are arranged on the other main surface 23 with a predetermined interval in a direction perpendicular to the stacking direction of the varistor layer and parallel to the other main surface 23. Has been. The second external electrodes 27 and 28 have a rectangular shape (in this embodiment, a square shape). For example, the length of each side of the second external electrodes 27 and 28 is set to about 300 μm, and the thickness is set to about 5 μm.

  The external electrodes 25 to 28 have first electrode layers 25a to 28a and second electrode layers 25b to 28b, respectively. The first electrode layers 25a to 28a are formed on the outer surface of the varistor element body 21, and contain Pd. The first electrode layers 25a to 28a are formed by firing a conductive paste as will be described later. As the conductive paste, a mixture of a metal powder containing Pd particles as a main component with an organic binder and an organic solvent is used. The metal powder may be mainly composed of Ag—Pd alloy particles.

  The second electrode layers 25b to 28b are formed on the first electrode layers 25a to 28a by a printing method or a plating method. The second electrode layers 25b to 28b are made of Au or Pt. In the case of using the printing method, a conductive paste in which an organic binder and an organic solvent are mixed in a metal powder mainly composed of Au particles or Pt particles is prepared, and the conductive paste is applied to the first electrode layers 25a to 28a. The second electrode layers 25b to 28b are formed by printing and baking or baking. When the plating method is used, the second electrode layers 25b to 28b are formed by vapor-depositing Au or Pt by a vacuum plating method (vacuum evaporation method, sputtering method, ion plating method, or the like). The second electrode layers 25b to 28b may be configured as a Pt / Au laminate.

  As described above, the first electrode portion 33 of the first internal electrode 31 and the first electrode portion 43 of the third internal electrode 41 are the first electrode portions 33 of the adjacent first internal electrodes 31. And overlap each other. Therefore, a region overlapping the first electrode portion 33 and the first electrode portion 43 in the varistor layer functions as a region that develops varistor characteristics. In the multilayer chip varistor 11 having the above-described configuration, the first electrode portion 33, the first electrode portion 43, and a region overlapping the first electrode portion 33 and the first electrode portion 43 in the varistor layer. One varistor portion is formed.

  There are a plurality of varistor portions formed by the first electrode portions 33 and 43 and regions of the varistor layer overlapping the first electrode portions 33 and 43 along the stacking direction of the varistor layers (in this embodiment, two varistor portions). ) Will be arranged. In addition, a plurality of varistor portions constituted by the first electrode portions 33 and 43 and a region of the varistor layer overlapping the first electrode portions 33 and 43 are arranged along a direction parallel to the varistor layer (in the present embodiment, 2).

  The pair of main surfaces 22 and 23 of the varistor element body 21 are parallel to the direction in which the above-described varistor portion is disposed, that is, the direction in which the varistor layers are stacked and the direction parallel to the varistor layers. As described above, the varistor element body 21 has a plate shape having a pair of main surfaces 22 and 23. The distance between the pair of main surfaces 22 and 23 is set to be smaller than the length in the direction in which the varistor part in the varistor element body 21 is arranged, that is, in the direction in which the varistor layers are stacked and in the direction parallel to the varistor layers. Yes. The distance between the pair of main surfaces 22 and 23 corresponds to the thickness of the varistor element body 21.

  Next, a manufacturing process of the multilayer chip varistor 11 having the above-described configuration will be described with reference to FIGS. FIG. 8 is a flowchart for explaining the manufacturing process of the multilayer chip varistor according to the present embodiment. FIG. 9 is a view for explaining the manufacturing process of the multilayer chip varistor according to the present embodiment.

  First, after weighing ZnO, which is a main component constituting the varistor layer, and trace additives such as Pr, Co, Cr, Ca, Si, K, and Al metals or oxides so as to have a predetermined ratio. The varistor material is adjusted by mixing the components (step S101). Then, an organic binder, an organic solvent, an organic plasticizer, etc. are added to this varistor material, and it mixes and grinds for about 20 hours using a ball mill etc., and obtains a slurry.

  The slurry is applied onto a film made of, for example, polyethylene terephthalate by a known method such as a doctor blade method, and then dried to form a film having a thickness of about 30 μm. The film thus obtained is peeled from the film to obtain a green sheet (step S103).

  Next, a plurality of electrode portions corresponding to the first internal electrodes 31 (a number corresponding to the number of divided chips described later) are formed on the green sheet (step S105). Similarly, a plurality of electrode portions corresponding to the second internal electrode 41 (a number corresponding to the number of divided chips described later) are formed on different green sheets (step S105). The electrode portions corresponding to the first and second internal electrodes 31 and 41 are printed by a printing method such as screen printing with a conductive paste in which a metal powder mainly composed of Pd particles, an organic binder, and an organic solvent is mixed. It is formed by drying.

  Next, a sheet laminate is formed by stacking each green sheet on which electrode portions are formed and a green sheet on which electrode portions are not formed in a predetermined order (step S107). The sheet laminate thus obtained is cut into chips, and a plurality of divided green bodies GL1 (see FIG. 9) are obtained (step S109). In the obtained green body GL1, a green sheet GS1 in which an electrode portion EL1 corresponding to the first internal electrode 31 is formed, a green sheet GS2 in which an electrode portion EL2 corresponding to the second internal electrode 41 is formed, A green sheet GS3 on which the electrode portions EL1 and EL2 are not formed is sequentially laminated. A plurality of green sheets GS3 positioned between the green sheets GS1 and GS2 may be stacked or may not be stacked.

  Next, the conductive paste for the first electrode layers 25a to 28a of the external electrodes 25 to 28 and the conductive paste for the second electrode layers 25b to 28b of the external electrodes 25 to 28 are formed on the outer surface of the green body GL1. (Step S111). Here, a conductive paste is printed on one main surface of the green body GL1 so as to be in contact with the corresponding electrode portions EL1 and EL2, and then dried, thereby drying the first electrode layer 25a, An electrode portion corresponding to 26a is formed. Then, the conductive paste is printed on the electrode portions corresponding to the first electrode layers 25a and 26a by a screen printing method, and then dried, so that the electrode portions corresponding to the second electrode layers 25b and 26b are formed. Form. In addition, a conductive paste is printed on the other main surface of the green body GL1 so as to be in contact with the corresponding electrode portions EL1 and EL2 by a screen printing method, and then dried to thereby form the first electrode layers 27a and 28a. The electrode part corresponding to is formed. Then, after the conductive paste is printed on the electrode portions corresponding to the first electrode layers 27a and 28a by the screen printing method, the electrode portions corresponding to the second electrode layers 27b and 28b are dried by drying. Form.

  As described above, the conductive paste for the first electrode layers 25a to 28a is a mixture of an organic binder and an organic solvent in a metal powder mainly composed of Ag-Pd alloy particles or Pd particles. Can do. As described above, the conductive paste for the second electrode layers 25b to 28b may be a mixture of a metal powder containing Pt particles as a main component and an organic binder and an organic solvent. These conductive pastes do not contain glass frit.

  Next, the green body GL1 provided with the conductive paste was subjected to a heat treatment at 180 to 400 ° C. for about 0.5 to 24 hours to remove the binder, and then further to 1000 to 1400 ° C. and 0. Baking is performed for about 5 to 8 hours (step S113), and the varistor element body 21, the first electrode layers 25a to 28a, and the second electrode layers 25b to 28b are obtained. By this firing, the green sheets GS1 to GS3 in the green body GL1 become varistor layers. The electrode portion EL <b> 1 becomes the first internal electrode 31. The electrode portion EL <b> 2 becomes the second internal electrode 41.

  Through the above process, the multilayer chip varistor 11 is obtained. Note that alkali metal (for example, Li, Na, etc.) may be diffused from the surface of the varistor element body 21 after firing.

  Next, the configuration of each semiconductor light emitting element 1 will be described with reference to FIGS.

  Each semiconductor light emitting element 1 is a light emitting diode (LED: Light-Emitting Diode) of a GaN (gallium nitride) semiconductor, and includes a substrate 2 and a layer structure LS formed on the substrate 2. GaN-based semiconductor LEDs are well known and will be described briefly. The substrate 2 is an optically transparent and electrically insulating substrate made of sapphire. The layer structure LS includes an n-type (first conductivity type) semiconductor region 3, a light emitting layer 4, and a p-type (second conductivity type) semiconductor region 5 which are stacked. The semiconductor light emitting element 1 emits light according to a voltage applied between the n-type semiconductor region 3 and the p-type semiconductor region 5.

  The n-type semiconductor region 3 includes an n-type nitride semiconductor. In this embodiment, the n-type semiconductor region 3 is formed by epitaxially growing GaN on the substrate 2 and has an n-type conductivity by adding an n-type dopant such as Si. Further, the n-type semiconductor region 3 may have a composition such that the refractive index is smaller than that of the light emitting layer 4 and the band gap is increased. In this case, the n-type semiconductor region 3 serves as a lower cladding for the light emitting layer 4.

  The light emitting layer 4 is formed on the n-type semiconductor region 3, and carriers (electrons and holes) supplied from the n-type semiconductor region 3 and the p-type semiconductor region 5 are recombined to emit light in the light-emitting region. Is generated. The light emitting layer 4 can have, for example, a multiple quantum well (MQW) structure in which barrier layers and well layers are alternately stacked over a plurality of periods. In this case, the barrier layer and the well layer are made of InGaN, and the band gap of the barrier layer is configured to be larger than the band gap of the well layer by appropriately selecting the composition of In (indium). The light emitting region is generated in a region where carriers are injected in the light emitting layer 4.

  The p-type semiconductor region 5 includes a p-type nitride semiconductor. In the present embodiment, the p-type semiconductor region 5 is formed by epitaxially growing AlGaN on the light emitting layer 4 and has p-type conductivity by adding a p-type dopant such as Mg. The p-type semiconductor region 5 may have a composition that has a refractive index smaller than that of the light emitting layer 4 and a larger band gap. In this case, the p-type semiconductor region 5 serves as an upper cladding for the light emitting layer 4.

  A cathode electrode 6 is formed on the n-type semiconductor region 3. The cathode electrode 6 is made of a conductive material and realizes ohmic contact with the n-type semiconductor region 3. An anode electrode 7 is formed on the p-type semiconductor region 5. The anode electrode 7 is made of a conductive material, and has an ohmic contact with the p-type semiconductor region 5. Bump electrodes 8 are formed on the cathode electrode 6 and the anode electrode 7.

  In the semiconductor light emitting device 1 having the above-described configuration, when a predetermined voltage is applied between the anode electrode 7 (bump electrode 8) and the cathode electrode 6 (bump electrode 8) and a current flows, the light emitting region 4 emits light. Luminescence will occur.

  Each semiconductor light emitting element 1 is bump-connected to a corresponding pair of second external electrodes 27 and 28. That is, the cathode electrode 6 is electrically and physically connected to the second external electrode 28 via the bump electrode 8. The anode electrode 7 is electrically and physically connected to the second external electrode 27 through the bump electrode 8. As a result, the varistor portion constituted by the first electrode portions 33 and 43 and the region of the varistor layer overlapping the first electrode portions 33 and 43 is connected in parallel to the semiconductor light emitting element 1.

  As described above, according to the present embodiment, each varistor part is connected in parallel to the semiconductor light emitting element 1 corresponding to each varistor part, so that each semiconductor light emitting element 1 can be protected from an ESD surge.

  In the present embodiment, the varistor element body 21 includes a plurality of varistor portions, and a plurality of first external electrodes 25 and 26 are formed on one main surface 22 of the varistor element body 21. The plurality of first external electrodes 25 and 26 are electrically connected to the corresponding internal electrodes 31 and 41 through the second electrode portions 35a and 45a. Therefore, by mounting the main surface 22 on which the plurality of first external electrodes 25 and 26 are formed facing the mounting surface of the external substrate, external device, etc., the plurality of varistor portions can be It will be mounted on external devices. As a result, the mounting area can be reduced when mounting a plurality of varistor portions. Moreover, the mounting cost for mounting a plurality of varistor portions can be reduced and mounting can be easily performed.

  By the way, in the multilayer chip varistor 11 of the present embodiment, the first external electrode 25 functioning as an input terminal electrode and the external electrode 26 functioning as a first output terminal electrode are both main elements of the varistor element body 21. Arranged on the surface 22. That is, the multilayer chip varistor 11 is a multilayer chip varistor formed as a BGA (Ball Grid Array) package. The multilayer chip varistor 11 electrically and mechanically connects the external electrodes 25 and 26 and lands corresponding to the first external electrodes 25 and 26 using solder balls, bump electrodes, or the like. It is mounted on an external board or an external device.

  In the present embodiment, the plurality of second external electrodes 27 and 28 are formed on the other main surface 23 facing the main surface 22 on which the plurality of first external electrodes 25 and 26 are formed. The plurality of second external electrodes 27 and 28 are electrically connected to the corresponding internal electrodes 31 and 41 through the second electrode portions 35b and 45b. Thereby, the plurality of semiconductor light emitting elements 1 can be easily mounted so as to be connected in parallel to the varistor portion using the outer surface on which the plurality of second external electrodes 27 and 28 are formed.

  By the way, the semiconductor light emitting element 1 emits heat during the light emitting operation. When the semiconductor light emitting element 1 becomes high temperature, the light emitting operation is affected. For this reason, it is necessary to dissipate the generated heat efficiently. In the present embodiment, the multilayer chip varistor 11 is connected to the semiconductor light emitting element 1 with the second external electrodes 27, 28 and the first and second internal electrodes 31, 41 connected to the second external electrodes 27, 28. Therefore, the heat generated in the semiconductor light emitting device 1 is mainly transmitted to and dissipated in the second external electrodes 27 and 28 and the first and second internal electrodes 31 and 41. Thereby, the heat radiation path of the heat generated in the semiconductor light emitting element 1 is expanded, and the heat generated in the semiconductor light emitting element 1 can be efficiently dissipated.

  In the present embodiment, one main surface 22 and the other main surface 23 extend in a direction parallel to the stacking direction of the varistor element body 21, that is, the stacking direction of the varistor layers. Thus, the first and second internal electrodes 31 and 41 are juxtaposed along the direction in which the one main surface 22 and the other main surface 23 extend with respect to the one main surface 22 and the other main surface 23. The Rukoto. As a result, for each internal electrode 31, 41, a heat radiation path from each internal electrode 31, 41 to one main surface 22 and the other main surface 23 of the varistor element body 21, that is, to the outer surface of the multilayer chip varistor 11. The heat radiation path of the first and second internal electrodes 31 and 41 can be more efficiently dissipated.

  In the present embodiment, the varistor layer contains ZnO as the main component. ZnO has a thermal conductivity comparable to that of alumina or the like normally used as a heat dissipation substrate, and has a relatively good thermal conductivity. Therefore, it is possible to suppress the heat dissipation from the first and second internal electrodes 31 and 41 from being inhibited by the varistor layer.

  According to the present embodiment, the green body GL1 includes Pr, the conductive paste for the first electrode layers 25a to 28a of the first and second external electrodes 25 to 28 includes Pd, and the conductive paste includes The applied green body GL1 is baked to obtain the varistor element body 21 containing Pr and the first electrode layers 25a to 28a containing Pd. Therefore, the varistor element body 21 and the first electrode layers 25a to 28a It will be fired simultaneously. Thereby, the adhesive strength between the varistor element body 21 and the first and second external electrodes 25 to 28 (first electrode layers 25a to 28a) can be improved.

The effect of improving the adhesive strength between the varistor element body 21 and the first and second external electrodes 25 to 28 is considered to be caused by the following event during firing. When the green body GL1 and the conductive paste are fired, Pr contained in the green body GL1 moves near the surface of the green body GL1, that is, near the interface between the green body GL1 and the conductive paste. Then, Pr moved to the vicinity of the interface between the green body GL1 and the conductive paste and Pd contained in the conductive paste mutually diffuse. When Pr and Pd are interdiffused, an oxide of Pr and Pd (for example, Pr ₂ Pd) is formed in the vicinity (including the interface) between the varistor element body 21 and the first and second external electrodes 25 to 28. _{sometimes 2} O ₅ and _Pr 4 PdO _7, etc.) are formed. An anchor effect is generated by the oxide of Pr and Pd, and the adhesive strength between the varistor element body 21 obtained by firing and the first and second external electrodes 25 to 28 is improved.

  A multilayer chip varistor formed as a BGA package has a particularly small area of an external electrode functioning as an input / output terminal electrode or a ground terminal electrode. For this reason, the adhesive strength between the varistor element body and the external electrode is lowered, and the external electrode may be peeled off from the varistor element body. However, in the multilayer chip varistor 11 of this embodiment, as described above, the adhesive strength between the varistor element body 21 and the first and second external electrodes 25 to 28 (first electrode layers 25a to 28a) is improved. Therefore, the first and second external electrodes 25 to 28 are not peeled off from the varistor element body 21.

  When the conductive paste for forming the first electrode layers 25a to 28a contains glass frit, a glass component may be deposited on the surfaces of the first electrode layers 25a to 28a during firing. Plating properties and solderability may be deteriorated. However, in the present embodiment, since the conductive paste for forming the first electrode layers 25a to 28a does not include glass frit, the plating property and the solderability are not deteriorated.

  In the present embodiment, the varistor element body 21 is substantially plate-shaped having a pair of main surfaces 22 and 23, and the distance between the pair of main surfaces 22 and 23 is the direction in which the varistor part in the varistor element body 21 is arranged. It is set smaller than the length at. Thereby, it is possible to reduce the height of the multilayer chip varistor 11, and it is also possible to reduce the height of the light emitting device LE1.

  In the present embodiment, each semiconductor light emitting element 1 is disposed on the multilayer chip varistor 11 by being bump-connected to the corresponding second external electrodes 27 and 28. Thereby, the mounting of each semiconductor light emitting element 1 on the multilayer chip varistor 11 can be performed very easily and simply.

  In the multilayer chip varistor 11 according to this embodiment, the varistor element body 21 (varistor layer) does not contain Bi. The reason why the varistor element body 21 does not contain Bi is as follows. When the varistor element body contains ZnO as a main component and contains Bi, and the external electrode has an electrode layer formed on the outer surface of the varistor element body by simultaneous firing with the varistor element body and including Pd, By simultaneous firing of the varistor element body and the electrode layer, Bi and Pd are alloyed, and an alloy of Bi and Pd is formed at the interface between the varistor element body and the electrode layer. The alloy of Bi and Pd has particularly poor wettability with the varistor element body, and acts to reduce the adhesive strength between the varistor element body and the electrode layer. For this reason, it becomes difficult to ensure the adhesive strength between the varistor element body and the electrode layer (external electrode) in a desired state.

  The preferred embodiments of the present invention have been described above, but the present invention is not necessarily limited to these embodiments. For example, the number of semiconductor light emitting elements 1 arranged on the multilayer chip varistor 11 is not limited to the above-described four, and may be two or more. In this case, the number of varistor portions and external electrodes 25 to 28 is a number corresponding to the number of semiconductor light emitting elements 1.

  Each varistor portion of the multilayer chip varistor 11 described above has a pair of internal electrodes 31 and 41, but is not limited thereto. Each varistor portion may have a plurality of first internal electrodes 31 and a plurality of second internal electrodes 41.

  In the multilayer chip varistor 11 described above, a plurality of varistor portions are arranged along the direction in which the varistor layers are laminated and the direction parallel to the varistor layers, but this is not limitative. A plurality of varistor portions may be arranged only in the stacking direction of the varistor layers. A plurality of varistor portions may be arranged only in a direction parallel to the varistor layer. Further, the number of varistor portions arranged is not limited to the number described above.

  In the present embodiment, a GaN-based semiconductor LED is used as the semiconductor light emitting element 1, but the present invention is not limited to this. As the semiconductor light emitting element 1, for example, a nitride semiconductor LED other than GaN-based (for example, InGaNAs-based semiconductor LED), a compound semiconductor LED other than nitride-based, or a laser diode (LD) may be used. .

It is a schematic top view which shows the multilayer chip varistor concerning this embodiment. It is a schematic bottom view which shows the multilayer chip varistor concerning this embodiment. It is a figure for demonstrating the cross-sectional structure along the III-III line in FIG. It is a figure for demonstrating the cross-sectional structure along the IV-IV line | wire in FIG. It is a figure for demonstrating the cross-sectional structure along the VV line in FIG. It is a figure for demonstrating the cross-sectional structure along the VI-VI line in FIG. It is a figure which shows the modification of a 2nd internal electrode. It is a flowchart for demonstrating the manufacturing process of the multilayer chip varistor concerning this embodiment. It is a figure for demonstrating the manufacturing process of the multilayer chip varistor concerning this embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor light-emitting device, 11 ... Multi-layer chip varistor, 21 ... Varistor element body, 22 ... One main surface, 23 ... Other main surface, 25, 26 ... First external electrode, 25a, 26a ... First Electrode layer, 25b, 26b ... second electrode layer, 27, 28 ... second external electrode, 27a, 28a ... first electrode layer, 27b, 28b ... second electrode layer, 31 ... first internal electrode 33 ... first electrode portion, 35a, 35b ... second electrode portion, 41 ... second internal electrode, 43 ... first electrode portion, 45a, 45b ... second electrode portion, LE1 ... light emitting device.

Claims (13)

A plurality of semiconductor light emitting devices and a multilayer chip varistor,
The multilayer chip varistor is
A laminated body in which a plurality of varistor portions having a varistor layer that exhibits voltage nonlinear characteristics and a plurality of internal electrodes arranged so as to sandwich the varistor layer are arranged along a predetermined direction;
A plurality of first external electrodes formed on one outer surface parallel to the predetermined direction among the outer surfaces of the laminated body and electrically connected to corresponding internal electrodes among the plurality of internal electrodes When,
A plurality of second external electrodes formed on an outer surface opposite to the outer surface on which the plurality of first external electrodes are formed and electrically connected to corresponding internal electrodes among the plurality of internal electrodes. An electrode, and
The plurality of internal electrodes are
A first electrode portion overlapping between adjacent internal electrodes of the plurality of internal electrodes;
The second electrode drawn from the first electrode portion so as to be exposed on the outer surface on which the plurality of first external electrodes are formed and on the outer surface on which the plurality of second external electrodes are formed. Including, and
The plurality of first external electrodes and the plurality of second external electrodes are electrically connected to the first electrode portions of the corresponding internal electrodes through the second electrode portions;
The plurality of semiconductor light emitting elements are arranged on the multilayer chip varistor, and the second corresponding one of the plurality of second external electrodes is connected in parallel to the corresponding varistor part among the plurality of varistor parts. A light emitting device connected to each of the external electrodes.   The outer surface on which the plurality of first external electrodes are formed and the outer surface on which the plurality of second external electrodes are formed extend in a direction parallel to the stacking direction of the stacked body. The light emitting device according to claim 1.   The light-emitting device according to claim 1, wherein the varistor layer contains ZnO as a main component. The varistor layer comprises Pr;
The plurality of first external electrodes and the plurality of second external electrodes have an electrode layer formed on the outer surface of the multilayer body by being simultaneously fired with the multilayer body and containing Pd. The light-emitting device according to claim 3. The varistor layer comprises Pr;
The plurality of first external electrodes and the plurality of second external electrodes have an electrode layer formed on the outer surface of the laminate and including Pd,
4. The light emitting device according to claim 3, wherein an oxide of Pr contained in the varistor layer and Pd contained in the electrode layer exists in the vicinity of an interface between the stacked body and the electrode layer.   The light emitting device according to claim 5, wherein the electrode layer is formed on the outer surface of the multilayer body by being simultaneously fired with the multilayer body. The laminate is substantially plate-shaped with the outer surface on which the plurality of first external electrodes are formed and the outer surface on which the plurality of second external electrodes are formed as main surfaces,
The distance between the outer surface on which the plurality of first external electrodes are formed and the outer surface on which the plurality of second external electrodes are formed is larger than the length of the multilayer body in the predetermined direction. The light emitting device according to claim 1, wherein the light emitting device is set to be small.   The light-emitting device according to claim 1, wherein the predetermined direction is a stacking direction of the varistor layers.   The light-emitting device according to claim 1, wherein the predetermined direction is a direction parallel to the varistor layer. The plurality of first external electrodes are two-dimensionally arranged on the outer surface on which the plurality of first external electrodes are formed,
2. The light emitting device according to claim 1, wherein the plurality of second external electrodes are two-dimensionally arranged on the outer surface on which the plurality of second external electrodes are formed.   2. The light emitting device according to claim 1, wherein each of the semiconductor light emitting elements is disposed on the multilayer chip varistor by being bump-connected to the corresponding second external electrode.   The semiconductor light emitting element has a first conductivity type semiconductor region and a second conductivity type semiconductor region, and is applied between the first conductivity type semiconductor region and the second conductivity type semiconductor region. The light emitting device according to claim 1, wherein the light emitting device emits light according to a voltage. A plurality of semiconductor light emitting devices and a multilayer chip varistor,
The multilayer chip varistor is a multilayer in which a plurality of varistor portions each having a varistor layer exhibiting voltage nonlinear characteristics and a plurality of internal electrodes arranged so as to sandwich the varistor layer are arranged along a predetermined direction. Have a body,
The light-emitting device, wherein the plurality of semiconductor light-emitting elements are arranged on the multilayer chip varistor and are connected in parallel to the corresponding varistor part among the plurality of varistor parts.

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