JP2006294864A - Nonvolatile semiconductor storage device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor device and a manufacturing method thereof for enabling speeding up writing while suppressing deterioration in the rewritable number of times and for assuring higher reliability. <P>SOLUTION: The nonvolatile semiconductor device 100 comprises a first capacitor 31 connected at one end thereof to a floating node 30, a detecting transistor 41 connected at a gate electrode thereof to the floating node 30, and a second capacitor 32 connected at one end thereof to the floating node 30 and also connected at the other end thereof to a drain of a detecting transistor 41. An upper first interlayer insulating film ILD1 of the second capacitor 32 is formed with the HDPCVD (High-Density-Plasma-Chemical-Vapor-Deposition) method. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device and a manufacturing method thereof.

  In an LSI (Large Scale Integrated circuit) manufacturing process, a BPSG (Boro-Phospho Silicate Glass) film is used as a planarized interlayer insulating film under a metal wiring. However, the formation of the BPSG film requires a high-temperature heat treatment and may cause the already optimized silicide to react again. In this case, a phenomenon peculiar to the material such as a fine line effect and aggregation is caused. This increases the resistance of the material that should have been metallized, resulting in a decrease in yield.

In addition, before forming the BPSG film, an oxide film having excellent step coverage may be formed in order to prevent generation of void. In this case, for example, TEOS (TetraEthylOrthoSilisate) -O ₃ CVD method is used. However, in this method, hydrogen atoms are easily taken into the oxide film when the TEOS film is formed. For this reason, when the TEOS film is formed in the vicinity of the floating gate, the incorporated hydrogen atoms affect the electrons injected into the floating gate, and there is a risk of destroying the retained data. Further, when the TEOS film is thickened to cover the step, the flatness is deteriorated and the influence on the wiring layer exposure is increased. In this case, it cannot be used for a process of, for example, 0.25 μm or less.

Further, when considering the writing speed as the nonvolatile semiconductor memory device, for example, when the voltage applied to the tunnel film is increased, the tunnel film is remarkably deteriorated, and the number of rewritable times is reduced. That is, it has been difficult to increase the writing speed in a field where high reliability is required.
JP 2003-68734 A

  The present invention has been made in view of the technical problems as described above. The object of the present invention is to increase the writing speed while suppressing the deterioration of the number of rewritable times, and to provide a highly reliable nonvolatile memory. It is an object to provide a conductive semiconductor memory device and a method for manufacturing the same.

  The present invention includes a first capacitor having one end connected to the floating node, a detection transistor having a gate electrode connected to the floating node, one end connected to the floating node, and the other end connected to the floating node. A second capacitor connected to the drain of the detection transistor, and the first interlayer insulating film above the second capacitor is formed by HDPCVD (High-Density-Plasma-Chemical-Vapor-Deposition) method The present invention relates to a formed nonvolatile semiconductor memory device.

  Thereby, a trap region can be formed in the oxide film of the second capacitor. For this reason, it is possible to improve the writing speed without increasing the writing voltage. In addition, since the trap region can be formed by the HDPCVD method in the process of forming the first interlayer insulating film, it is not necessary to prepare a separate step for forming the trap region. For this reason, this invention is excellent also in cost performance.

  In addition, since the HDPCVD process is performed at a low temperature, the first interlayer insulating film can be formed without leaving a thermal history in each layer. This makes it possible to maintain the concentration of the impurity diffusion region, prevent a decrease in the capacitance value of each capacitor, and maintain a stable write operation.

  In the present invention, the first interlayer insulating film may be formed between a polysilicon layer forming an upper electrode of the second capacitor and a metal wiring layer.

  Thereby, the first interlayer insulating film having excellent flatness on the fine wiring can be formed by low-temperature processing. That is, it can be applied to a miniaturized process.

  In the present invention, the first interlayer insulating film may be formed between a second interlayer insulating film formed above the polysilicon layer and a metal wiring layer.

  This makes it possible to form the first interlayer insulating film having excellent step coatability, and thus it is possible to prevent the occurrence of VOID by low temperature processing.

  In the present invention, the metal wiring layer may be formed above the polysilicon layer without interposing a TEOS (TetraEthylOrthoSilisate) film.

  Thus, the first interlayer insulating film can be formed without leaving a thermal history in each layer, and adverse effects on the charge injected into the floating node can be prevented.

  In the present invention, the metal wiring layer may be formed above the polysilicon layer without interposing a BPSG (Boro-Phospho Silicate Glass) film.

  As a result, the first interlayer insulating film can be formed without leaving a thermal history in each layer, and the occurrence of VOID can be prevented by low-temperature processing.

  In the present invention, the thickness of the second capacitor insulating film formed between the upper electrode and the lower electrode of the second capacitor is formed between the upper electrode and the lower electrode of the first capacitor. A charge trap region may be formed in the second capacitor insulating film by a bias applied to the substrate by the HDPCVD method.

  As a result, it is possible to reduce the writing voltage while suppressing a decrease in writing speed. That is, the deterioration of the tunnel film of the second capacitor can be prevented, and the deterioration of the number of rewritable times can be suppressed. In addition, the power consumption of the nonvolatile semiconductor memory device can be reduced.

  In the present invention, the area of the region where the second capacitor insulating film is formed is narrower than the area of the region where the first capacitor insulating film is formed, and the capacitance of the second capacitor is You may make it become smaller than the capacity | capacitance of a 1st capacitor.

  Thereby, a desired write voltage can be applied to the tunnel film of the second capacitor.

  In the present invention, the first selection transistor provided between the control node voltage supply node and the other end of the first capacitor, the control drain voltage supply node, and the second capacitor A second selection transistor provided between the other end of the first selection transistor and a second selection transistor, and a selection voltage is supplied to the gate electrodes of the first and second selection transistors during the write operation. A selection transistor is set in an on state, and the other end of the first capacitor is supplied with the control gate voltage via the first selection transistor set in an on state, in addition to the second capacitor. The control drain voltage may be supplied to the end via the second selection transistor set to the on state.

  Thus, the control gate voltage can be supplied to the other end of the first capacitor, and the control drain voltage can be supplied to the other end of the second capacitor.

  The present invention further includes an auxiliary capacitor having one end connected to the floating node, and at least during a write operation, a control gate voltage is supplied to the other end of the first capacitor, A control drain voltage may be supplied to the other end, and a capacitance ratio correction voltage higher than the voltage of the floating node may be supplied to the other end of the auxiliary capacitor.

  As a result, the change in the capacitance ratio between the first capacitor and the second capacitor due to the parasitic capacitance of the floating node can be corrected. That is, a stable write operation can be performed, and deterioration of the oxide film and reliability of the second capacitor can be prevented.

  In the present invention, at least during the write operation, the capacitance ratio correction voltage is any one of a voltage supplied to one end of the first capacitor and a voltage supplied to the other end of the second capacitor. It may be set to the same voltage as the higher voltage or a higher voltage.

  Thus, when the voltage supplied to one end of the first capacitor is higher than the voltage supplied to the other end of the second capacitor, the potential of the floating node is equal to the capacitance of the auxiliary capacitor and the first capacitor. This is based on a capacitance ratio constituted by a combined capacitance of the capacitance of the capacitor and a combined capacitance of the gate capacitance of the detection transistor and the capacitance of the second capacitor. Similarly, when the voltage supplied to the other end of the second capacitor is higher than the voltage supplied to one end of the first capacitor, the potential of the floating node is equal to the capacitance of the auxiliary capacitor and the second capacitance. This is based on a capacitance ratio composed of a combined capacitance of the capacitor of the first capacitor and a combined capacitance of the gate capacitance of the detection transistor and the capacitance of the first capacitor. That is, the change in the capacitance ratio between the write operation for writing logic “1” and the write operation for writing logic “0” can be reduced.

  In the present invention, the capacitance value of the auxiliary capacitor may be set to the same value as the gate capacitance value of the detection transistor.

  As a result, the change in the capacitance ratio between the write operation for writing logic “1” and the write operation for writing logic “0” can be reduced. That is, the offset between the voltage applied to the second capacitor during the write operation for writing logic “1” and the voltage applied to the second capacitor during the write operation for writing logic “0” can be reduced. it can.

  In the present invention, the auxiliary capacitor may be formed in a region above a first capacitor formation region where the first capacitor is formed.

  Thus, the auxiliary capacitor can be formed without unnecessarily increasing the layout area of the nonvolatile semiconductor memory device.

  In the present invention, the second capacitor formation region in which the second capacitor is formed is formed on the first direction side of the first capacitor formation region, and the second capacitor formation region is The area may be narrower than the first capacitor formation region.

  Thereby, since the area of the formation region of the first capacitor is formed to be larger than that of the second capacitor, the capacity of the auxiliary capacitor can be increased.

  Further, in the present invention, when the direction orthogonal to the first direction is the second direction, the detection transistor gate electrode formation region in which the gate electrode of the detection transistor is formed is the first capacitor formation. It may be formed on the first direction side of the region and on the second direction side of the second capacitor formation region.

  Thereby, the layout area of the nonvolatile semiconductor memory device can be reduced.

  The present invention also includes a first capacitor having one end connected to the floating node and a detection transistor having a gate electrode connected to the floating node, and forms a gate electrode of the detection transistor. The first interlayer insulating film above the polysilicon layer relates to a nonvolatile semiconductor memory device formed by HDPCVD (High-Density-Plasma-Chemical-Vapor-Deposition) method.

  The present invention is also a method for manufacturing a nonvolatile semiconductor memory device including a first capacitor having one end connected to a floating node and a detection transistor having a gate electrode connected to the floating node. Forming a polysilicon layer for forming the gate electrode of the detection transistor, forming a second interlayer insulating film above the polysilicon layer, and forming a second interlayer insulating film above the second interlayer insulating film. Forming a first interlayer insulating film, wherein the first interlayer insulating film is formed by HDPCVD (High-Density-Plasma-Chemical-Vapor-Deposition) method About.

  The present invention also provides a first capacitor having one end connected to the floating node, a detection transistor having a gate electrode connected to the floating node, one end connected to the floating node, and the other end. And a second capacitor connected to the drain of the detection transistor, and a method of manufacturing a nonvolatile semiconductor memory device, the step of forming a polysilicon layer that forms the upper electrode of the second capacitor; A step of forming a second interlayer insulating film above the polysilicon layer, and a step of forming a first interlayer insulating film above the second interlayer insulating film, The insulating film relates to a method for manufacturing a nonvolatile semiconductor memory device formed by HDPCVD (High-Density-Plasma-Chemical-Vapor-Deposition).

  In addition, the method for manufacturing a nonvolatile semiconductor memory device according to the present invention may include a step of forming a metal wiring layer above the first interlayer insulating film.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention. In the following drawings, the same reference numerals have the same meaning.

1. Nonvolatile Semiconductor Memory Device A configuration example of an EEPROM (Electrically-Erasable-Programmable-Read-Only-Memory) 100 is shown below as an example of a nonvolatile semiconductor memory device.

  FIG. 1 is a circuit diagram showing a part of an EEPROM (nonvolatile semiconductor memory device in a broad sense) 100 according to this embodiment. The EEPROM 100 includes a selection transistor 21 (first selection transistor in a broad sense), a selection transistor 22 (second selection transistor in a broad sense), a cell 10, and a reading transistor 23. The cell 10 includes first and second capacitors 31 and 32, a floating node 30, and a detection transistor 41. The EEPROM 100 may include a plurality of cells 10, for example. The cell 10 can store 1-bit data, for example. The node CGN is a supply node to which the control gate voltage CG is supplied, and the node CDN is a supply node to which the control drain voltage CD is supplied.

  In the present embodiment and its modifications, an operation for injecting or discharging charges to the floating node 30 is defined as a write operation. For example, in the write operation, an operation of injecting charges into the floating node 30 is a logic “1” write operation, and an operation of discharging the charge of the floating node 30 is a logic “0” write operation.

  The selection transistors 21 and 22 are composed of N-type transistors, for example, and their gates are connected to the word line WL. One end of the selection transistor 21 is connected to the first capacitor 31 of the cell 10. A control gate voltage CG is supplied to the other end of the selection transistor 21. One end of the selection transistor 22 is connected to the second capacitor 32 of the cell 10 and the drain of the detection transistor 41. A control drain voltage CD is supplied to the other end of the selection transistor 22.

  For example, when a selection voltage for selecting the cell 10 is supplied to the word line WL, the selection transistors 21 and 22 are turned on. As a result, the control gate voltage CG and the control drain voltage CD are supplied to the cell 10. In this configuration example, writing from one bit unit is possible.

  One end of the first capacitor 31 of the cell 10 is connected to one end of the selection transistor 21, and the other end of the first capacitor 31 is connected to the floating node 30. One end of the second capacitor 32 is connected to the floating node 30, and the other end of the second capacitor 32 is connected to one end of the selection transistor 22.

  The gate electrode of the detection transistor 41 is connected to the floating node 30, and the drain of the detection transistor 41 is connected to one end of the selection transistor 22. The source of the detection transistor 41 is connected to the drain of the read transistor 23, and the ground level voltage VSS is supplied to the source of the read transistor 23, for example.

  In the EEPROM 100, the capacitance ratio is configured by the capacitance values of the first and second capacitors 31 and 32. The potential of the floating node 30 at the time of the write operation is set to a potential based on the capacitance ratio, the control gate voltage CG, and the control drain voltage CD. Then, by controlling the control gate voltage CG and the control drain voltage CD, for example, logic “1” or logic “0” can be written in the cell 10.

  For example, the capacitance value of the second capacitor 32 is set smaller than the capacitance value of the first capacitor 31, for example. The oxide film constituting the second capacitor 32 is formed of a thin oxide film (tunnel film) in order to inject and discharge charges.

  The above capacitance ratio is designed so that the electric field applied to the tunnel film is, for example, 10 MV / cm or more, but this is not the case when there is a margin in the writing time. A thin tunnel film has a low withstand voltage, and if the electric field applied to the tunnel film is too high, the tunnel film is easily broken. Moreover, even if it does not lead to destruction, damage due to a high electric field is accumulated, and the number of rewrites rapidly decreases. For this reason, the capacity ratio has an upper limit, and the capacity ratio may be set so as not to exceed the upper limit.

  The read transistor 23 is set to an on state, for example, during a data read operation. The read transistor 23 may be included in the cell 10 or may be laid out outside the cell 10 and shared by the plurality of cells 10.

  In addition, since the gate electrode of the detection transistor 41 is connected to the floating node 30, the data stored in the cell 10 can be read by detecting the on / off state of the detection transistor 41 with a sense amplifier or the like. it can.

  In the present embodiment, the operation of injecting or discharging charges to the floating node 30 is defined as a write operation. However, the present embodiment and its modifications are not limited to this. For example, the operation of injecting charges into the floating node 30 may be defined as a write operation, and the operation of discharging the charges of the floating node 30 may be defined as an erase operation. Further, in the present embodiment, writing of logic “1” or logic “0” is shown as a writing operation for convenience, but the present embodiment and its modification are not limited to this. For example, writing of logic “1” may be defined as a writing operation, and writing of logic “0” may be defined as an erasing operation, and vice versa.

  Next, the writing operation of the EEPROM 100 will be described. In the operation of writing logic “1” (hereinafter also referred to as high writing), the control gate voltage CG is set to a high voltage (for example, 10 V), and the control drain CD voltage is set to a low voltage (for example, 0 V). Further, since the selection voltage is supplied to the word line WL, for example, a voltage of 10 V is supplied to one end of the first capacitor 31, and a voltage of 0 V is supplied to the other end of the second capacitor 32, for example. .

  At this time, since it is a write operation, a signal set to non-active is supplied to the read signal line RD, and the read transistor 23 is set to an off state.

  At this time, the potential of the floating node 30 is set to a potential based on the capacitance ratio, the control gate voltage CG, and the control drain voltage CD. The capacitance value of the first capacitor 31 is C1, and the capacitance value of the second capacitor 32 is C2. For example, the ratio of capacitance values is C1: C2 = 8: 2. In this case, for example, a voltage of 7.5 V is applied to the tunnel film of the capacitor 32 as a voltage obtained by capacitively dividing the voltage of 10 V into 2: 8.

  On the other hand, when a voltage is applied to the thin oxide film (tunnel film), a tunnel current proportional to the applied voltage flows at a certain predetermined voltage. This predetermined voltage depends on, for example, the thickness of the oxide film. Here, a case where the thickness of the tunnel film of the capacitor 32 is formed so that a sufficient tunnel current flows when 7.5 V is applied will be described. In this case, for example, a voltage of 7.5V should be applied to the tunnel film of the capacitor 32. However, since a tunnel current flows, a voltage of about 6V is applied to the capacitor 32 as a result after a short time. It will only appear.

  That is, negative charges are injected into the floating node 30.

  In this way, high writing is performed. The upper limit of the capacitance ratio between the capacitors C1 and C2 is based on the thickness of the tunnel film of the capacitor 32. The film thickness of the tunnel film of the capacitor 32 and the capacitance ratio of the capacitors C1 and C2 can be set based on the use of the EEPROM 100. For example, in order to give the highest priority to the writing operation speed, the thickness of the capacitor 32 may be reduced, or the capacitance ratio between the capacitors C1 and C2 may be set high. As the capacitance ratio increases, the voltage applied to the tunnel film of the capacitor 32 increases, and the write speed increases accordingly.

  On the other hand, in the operation of writing logic “0” (hereinafter also referred to as “low write”), the control gate voltage CG is set to a low voltage (eg, 0 V), and the control drain CD voltage is set to a high voltage (eg, 10 V). Since the selection voltage is supplied to the word line WL, for example, a voltage of 0 V is supplied to one end of the first capacitor 31, and a voltage of 10 V is supplied to the other end of the second capacitor 32, for example. .

  At this time, since it is a write operation, a signal set to non-active is supplied to the read signal line RD, and the read transistor 23 is set to an off state. At this time, the potential of the floating node 30 is set to a potential based on the capacitance ratio, the control gate voltage CG, and the control drain voltage CD, as in the case of high writing.

  In this case, for example, a voltage of 7.5 V should be applied to the tunnel film of the capacitor 32 as a voltage obtained by capacitively dividing the voltage of 10 V into 2: 8. However, in the low write operation as in the high write operation, a tunnel current flows through the tunnel film of the capacitor 32, so that the potential difference is reduced to about 6 V after a short time.

  That is, negative charges are released from the floating node 30.

  In this way, row writing is performed. During the write operation, the control gate voltage CG is supplied to one end of the capacitor 31 and the control drain voltage CD is supplied to the other end of the capacitor 32. The time of charge injection into the floating node 30 during the write operation or the time of charge release from the floating node 30 is higher than that of an interlayer insulating film ILD1 described later than HDPCVD (High-Density-Plasma-Chemical-Vapor-Deposition) method. Compared to the case of forming by this process, the time is set shorter.

  FIG. 2 is a diagram showing a layout of the EEPROM 100. Regions 71 and 72 indicate diffusion regions 71 and 72 separated by the element isolation region 81. Reference signs DR1 and DR2 indicate directions, and the direction DR2 is a direction orthogonal to the direction DR1. The element isolation region 81 is formed by, for example, LOCOS (LoCal-Oxidation-of-Silicon) or STI (Shallow-Trench-Isolation). A region 31-2 represents a high concentration impurity implantation region, and represents a region where the lower electrode of the first capacitor 31 is formed (first capacitor forming region in a broad sense). A region 32-2 represents a high-concentration impurity implantation region, and represents a region where a lower electrode (second capacitor forming region in a broad sense) of the second capacitor 32 is formed.

  The region 31-1 indicates a region where the upper electrode of the first capacitor 31 formed in the first polysilicon layer, for example (first capacitor forming region in a broad sense) is formed. A region 32-1 indicates a region (second capacitor forming region in a broad sense) in which the upper electrode of the second capacitor 32 formed in the first polysilicon layer is formed.

  As shown in FIG. 2, the regions 32-1 and 32-2 (second capacitor forming region in a broad sense) where the second capacitor 32 is formed are regions 31-1 where the first capacitor 31 is formed. And 31-2 in the first direction DR1 side. The areas 32-1 and 32-2 where the second capacitor 32 is formed are narrower than the areas 31-1 and 31-2 where the first capacitor 31 is formed.

  The gate electrodes 21-G and 22-G of the selection transistors 21 and 22 are formed, for example, in the second polysilicon layer above the first polysilicon layer. In addition, the region where the gate electrode 21-G of the selection transistor 21 is formed (first selection transistor gate electrode formation region in a broad sense) is a region 31-1 and 31-2 where the first capacitor 31 is formed. Is formed on the opposite side of the second direction DR2. The region where the gate electrode 22-G of the selection transistor 22 is formed (second selection transistor gate electrode formation region in a broad sense) is the second of the regions 32-1 and 32-2 where the second capacitor 32 is formed. 2 is formed on the opposite side of the direction 2 and on the first direction DR1 side of the region where the gate electrode 22-G of the selection transistor 22 is formed.

  The gate electrode 41-G of the detection transistor 41 is formed, for example, in the first polysilicon layer and is connected to the upper electrode of the capacitor 31 in the region 31-1. In addition, the detection transistor gate electrode formation region 41-1 in which the gate electrode 41-G of the detection transistor 41 is formed is the first direction DR1 of the regions 31-1 and 31-2 in which the first capacitor 31 is formed. And on the second direction side of the regions 32-1 and 32-2 where the second capacitor 32 is formed.

  Note that the upper electrodes of the capacitors 31 and 32 and the gate electrode 41 -G formed in the first polysilicon layer are also the floating nodes 30.

  In order to apply an electric field of 10 MV / cm or more to the tunnel film of the capacitor 32, for example, the capacitance value C1 of the capacitor 31 needs to be sufficiently larger than the capacitance value C2 of the capacitor 32. However, since the oxide film of the capacitor 32 is a thin tunnel film, it is necessary to increase the area of the electrode of the capacitor 31 in order to make the capacitance value C1 of the capacitor 31 larger than the capacitance value C2 of the capacitor 32. The reason why the area of the upper electrode of the capacitor 31 indicated by the region 31-1 is larger than the area of the upper electrode of the capacitor 32 indicated by the region 32-1 is to increase the capacitance ratio.

  FIG. 3 is a cross-sectional view showing the AA cross section of FIG. Reference numeral PL1 denotes a first polysilicon layer, for example, a wiring including the upper electrodes of the capacitors 31 and 32. As shown in FIG. 3, the film thickness 32-3 of the oxide film 82 of the capacitor 32 is processed to be thinner than the film thickness 31-3 of the oxide film 82 of the capacitor 31, and a tunnel current flows. The film thickness 31-3 is set to, for example, 100 to 200 mm, and the film thickness 32-3 is set to, for example, 70 to 80 mm. However, since the upper electrode formation region 31-1 of the capacitor 31 is sufficiently larger in area than the upper electrode formation region 32-1 of the capacitor 32, the capacitance ratio can be configured. . Symbol PL2 indicates a second polysilicon layer, and symbol ILD1 indicates an interlayer insulating film (first interlayer insulating film in a broad sense). Reference numeral ILD2 denotes an interlayer insulating film (second interlayer insulating film in a broad sense).

2. Manufacturing Process Next, a manufacturing process of the EEPROM 100 according to the present embodiment will be described with reference to FIGS. 4 to 10 show a portion of the capacitor 32 in the cross-sectional view of FIG.

  First, as shown in FIG. 4, an impurity (for example, n +) is implanted into a substrate (for example, a P-type substrate) to form an element isolation region 81. The diffusion region 72 is formed as a high concentration impurity diffusion region, for example.

  Next, an oxide film 82 is formed as shown in FIG. Next, etching is performed as indicated by A1 in FIG. 6, and an oxide film is formed as indicated by A2 in FIG. Next, as shown in FIG. 8, a first polysilicon layer (polysilicon layer in a broad sense) PL1 is formed. As a forming method, it can be formed by a normal CVD method or the like. The region 32-1 of the first polysilicon layer PL1 is the upper electrode of the second capacitor 32, and the region 32-1 of the diffusion region 72 is the lower electrode of the second capacitor 32. .

  Next, as shown in FIG. 9, the polysilicon layer PL1 is etched, and an interlayer insulating film ILD2 is formed on the oxide film 82 so as to cover the first polysilicon layer PL1. As a forming method, it can be formed by a normal CVD method or the like.

  Next, as shown in FIG. 10, interlayer insulating film ILD2 is etched to form second polysilicon layer PL2. The second polysilicon layer PL2 is etched as shown in FIG. 10, and an interlayer insulating film ILD1 is formed on the interlayer insulating film ILD2 so as to cover the second polysilicon layer PL2.

  In the present embodiment, the interlayer insulating film ILD2 is formed by the HDPCVD method. Since the second polysilicon layer PL2 has very good workability, when etched, for example, a step between the interlayer insulating film ILD2 and the second polysilicon layer is sharply formed as indicated by A3 in FIG. However, since the HDPCVD method is excellent in step coatability, it is not necessary to improve the step coatability by fluid CVD or the like before using the HDPCVD method.

  When the interlayer insulating film IDL1 is formed using the HDPCVD method, charge up occurs in each layer. Since the substrate is bound to a predetermined potential, the charged-up charge flows in various directions along the predetermined potential of the substrate. At this time, the capacitors 31 and 32 in FIG. 3 collect more charges than the other gate electrodes. However, since the potential generated by the HDPCVD method is very high, for example, several KV, and the temperature during film formation is also high, the charge-up generated in the capacitors 31 and 32 becomes very severe. At this time, as shown in FIG. 3, the film thickness of the capacitor 32 is very thin compared to the film thickness of the capacitor 31. That is, the electric charge accumulated in the capacitors 31 and 32 flows in the direction of the potential of the substrate through the tunnel film of the capacitor 32. At this time, the tunnel film of the capacitor 32 is damaged by the flowing electric charge, and a trap region is formed, for example, in a portion indicated by A4 in FIG.

  By using this trap area, the writing speed of the EEPROM 100 of this embodiment can be improved. When the trap region is formed in the tunnel film as described above, when the charge is injected / released, the charge only needs to pass through an insulating layer thinner than the tunnel film. For example, the charge is injected into the floating node 30 in a short period. It becomes possible. Similarly, the charge of the floating node 30 can be released in a short period.

  In this embodiment, for example, silicide is formed on the second polysilicon layer PL2 and the upper portion of the impurity diffusion region, but is omitted in FIGS. Further, a metal wiring layer made of aluminum or the like may be formed on the interlayer insulating film ILD1. For the formation of the metal wiring layer, plasma CVD or HDPCVD can be used.

3. Effect Next, in order to show the improvement of the writing speed of the present embodiment, the writing time of the EEPROM 100 will be described with reference to FIGS. A case where the interlayer insulating film ILD1 of the EEPROM 100 of the present embodiment is formed of a BPSG film is used as a comparative example. In both the present embodiment and the comparative example, the voltage applied to the tunnel film of the capacitor 32 is set to the same voltage.

  FIG. 11 is a diagram showing the relationship between the write time of the EEPROM 100 and the threshold value Vt of the detection transistor 41, and FIG. 12 is a diagram showing the relationship between the write time of the comparative example and the threshold value Vt of the detection transistor 41.

  In the present embodiment, according to FIG. 11, when the write time is, for example, 0.001 sec as shown by A4, the threshold value Vt of the detection transistor 41 at that time is 1.0V. On the other hand, in the comparative example, according to FIG. 12, when the write time is 0.001 sec, Vt of the detection transistor 41 is 0.8 V as indicated by A5. That is, in order to set the threshold value Vt of the detection transistor 41 to 1.0 V, it is necessary to set the writing time to 0.002 sec, for example, as indicated by A6.

  In other words, in the write operation, when the threshold value Vt of the detection transistor 41 is set to 1.0 V, for example, the write time of 0.002 sec is required in the comparative example, but in this embodiment, the write time of 0.001 sec. Just do it. That is, in this embodiment, the writing speed can be improved by about 50%.

  This improvement in the writing speed is attributed to the trap region formed in the tunnel film of the capacitor 32 indicated by A8 in FIG. It can be considered that the insulating layer between the upper electrode and the lower electrode of the capacitor 32 is thinned by forming the trap region indicated by A4 in FIG. 10 in the tunnel film of the capacitor 32. In general, as the tunnel film becomes thinner, the amount of charge flowing per unit time increases. That is, also in this embodiment, the amount of charge flowing per unit time is increased compared to the comparative example. Thereby, in this embodiment, the writing speed can be improved as compared with the comparative example without raising the voltage applied to the tunnel film of the capacitor 32. In addition, since the writing time can be shortened, the power consumption of the nonvolatile semiconductor memory device can be reduced. In addition, the improvement in the writing speed shortens the application time of the writing voltage as compared with the comparative example, so that the number of rewritable times can be almost eliminated.

  Further, due to the improvement of the writing speed, in this embodiment, when the same writing time as that required in the comparative example is set, the writing voltage can be set to a voltage lower than that in the comparative example. In this case, since the voltage applied to the tunnel film of the capacitor 32 becomes low, deterioration of the tunnel film can be alleviated. That is, the present embodiment can improve the reliability more than the comparative example, and the nonvolatile semiconductor memory device of the present embodiment can be used when higher reliability is required. In addition, since the writing voltage can be reduced, the power consumption of the nonvolatile semiconductor memory device can be reduced.

Further, in the comparative example, when the interlayer insulating film ILD1 is formed, an oxide film (for example, a TEOS film) having excellent step film property is formed by using, for example, fluid CVD in order to absorb the step indicated by A7 in FIG. Then, a BPSG film is formed. For example, TEOS (TetraEthylOrthoSilisate) -O ₃ CVD can be used as the flowable CVD. When the interlayer insulating film ILD1 is formed, for example, if a BPSG film is formed without forming a TEOS film, a VOID may occur in the portion A7. VOID may cause rupture or the like in a later manufacturing process, which deteriorates the yield. For this reason, in the comparative example, in order to suppress the generation of VOID, it is necessary to form an oxide film having excellent step film properties such as a TEOS film. Further, in the TEOS film formation process, hydrogen atoms are easily taken into the oxide film or the like. Therefore, when the TEOS film is formed in the vicinity of the floating node 30, the hydrogen atoms adversely affect the charge injected into the floating node 30 by the write operation.

  On the other hand, in the present embodiment, the interlayer insulating film ILD1 is formed using the HDPCVD method. The HDPCVD method is excellent in step coatability and does not require the formation of a TEOS film or the like. For this reason, the number of processes can be reduced, and the manufacturing cost can be reduced. In addition, since the TEOS film is not formed, adverse effects on the floating node 30 in the comparative example can be prevented.

  In the comparative example, when the TEOS film is formed thin, relatively high temperature annealing is required in the process of forming the BPSG film in order to suppress the generation of VOID. This high temperature annealing may adversely affect the silicide SL1 formed in the second polysilicon layer PL2 and the silicide SL2 formed in the diffusion region.

  Although depending on the material, the silicides SL1 and SL2 undergo a re-reaction by the annealing exceeding about 700 ° C. to cause aggregation or the like. When aggregation occurs in the silicides SL1 and SL2, the resistances of the silicides SL1 and SL2 are increased due to the fine line effect or the like. On the other hand, for example, the melting point of the BPSG film is 800 ° C., and it is necessary to perform annealing at a high temperature of 800 ° C. or higher in order to suppress the generation of VOID. In other words, in the comparative example, the re-reaction of the silicides SL1 and SL2 is promoted, causing aggregation of the silicides SL1 and SL2. As a result, the silicides SL1 and SL2 optimized in the previous process are increased in resistance due to the fine line effect or the like, which deteriorates the yield of the nonvolatile semiconductor memory device.

  In contrast, in the present embodiment, the interlayer insulating film ILD1 is formed by the HDPCVD method. In the HDPCVD method, film formation is performed at a low temperature (for example, 350 ° C. to 400 ° C.) that is sufficiently lower than CVD when forming a BPSG film or the like. In this low temperature treatment, the silicides SL1, SL2 and the like hardly aggregate, so that the silicides SL1, SL2, etc. are not adversely affected when the interlayer insulating film ILD1 is formed. That is, compared to the comparative example, it is possible to suppress a decrease in yield due to the high resistance of the silicides SL1 and SL2.

  Further, in the HDPCVD method, the processing time is, for example, about 100 seconds, which is a short time. For this reason, the manufacturing cost can be reduced as compared with the comparative example.

  Further, the high temperature annealing required for the BPSG film of the comparative example also affects the diffusion regions 71 and 72. The diffusion regions 71 and 72 are, for example, high-concentration impurity diffusion regions, but impurities are diffused by this high-temperature annealing. Impurities are diffused, the impurity concentration of the diffusion regions 71 and 72 is reduced, a depletion layer is formed in the diffusion regions 71 and 72, and the capacitance values of the capacitors 31 and 32 are changed. Further, since the impurity concentration is reduced, the resistance of the diffusion regions 71 and 72 and other high concentration impurity diffusion regions is increased. These may cause the writing operation to become unstable and cause a reduction in product quality. In addition, the yield is deteriorated and the reduction of the manufacturing cost is hindered.

  On the other hand, in the present embodiment, the interlayer insulating film ILD1 is formed by the HDPCVD method and does not require high-temperature annealing. Therefore, unlike the comparative example, thermal history due to high-temperature annealing is not left in each layer. For example, the impurity concentrations of the diffusion regions 71 and 72 and other impurity diffusion regions are not affected. In other words, the present embodiment can prevent the diffusion regions 71 and 72 from becoming depleted and the capacitance values of the capacitors 31 and 32 from changing in the present embodiment. As a result, product quality can be ensured. In addition, a decrease in yield can be suppressed and manufacturing costs can be reduced.

  As described above, in this embodiment, since the interlayer insulating film ILD1 can be formed by low-temperature processing, no thermal history is left in each layer formed in the previous process, as compared with the comparative example. Therefore, it is possible to eliminate the influence of the high temperature treatment, and it is possible to improve the product yield and ensure the product quality. Further, the trap region can be formed in the tunnel film of the capacitor 32 without giving a thermal history. In addition, when the film formation or the like is performed by the low-temperature processing in all the previous steps, all the steps for manufacturing the nonvolatile semiconductor memory device of this embodiment can be performed by the low-temperature processing.

  In the comparative example, since the VOID can be prevented from being formed by forming the TEOS film thick, the BPSG film can be annealed at a relatively low temperature (for example, 650 ° C.). However, the method of forming a thick TEOS film cannot be used for a process of 0.25 μm or less. Even if annealing of the BPSG film is performed at a relatively low temperature, the temperature is higher than that of plasma CVD or the like, and accordingly, the diffusion regions 71 and 72 are damaged accordingly. Therefore, the diffusion regions 71 and 72 as described above are likely to be depleted, and as a result, the capacitance values of the capacitors 31 and 32 are decreased, and the writing operation is made unstable.

  On the other hand, in the present embodiment, the interlayer insulating film ILD1 is formed by HDPCVD without forming a TEOS film or a BPSG film. For this reason, it can utilize also for a process of 0.25 micrometer or less, suppressing generation | occurrence | production of VOID. Further, as described above, in the HDPCVD method, since the processing is performed at a low temperature that is sufficiently lower than the CVD for forming the BPSG film or the like, the diffusion regions 71 and 72 or the like are formed when the interlayer insulating film ILD1 is formed. The adverse effects due to the heat treatment applied to the silicides SL1, SL2, etc. can be alleviated.

  Further, in the present embodiment, since the trap region can be formed in the tunnel film of the capacitor 32 in the film formation process of the interlayer insulating film IDL1, it is not necessary to prepare a separate process for forming the trap region in the tunnel film. Excellent performance.

  FIG. 14 is a diagram showing retention (holding) characteristics of the EEPROM 100 of this embodiment and the nonvolatile semiconductor memory device of the comparative example. The horizontal axis represents time (h), and the vertical axis represents the threshold value Vt of the detection transistor 41. FIG. 14 shows retention characteristics in an environment of 300 ° C., for example. A curve B1 shows the retention characteristic of the comparative example, and a curve B2 shows the retention characteristic according to this embodiment. As can be seen from the curve B1, in the comparative example, the threshold value Vt does not decrease so much even after 10 hours from the start of measurement even in an environment of 300 ° C. In other words, the charge injected by writing can be held for a long time.

  On the other hand, in the present embodiment, as shown in A9, the threshold value Vt is significantly reduced approximately 1 hour after the start of measurement. That is, in an environment of 300 ° C., in this embodiment, the charge injected by writing disappears in a short time. However, from this result and various experiments, it was found that a trap region was formed at a shallow position of the tunnel film of the capacitor 32 by HDPCVD in this embodiment. As described above, it has been found that the trapping region is formed at a shallow position of the tunnel film, so that the writing speed is dramatically improved.

  In contrast, the present embodiment applies this characteristic to a nonvolatile semiconductor memory device. As a result of further experiments, it was found that the retention characteristics shown in FIG. 14 appear in an environment of about 250 ° C. or higher. That is, in an environment of 250 ° C. or lower, charge can be held for a long time as long as the comparative example.

  In addition, considering the normal use environment, it is not necessary to consider operation guarantee at an actual use of 200 ° C. or higher, so this embodiment can be applied to various electronic devices. Further, when the specification is such that data is written before being mounted on a product and the written data is retained for a long period of time, there is no problem as in the comparative example.

  The present embodiment is also suitable for a memory indicating the remaining amount of the ink tank of the printer, a cryptographic memory stored in a key of a car or the like, for example. The memory for indicating the remaining amount of the ink tank and the memory for key encryption need to be frequently rewritten due to the nature of the usage environment. Furthermore, the reliability of holding the data is also required. In other words, in order to apply the comparative example to these memories, it is necessary to devise a technique that can solve the problem of the comparative example, and it is difficult to apply the memory as it is.

  On the other hand, in this embodiment, the write voltage can be lowered, and the deterioration of the tunnel film of the capacitor 32 can be significantly reduced as compared with the comparative example. For example, it can sufficiently withstand the usage situation where the number of rewrites is relatively large. In this embodiment, the writing speed can be improved without increasing the writing voltage. Further, as described above, in the present embodiment, the reliability can be improved as compared with the comparative example. That is, the present embodiment is suitable for the ink tank memory and the key encryption memory.

4). Modification This embodiment is not limited to the circuit of FIG. 1, and can be applied to each of the nonvolatile semiconductor memory devices 110 to 130 shown in FIGS. In each of the nonvolatile semiconductor memory devices 110 to 130, the same effect as that of the EEPROM 100 of the present embodiment can be achieved.

  FIG. 15 is a diagram illustrating a configuration example of a nonvolatile semiconductor memory device 110 which is a modification of the present embodiment. The nonvolatile semiconductor memory device 110 includes a selection transistor 122 (second selection transistor in a broad sense), first capacitors 131-1 and 131-2, a second capacitor 132, a floating node 130, and a detection transistor. 141 is included. The capacitor 132 is a capacitor provided at the gate of the detection transistor 141.

  In the nonvolatile semiconductor memory device 110, at the time of writing, a selection voltage is supplied to the word line WL, a voltage of, for example, 8V is supplied to the supply nodes CDN and CGN, and the supply node ER is set to a floating state, for example. At the time of erasing, a non-selection voltage is supplied to the word line WL, the supply node CGN is set in a floating state, for example, and a voltage of 20 V, for example, is supplied to the supply node ER.

  Also in the modified example of FIG. 15, the interlayer insulating film formed above the second capacitor 132 and below the metal wiring layer can be formed by HDPCVD. As a result, a trap region is formed in the tunnel film of the capacitor 132, and the writing speed can be improved.

  FIG. 16 is a diagram illustrating a configuration example of a nonvolatile semiconductor memory device 120 which is a modification of the present embodiment. The nonvolatile semiconductor memory device 120 includes a first capacitor 231, a second capacitor 232, a floating node 230, and a detection transistor 241. The capacitor 232 is a capacitor provided at the gate of the detection transistor 241.

  In the nonvolatile semiconductor memory device 120, at the time of writing, for example, a voltage of 5V is supplied to the supply nodes CDN and CGN, and a voltage of 0V, for example, is supplied to the supply node CS. At the time of erasing, for example, a voltage of 0 V is supplied to the supply node CGN, and a voltage of 9 V, for example, is supplied to the supply node CS and the supply node CDN.

  Also in the modification of FIG. 16, the interlayer insulating film formed above the second capacitor 232 and below the metal wiring layer can be formed by the HDPCVD method. Thereby, a trap region is formed in the tunnel film of the capacitor 232, and the writing speed can be improved.

  FIG. 17 is a diagram illustrating a configuration example of a nonvolatile semiconductor memory device 130 which is a modification of the present embodiment. The nonvolatile semiconductor memory device 130 is an EEPROM 130 in which an auxiliary capacitor 33 is provided on the floating node 30 of the EEPROM 100 of the present embodiment. That is, the cell 11 included in the EEPROM 130 includes first and second capacitors 31 and 32, a floating node 30, an auxiliary capacitor 33, and a detection transistor 41. Other configurations of the EEPROM 130 are the same as those of the EEPROM 100. The voltage supplied to the supply nodes CGN and CDN in the write operation may be the same as that of the EEPROM 100. However, since the EEPROM 130 includes the auxiliary capacitor 33, unlike the EEPROM 100, the capacitance ratio correction voltage VPP is supplied to the auxiliary capacitor 33.

  One end of the auxiliary capacitor 33 of the cell 11 is connected to the floating node 30, and the other end of the auxiliary capacitor 33 is supplied with the capacitance ratio correction voltage VPP at least during the write operation. For example, the capacitance ratio correction voltage VPP is set to a higher one of the control gate voltage CG and the control drain voltage CD. When the control gate voltage CG is set to 10V, for example, and the control drain voltage CD is set to 0V, for example, during the write operation, the capacitance ratio correction voltage VPP is set to 10V. Further, when the control gate voltage CG is set to, for example, 0V and the control drain voltage CD is set to, for example, 10V during the write operation, the capacitance ratio correction voltage VPP is set to 10V.

  Note that the capacitance ratio correction voltage VPP is not limited to the above voltage, and the capacitance ratio correction voltage VPP may be set to a voltage higher than the voltage of the floating node 30 during the write operation, for example. Further, the capacitance ratio correction voltage VPP may be set to a voltage equal to or higher than the voltage of the node ND1 or ND2 during the write operation.

  For example, in the high writing of the EEPROM 130, the control gate voltage CG is set to a high voltage (for example, 10V), and the control drain CD voltage is set to a low voltage (for example, 0V). Further, since the selection voltage is supplied to the word line WL, for example, a voltage of 10 V is supplied to one end of the first capacitor 31, and a voltage of 0 V is supplied to the other end of the second capacitor 32, for example. .

  Further, a capacitance ratio correction voltage VPP (for example, 10 V) is supplied to the other end of the auxiliary capacitor 33. At this time, since it is a write operation, a signal set to non-active is supplied to the read signal line RD, and the read transistor 23 is set to an off state.

  At this time, the potential of the floating node 30 is set to a potential based on the capacitance ratio, the control gate voltage CG, and the control drain voltage CD. Strictly speaking, the capacitance ratio here is constituted by the capacitance value of the first and second capacitors 31 and 32, the gate capacitance value with respect to the substrate potential of the detection transistor 41, and the capacitance value of the auxiliary capacitor 33.

  FIG. 18 is a diagram showing the capacity ratio of the cell 11 in the high writing of the EEPROM 130. The capacitance value of the first capacitor 31 is C1, the capacitance value of the second capacitor 32 is C2, the gate capacitance value with respect to the substrate potential of the detection transistor 41 is C3, and the capacitance value of the auxiliary capacitor 33 is C4. In the EEPROM 130 of the modified example, the capacitance value C4 of the auxiliary capacitor 33 is set to the same value as the gate capacitance value C3 of the detection transistor 41, for example, but is not limited thereto.

  As shown in FIG. 18, a voltage of 10V is supplied to one end of the capacitor 31, and 10V is supplied to the other end of the auxiliary capacitor 33 as a capacitance ratio correction voltage. That is, the capacitor 31 and the auxiliary capacitor 33 are connected in parallel.

  The other end of the capacitor 32 is set to 0V. The gate capacitance value C3 of the detection transistor 41 is a capacitance value with respect to the substrate potential. That is, it can be considered that the gate capacitances of the capacitor 32 and the detection transistor 41 are connected in parallel.

  From the above, it can be considered that the combined capacitor CC1 whose capacitance value is C1 + C4 and the combined capacitor CC2 whose capacitance value is C2 + C3 are connected in series at the floating node 30. A control gate voltage CG (for example, 10V) and a control drain voltage CD (for example, 0V) are respectively supplied to both ends of the combined capacitors CC1 and CC2 connected in series.

  For example, the ratio of the capacitance values is C1: C2: C3: C4 = 8: 2: 1: 1. Then, the capacity ratio between the composite capacitor CC1 and the composite capacitor CC2 is (8 + 1) :( 2 + 1) = 9: 3. In this case, for example, a voltage of 7.5 V is applied to the tunnel film of the capacitor 32 as a voltage obtained by capacitively dividing the voltage of 10 V into 3: 9.

  The thickness of the tunnel film of the capacitor 32 is formed so that a sufficient tunnel current flows, for example, when 7.5 V is applied, for example, as in the EEPROM 100 of the present embodiment. In this case, for example, a voltage of 7.5V should be applied to the tunnel film of the capacitor 32. However, since a tunnel current flows, a voltage of about 6V is applied to the capacitor 32 as a result after a short time. It will only appear.

  That is, negative charges are injected into the floating node 30.

  In this way, high writing is performed. Note that the capacitance ratio correction voltage VPP may be set to a potential higher than the potential of the floating node 30. As described above, the potential of the floating node 30 is determined by the capacitance ratio of the combined capacitors CC1 and CC2 obtained from the capacitance values C1 to C4, the control gate voltage CG, and the control drain voltage CD. Further, the upper limit of the capacitance ratio of the combined capacitors CC1 and CC2 is based on the film thickness of the tunnel film of the capacitor 32. The film thickness of the tunnel film of the capacitor 32 and the capacitance ratio of the combined capacitors CC1 and CC2 can be set based on the use of the EEPROM 100.

  For example, when the write operation speed is given the highest priority, the capacitor 32 may be thinned or the capacitance ratio of the combined capacitors CC1 and CC2 may be set high. As the capacitance ratio increases, the voltage applied to the tunnel film of the capacitor 32 increases, and the write speed increases accordingly.

  Further, the capacitance ratio correction voltage VPP may be set to a voltage equal to or higher than a high voltage (for example, 10 V) supplied to the control gate voltage CG, for example, at least during a high write operation.

  Next, row writing of the EEPROM 130 according to a modification will be described. In the low writing of the EEPROM 130, the control gate voltage CG is set to a low voltage (for example, 0V), and the control drain CD voltage is set to a high voltage (for example, 10V). Since the selection voltage is supplied to the word line WL, for example, a voltage of 0 V is supplied to one end of the first capacitor 31, and a voltage of 10 V is supplied to the other end of the second capacitor 32, for example. .

  Further, a capacitance ratio correction voltage VPP (for example, 10 V) is supplied to the other end of the auxiliary capacitor 33. At this time, since it is a write operation, a signal set to non-active is supplied to the read signal line RD, and the read transistor 23 is set to an off state.

  At this time, the potential of the floating node 30 is set to a potential based on the capacitance ratio, the control gate voltage CG, and the control drain voltage CD, as in the case of high writing.

  19A and 19B are diagrams showing the capacity ratio of the cell 11 in row writing. In FIG. 19, the case where the capacitance values C1 to C4 have the same capacitance ratio as in FIG. 18 will be described.

  According to FIG. 19A, a voltage of 0V is supplied to one end of the capacitor 31, and 10V is supplied to the other end of the auxiliary capacitor 33 as a capacitance ratio correction voltage. The other end of the capacitor 32 is supplied with a voltage of 10V. That is, as shown in FIG. 19B, it can be considered that the capacitor 32 and the auxiliary capacitor 33 are connected in parallel, and the capacitor of the capacitor 31 and the detection transistor 41 are connected in parallel.

  Therefore, it can be considered that the composite capacitor CC11 whose capacitance value is C1 + C3 and the composite capacitor CC12 whose capacitance value is C2 + C4 are connected in series at the floating node 30. A control gate voltage CG (for example, 0V) and a control drain voltage CD (for example, 10V) are respectively supplied to both ends of the combined capacitors CC11 and CC12 connected in series.

  As a result, the capacity ratio between the combined capacitor CC11 and the combined capacitor CC12 is (8 + 1) :( 2 + 1) = 9: 3. In this case, for example, a voltage of 7.5V should be applied to the tunnel film of the capacitor 32 as a voltage obtained by capacitively dividing the voltage of 10V into 3: 9. However, in the low write operation as in the high write operation, a tunnel current flows through the tunnel film of the capacitor 32, so that the potential difference is reduced to about 6 V after a short time.

  That is, negative charges are released from the floating node 30.

  In this way, row writing is performed. Note that the capacitance ratio correction voltage VPP may be set to a voltage equal to or higher than a high voltage (for example, 10 V) supplied to the control drain voltage CD, for example, at least during a low write operation.

  In the above configuration, the capacitance value C4 of the auxiliary capacitor 33 is set to the same value as the capacitance value C3 of the gate capacitance of the detection transistor 41 as an example, but is not limited thereto. For example, the capacitance value C4 of the auxiliary capacitor 33 may be set smaller than the capacitance value C3 of the gate capacitance of the detection transistor 41.

  In the EEPROM 130, the capacitance ratio correction voltage VPP can be supplied to the other end of the auxiliary capacitor 33 during the write operation, and the capacitance ratio correction voltage VPP can be prevented from being supplied during the read operation. In addition, during the read operation, the other end of the auxiliary capacitor 33 can be set to a ground level voltage or a floating state. Therefore, the auxiliary capacitor 33 has an obstructive capacitance when detecting the on / off state of the detection transistor 41. Must not.

  FIG. 20 is a diagram showing a layout of the EEPROM 130 according to a modification. The difference from the EEPROM 100 is that an auxiliary capacitor 33 is provided. That is, in FIG. 20, a region 33-1 where the auxiliary capacitor 33 is formed is added.

  A region 33-1 indicates a region where the upper electrode of the auxiliary capacitor 33 is formed, and the upper electrode of the auxiliary capacitor 33 is formed, for example, in the first aluminum wiring layer. The auxiliary capacitor 33 is formed in a pair with the upper electrode formed in the first aluminum wiring layer by using the upper electrode of the capacitor 31 indicated by the region 31-1 as the lower electrode of the auxiliary capacitor 33. The

  The auxiliary capacitor 33 is formed in a region above the regions 31-1 and 31-2 (first capacitor forming region in a broad sense) where the first capacitor 31 is formed.

  Further, as shown in FIG. 20, the regions 32-1 and 32-2 (second capacitor forming region in a broad sense) where the second capacitor 32 is formed are regions 31 where the first capacitor 31 is formed. -1 and 31-2 in the first direction DR1 side. The areas 32-1 and 32-2 where the second capacitor 32 is formed are narrower than the areas 31-1 and 31-2 where the first capacitor 31 is formed.

  21 is a cross-sectional view showing the AA cross section of FIG. Reference symbol AL1 indicates an upper electrode of the auxiliary capacitor 33, and is formed, for example, in the region 33-1 of the first aluminum wiring layer. Reference numeral PL1 denotes, for example, a wiring formed in the first polysilicon layer, and includes upper electrodes of capacitors 31 and 32 formed in the first polysilicon layer. As shown in FIG. 21, the film thickness 32-3 of the oxide film 82 of the capacitor 32 is processed thinner than the film thickness 31-3 of the oxide film 82 of the capacitor 31, and a tunnel current flows. The film thickness 31-3 is set to, for example, 100 to 200 mm, and the film thickness 32-3 is set to, for example, 70 to 80 mm. However, since the upper electrode formation region 31-1 of the capacitor 31 is sufficiently larger in area than the upper electrode formation region 32-1 of the capacitor 32, the capacitance ratio can be configured. .

  Further, the thickness 33-3 of the oxide film of the auxiliary capacitor 33 is thicker than the other thicknesses 31-3 and 32-3. However, in this embodiment, the formation region of the auxiliary capacitor 33 is secured by using the formation region of the upper electrode of the capacitor 31. As a result, the waste of circuit layout can be eliminated and the capacitance value C4 of the auxiliary capacitor 33 can be earned.

  Next, effects of the EEPROM 130 according to the modification will be described. For example, when the gate capacitance of the detection transistor 41 of the EEPROM 100 cannot be ignored, the gate capacitance value of the detection transistor 41 is set to C3. At this time, in the EEPROM 100, when the other end of the capacitor 32 is set to 0V, that is, when high writing is performed, it can be considered that the gate capacitance of the capacitor 32 and the detection transistor 41 is connected in parallel.

  That is, it can be considered that the capacitor CC21 having the capacitance value C1 and the combined capacitor CC22 having the capacitance value C2 + C3 are connected in series at the floating node 30. A control gate voltage CG (for example, 10V) and a control drain voltage CD (for example, 0V) are respectively supplied to both ends of the combined capacitors CC21 and CC22 connected in series.

  For example, the ratio of capacitance values is C1: C2: C3 = 8: 2: 1. Then, the capacity ratio between the capacitor CC1 and the combined capacitor CC2 is 8: (2 + 1) = 8: 3. In this case, for example, a voltage of about 7.3 V is applied to the tunnel film of the capacitor 32 as a voltage obtained by capacitively dividing the voltage of 10 V into 3: 8.

  At this time, a tunnel current flows through the tunnel film of the capacitor 32, and after a short time, the potential difference is reduced to about 6V.

  That is, negative charges are injected into the floating node 30. In this way, high writing is performed.

  On the other hand, in the low writing of the EEPROM 100, for example, a voltage of 0V is supplied to one end of the capacitor 31, and a voltage of 10V is supplied to the other end of the capacitor 32. That is, it can be considered that the capacitor of the capacitor 31 and the detection transistor 41 are connected in parallel.

  Therefore, it can be considered that the composite capacitor CC31 whose capacitance value is C1 + C3 and the capacitor CC32 whose capacitance value is C2 are connected in series at the floating node 30 of the EEPROM 100. A control gate voltage CG (for example, 0V) and a control drain voltage CD (for example, 10V) are respectively supplied to both ends of the combined capacitors CC11 and CC12 connected in series.

  As a result, the capacity ratio of the combined capacitor CC31 and the capacitor CC32 is (8 + 1): 2 = 9: 2. In this case, for example, a voltage of about 8.2 V is applied to the tunnel film of the capacitor 32 as a voltage obtained by capacitively dividing the voltage of 10 V into 2: 9. Similarly to the high write operation, in the low write operation, a tunnel current flows through the tunnel film of the capacitor 32, and after a short time, the potential difference is reduced to about 6V.

  That is, negative charges are released from the floating node 35.

  Here, comparing the high write and the low write when the gate capacitance of the detection transistor 41 of the EEPROM 100 cannot be ignored, the voltage applied to the tunnel film of the capacitor 32 differs between the high write and the low write. Specifically, a voltage of about 7.3 V is applied to the tunnel film of the capacitor 32 in high writing, and a voltage of about 8.2 V is applied to the tunnel film of the capacitor 32 in low writing. That is, it means that the charges that are injected and released are not balanced between the high writing and the low writing. Since the capacitance ratio of the capacitors 31 and 32 is C1: C2 = 8: 2, ideally, a voltage of 7.5 V is applied to the tunnel film of the capacitor 32. However, since the gate capacitance of the detection transistor 41 cannot be ignored, an offset is generated in the voltage applied to the tunnel film between high writing and low writing as described above.

  In the EEPROM 100 in which the gate capacitance cannot be ignored, a voltage of about 7.3 V, which is lower than the ideal 7.5 V, is applied to the tunnel film of the capacitor 32 at the time of high writing, so that the electrons injected into the floating node 30 The amount is less than in the state where the ideal 7.5V is applied. That is, the potential of the floating node 30 of the EEPROM 100 becomes higher than that in the ideal high write. When ideal high writing is performed, the potential of the floating node 30 of the EEPROM 100 is sufficiently lower than the threshold value of the detection transistor 41, so that the detection transistor is turned off. However, in the high writing of the EEPROM 100 when the gate capacity cannot be ignored, electrons are not sufficiently injected into the floating node 30 of the EEPROM 100, so that the off state of the detection transistor 41 becomes unstable and is turned on in the worst case. That is, it means that sufficient high writing cannot be performed.

  In the EEPROM 100 in which the gate capacity cannot be ignored, a voltage of about 8.2 V, which is higher than the ideal 7.5 V, is applied to the tunnel film of the capacitor 32 at the time of row writing, so that it is discharged from the floating node 30. The amount of electrons is larger than in the state in which an ideal 7.5V is applied. That is, the potential of the floating node 30 of the EEPROM 100 becomes lower than that in the ideal row writing. When ideal row writing is performed, the potential of the floating node 30 of the EEPROM 100 is sufficiently higher than the threshold value of the detection transistor 41, so that the detection transistor is turned on. However, in the low write of the EEPROM 100 in the case where the gate capacity cannot be ignored, excessive electrons are emitted from the floating node 30, so that overwriting is performed. This damages the tunnel film of the capacitor 32 and accelerates the deterioration.

  Further, even if high writing is performed on the floating node 30 of the cell 10 that has been overwritten (or overerased), the amount of electrons injected by high writing compensates for the amount of electrons that have been excessively emitted. I can't. For this reason, a cell 10 incapable of high writing occurs.

  As described above, the EEPROM 100 in the case where the gate capacitance cannot be ignored has an offset in the amount of electrons injected or emitted into the floating gate 30 between the high writing and the low writing, and thus the EEPROM 100 in the case where the gate capacitance cannot be ignored. However, the operation is unstable and the reliability is low.

  On the other hand, in the EEPROM 130 according to the modified example, the above problem can be solved by the function of the auxiliary capacitor 33. As shown in FIGS. 18 and 19, in the EEPROM 130 according to the modification, the capacity ratio at the time of high write operation is CC1: CC2 = 9: 3, and the capacity ratio at the time of low write operation is CC11: CC12 = 9: 3. is there. That is, both the high write operation and the low write operation have the same capacitance ratio. As a result, in the EEPROM 130 according to the modified example, the same voltage is applied to the tunnel film of the capacitor 32 in each of the high write operation and the low write operation, so that a stable write operation can be performed and the reliability can be maintained. Is possible.

  In the EEPROM 100 in which the gate capacitance cannot be ignored, the voltage applied to the tunnel film of the capacitor 32 is higher during the low write operation than during the high write operation. That is, in the EEPROM 100 in which the gate capacity cannot be ignored, the high write operation is slow and the low write operation is fast. As described above, when the balance between the time required for the high write and the low write is poor, the setting of the program time has to be determined by the slower characteristic. If this balance becomes extremely bad, for example, in the low write operation, the time during which an excessively high voltage is applied becomes long, and the lifetime of the element (for example, the tunnel film of the capacitor 32) is shortened.

  On the other hand, in the EEPROM 130 according to the modified example, the time required for high writing and low writing can be balanced, so that damage given to the tunnel film of the capacitor 32 can be reduced. In other words, the EEPROM 130 according to the modification can stabilize the high write operation and the low write operation, and can improve the reliability.

  Further, in the EEPROM 100 in which the gate capacitance cannot be ignored, when the cell area is reduced for cost reduction, the parasitic capacitance (for example, the gate capacitance of the detection transistor 41) appears to be large at the same time. Impairs the balance of raw writing time. This causes many problems such as the above-mentioned unstable operation and shortening of the device life.

  On the other hand, in the modified EEPROM 130, the influence of the parasitic capacitance can be corrected by the auxiliary capacitor 33, so that the cell area can be reduced while suppressing the deterioration of the balance between the high write time and the low write time. it can. That is, cost reduction by reducing the cell area can be performed more easily than in the comparative example.

  In the modified EEPROM 130, the auxiliary capacitor 33 can be formed, for example, in a region above the region where the capacitor 31 is formed, so that the cell area is not sacrificed. For example, the cell of the modified EEPROM 130 can be formed with the same cell area as that of the EEPROM 100 of the present embodiment, or can be made smaller.

  Although the gate capacitance of the detection transistor 41 is shown as a parasitic capacitance, the present invention is not limited to this. Here, the parasitic capacitance refers to a capacitance parasitic to the floating gate, for example, among the capacitance with respect to the substrate potential. This parasitic capacitance changes the capacitance ratio of the cell 11 between the high write operation and the low write operation.

  In the EEPROM 130 according to the modification, the auxiliary capacitor 33 can correct the change in the capacitance ratio due to these parasitic capacitances. For example, by setting the capacitance of the auxiliary capacitor 33 in consideration of the parasitic capacitance and the gate capacitance of the detection transistor 41, the change in the capacitance ratio can be corrected.

  In the EEPROM 130 of the modified example, an interlayer insulating film formed above the second capacitor 32 and below the metal wiring layer can be formed by HDPCVD. As a result, a trap region is formed in the tunnel film of the capacitor 32, and the writing speed can be improved. In addition, the writing voltage can be lowered by improving the writing speed. Thereby, deterioration of the tunnel film of the capacitor 32 can be suppressed, and a highly reliable nonvolatile semiconductor memory device can be provided.

  In other words, the modified EEPROM 130 can provide a more reliable nonvolatile semiconductor memory device by the auxiliary capacitor 33 and the interlayer insulating film ILD1 formed by the HDPCVD method.

  As described above, the embodiments of the present invention have been described in detail. However, those skilled in the art can easily understand that many modifications can be made without departing from the novel matters and effects of the present invention. . Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, a term described with a different term having a broader meaning or the same meaning at least once in the specification or the drawings can be replaced with the different term anywhere in the specification or the drawings.

1 is a configuration example of a nonvolatile semiconductor memory device according to an embodiment. 4 is a configuration example of a layout of the nonvolatile semiconductor memory device according to the embodiment. Sectional drawing which shows the AA cross section of FIG. 6A and 6B illustrate a manufacturing process of the nonvolatile semiconductor memory device according to the embodiment. FIG. 16 is another view for explaining the manufacturing process of the nonvolatile semiconductor memory device according to the embodiment. FIG. 16 is another view for explaining the manufacturing process of the nonvolatile semiconductor memory device according to the embodiment. FIG. 16 is another view for explaining the manufacturing process of the nonvolatile semiconductor memory device according to the embodiment. FIG. 16 is another view for explaining the manufacturing process of the nonvolatile semiconductor memory device according to the embodiment. FIG. 16 is another view for explaining the manufacturing process of the nonvolatile semiconductor memory device according to the embodiment. 6A and 6B illustrate a manufacturing process of the nonvolatile semiconductor memory device according to the embodiment. FIG. 4 is a diagram for explaining a writing time of the nonvolatile semiconductor memory device according to the embodiment. The figure explaining the write time of the comparative example which concerns on this embodiment. Sectional drawing explaining the effect of the non-volatile semiconductor memory device which concerns on this embodiment The figure which shows the retention characteristic of this embodiment and a comparative example. The figure which shows the modification concerning this embodiment. The other figure which shows the modification which concerns on this embodiment. The other figure which shows the modification which concerns on this embodiment. FIG. 18 is a diagram for explaining a high write operation according to a modification. FIG. 19A and FIG. 19B are diagrams for explaining a row write operation of a modified example. The figure which shows the layout of the modification which concerns on this embodiment. Sectional drawing which shows the AA cross section of FIG.

Explanation of symbols

21 1st selection transistor, 21-G gate electrode formation area,
22 second selection transistor, 22-G gate electrode formation region 30 floating node, 31 first capacitor,
31-1, 31-2 first capacitor forming region, 32 second capacitor,
32-1, 32-2 Second capacitor formation region, 41-1 Gate electrode formation region,
33 auxiliary capacitor, 41 detection transistor, CD control drain voltage,
CDN supply node, CG control gate voltage, CGN supply node,
IDL1 first interlayer insulating film, ILD2 second interlayer insulating film,
PL1 first polysilicon layer, VPP capacitance ratio correction voltage

Claims (18)

A first capacitor having one end connected to the floating node;
A detection transistor whose gate electrode is connected to the floating node;
A second capacitor having one end connected to the floating node and the other end connected to the drain of the detection transistor;
Including
The non-volatile semiconductor memory device, wherein the first interlayer insulating film above the second capacitor is formed by HDPCVD (High-Density-Plasma-Chemical-Vapor-Deposition) method. In claim 1,
The non-volatile semiconductor memory device, wherein the first interlayer insulating film is formed between a polysilicon layer forming an upper electrode of the second capacitor and a metal wiring layer. In claim 2,
The non-volatile semiconductor memory device, wherein the first interlayer insulating film is formed between a second interlayer insulating film formed above the polysilicon layer and a metal wiring layer. In claim 2 or 3,
The nonvolatile semiconductor memory device, wherein the metal wiring layer is formed above the polysilicon layer without interposing a TEOS (TetraEthylOrthoSilisate) film. In any of claims 2 to 4,
The non-volatile semiconductor memory device, wherein the metal wiring layer is formed above the polysilicon layer without interposing a BPSG (Boro-Phospho Silicate Glass) film. In any one of Claims 1 thru | or 5,
The film thickness of the second capacitor insulating film formed between the upper electrode and the lower electrode of the second capacitor is the same as that of the first capacitor formed between the upper electrode and the lower electrode of the first capacitor. Formed thinner than the film thickness,
A non-volatile semiconductor memory device, wherein a charge trap region is formed in the second capacitor insulating film by a bias applied to the substrate by the HDPCVD method. In claim 6,
The area of the region where the second capacitor insulating film is formed is narrower than the area of the region where the first capacitor insulating film is formed,
The non-volatile semiconductor memory device, wherein a capacity of the second capacitor is smaller than a capacity of the first capacitor. In any one of Claims 1 thru | or 7,
A first selection transistor provided between a supply node of the control gate voltage and the other end of the first capacitor;
A second selection transistor provided between a supply node of the control drain voltage and the other end of the second capacitor;
Further including
During write operation,
A selection voltage is supplied to the gate electrodes of the first and second selection transistors, the first and second selection transistors are set to an on state,
The other end of the first capacitor is supplied with the control gate voltage via the first selection transistor set to an on state,
The non-volatile semiconductor memory device, wherein the control drain voltage is supplied to the other end of the second capacitor via the second selection transistor set to an on state. In any one of Claims 1 thru | or 8.
An auxiliary capacitor having one end connected to the floating node;
At least during a write operation
A control gate voltage is supplied to the other end of the first capacitor, a control drain voltage is supplied to the other end of the second capacitor, and a capacitance ratio correction higher than the voltage of the floating node is supplied to the other end of the auxiliary capacitor. A non-volatile semiconductor memory device, wherein a voltage is supplied. In claim 9,
At least during the write operation
The capacitance ratio correction voltage is equal to or higher than the higher of the voltage supplied to one end of the first capacitor and the voltage supplied to the other end of the second capacitor. A non-volatile semiconductor memory device, wherein In claim 9 or 10,
The non-volatile semiconductor memory device, wherein the capacitance value of the auxiliary capacitor is set to the same value as the gate capacitance value of the detection transistor. In any of claims 9 to 11,
The non-volatile semiconductor memory device, wherein the auxiliary capacitor is formed in a region above a first capacitor forming region where the first capacitor is formed. In claim 12,
A second capacitor forming region in which the second capacitor is formed is formed on a first direction side of the first capacitor forming region;
The non-volatile semiconductor memory device, wherein the area of the second capacitor formation region is narrower than that of the first capacitor formation region. In claim 13,
When the direction orthogonal to the first direction is the second direction,
A detection transistor gate electrode formation region in which a gate electrode of the detection transistor is formed is on the first direction side of the first capacitor formation region, and the second capacitor formation region has the second A non-volatile semiconductor memory device formed on a direction side. A first capacitor having one end connected to the floating node;
A detection transistor whose gate electrode is connected to the floating node;
Including
The first interlayer insulating film above the polysilicon layer forming the gate electrode of the detection transistor is formed by HDPCVD (High-Density-Plasma-Chemical-Vapor-Deposition) method. Semiconductor memory device. A first capacitor having one end connected to the floating node;
A detection transistor whose gate electrode is connected to the floating node;
A method for manufacturing a nonvolatile semiconductor memory device including:
Forming a polysilicon layer for forming a gate electrode of the detection transistor;
Forming a second interlayer insulating film above the polysilicon layer;
Forming a first interlayer insulating film above the second interlayer insulating film;
Including
The method of manufacturing a nonvolatile semiconductor memory device, wherein the first interlayer insulating film is formed by an HDPCVD (High-Density-Plasma-Chemical-Vapor-Deposition) method. A first capacitor having one end connected to the floating node;
A detection transistor whose gate electrode is connected to the floating node;
A second capacitor having one end connected to the floating node and the other end connected to the drain of the detection transistor;
A method for manufacturing a nonvolatile semiconductor memory device including:
Forming a polysilicon layer forming an upper electrode of the second capacitor;
Forming a second interlayer insulating film above the polysilicon layer;
Forming a first interlayer insulating film above the second interlayer insulating film;
Including
The method of manufacturing a nonvolatile semiconductor memory device, wherein the first interlayer insulating film is formed by an HDPCVD (High-Density-Plasma-Chemical-Vapor-Deposition) method. In claim 16 or 17,
A method for manufacturing a nonvolatile semiconductor memory device, comprising the step of forming a metal wiring layer above the first interlayer insulating film.

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