JP2006294061A - メモリ管理 - Google Patents
メモリ管理 Download PDFInfo
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- JP2006294061A JP2006294061A JP2006194909A JP2006194909A JP2006294061A JP 2006294061 A JP2006294061 A JP 2006294061A JP 2006194909 A JP2006194909 A JP 2006194909A JP 2006194909 A JP2006194909 A JP 2006194909A JP 2006294061 A JP2006294061 A JP 2006294061A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7201—Logical to physical mapping or translation of blocks or pages
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0662—Virtualisation aspects
- G06F3/0664—Virtualisation aspects at device level, e.g. emulation of a storage device or system
Abstract
【解決手段】各論理セクタアドレス値用のデータブロックおよび複数の予備データブロックを使用して、論理セクタアドレスと対応する物理アドレスとの間のマッピングを維持する方法。各データブロックは、直接アドレスフィールドおよび間接アドレスフィールドを含む。論理セクタアドレスにデータが最初に書き込まれたときに、直接アドレスフィールドは、対応する物理アドレスでプログラムされる。その後、同じ論理セクタアドレスにデータが書き込まれるたびに、間接アドレスフィールドが予備データブロックのアドレスでプログラムされ、予備データブロックの直接アドレスフィールドがそのデータの新しい物理アドレスでプログラムされる。
【選択図】図1A
Description
第一のアドレスと対応する第二のアドレスとの間のマッピングを維持する方法であって、使用していないデータブロックの数が所定のしきい値を下まわったときにデータブロックがクリーンアップされる方法。
Claims (1)
- ホストシステムとともに用いられるデータ記憶システムであって、
該データ記憶システムは、
複数の消去可能なソリッドステートデータ記憶手段(20)であって、該複数の消去可能なソリッドステートデータ記憶手段の各々は、一意的な物理アドレスによって位置を特定することができ、かつ、一度書き込まれると、再書き込みされる前に消去されなければならない、複数の消去可能なソリッドステートデータ記憶手段(20)と、
該ホストから受け取られた複数の論理アドレスを該複数の消去可能なソリッドステートデータ記憶手段の対応する複数の物理アドレスにマッピングするルックアップテーブルを記憶する不揮発性のブロック消去可能な記憶手段を含む制御手段(12、22)と
を備え、
該制御手段の記憶手段は、複数のデータブロックを含み、該複数の論理アドレスの各々に対してそれぞれのデータブロックが存在し、
該制御手段は、複数の予備データブロックをさらに含み、
各データブロックと各予備データブロックは、直接アドレスフィールド(14)と間接アドレスフィールド(16)とを含み、
該制御手段は、
該データ記憶手段に書き込まれるためのデータとともに論理アドレスが該ホストから供給される場合には、該論理アドレスに対応する物理アドレスを用いて該記憶手段の各データブロックの直接アドレスフィールドをプログラムする手段と、
新しいデータが同一の論理アドレスに書き込まれる場合には、使用されていない予備データブロックのアドレスを用いて各データブロックの間接アドレスフィールドをプログラムし、かつ、該同一の論理アドレスに対応する新しい物理アドレスを用いて該予備データブロックの該直接アドレスフィールドをプログラムする手段と
をさらに含む、データ記憶システム。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9519669A GB2291990A (en) | 1995-09-27 | 1995-09-27 | Flash-memory management system |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9513195A Division JP2000505215A (ja) | 1995-09-27 | 1996-02-06 | メモリ管理 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007191421A Division JP2007280428A (ja) | 1995-09-27 | 2007-07-23 | メモリ管理 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2006294061A true JP2006294061A (ja) | 2006-10-26 |
Family
ID=10781331
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9513195A Pending JP2000505215A (ja) | 1995-09-27 | 1996-02-06 | メモリ管理 |
JP2006194909A Withdrawn JP2006294061A (ja) | 1995-09-27 | 2006-07-14 | メモリ管理 |
JP2007191421A Pending JP2007280428A (ja) | 1995-09-27 | 2007-07-23 | メモリ管理 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9513195A Pending JP2000505215A (ja) | 1995-09-27 | 1996-02-06 | メモリ管理 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007191421A Pending JP2007280428A (ja) | 1995-09-27 | 2007-07-23 | メモリ管理 |
Country Status (8)
Country | Link |
---|---|
EP (1) | EP0852765B1 (ja) |
JP (3) | JP2000505215A (ja) |
KR (1) | KR19990063714A (ja) |
CN (1) | CN1197520A (ja) |
AT (1) | ATE205946T1 (ja) |
DE (1) | DE69615385D1 (ja) |
GB (1) | GB2291990A (ja) |
WO (1) | WO1997012324A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012068863A (ja) * | 2010-09-22 | 2012-04-05 | Toshiba Corp | 半導体記憶制御装置 |
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-
1995
- 1995-09-27 GB GB9519669A patent/GB2291990A/en not_active Withdrawn
-
1996
- 1996-02-06 WO PCT/GB1996/000249 patent/WO1997012324A1/en not_active Application Discontinuation
- 1996-02-06 AT AT96901894T patent/ATE205946T1/de not_active IP Right Cessation
- 1996-02-06 CN CN96197203A patent/CN1197520A/zh active Pending
- 1996-02-06 JP JP9513195A patent/JP2000505215A/ja active Pending
- 1996-02-06 DE DE69615385T patent/DE69615385D1/de not_active Expired - Lifetime
- 1996-02-06 KR KR1019980702181A patent/KR19990063714A/ko not_active Application Discontinuation
- 1996-02-06 EP EP96901894A patent/EP0852765B1/en not_active Expired - Lifetime
-
2006
- 2006-07-14 JP JP2006194909A patent/JP2006294061A/ja not_active Withdrawn
-
2007
- 2007-07-23 JP JP2007191421A patent/JP2007280428A/ja active Pending
Cited By (1)
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JP2012068863A (ja) * | 2010-09-22 | 2012-04-05 | Toshiba Corp | 半導体記憶制御装置 |
Also Published As
Publication number | Publication date |
---|---|
WO1997012324A1 (en) | 1997-04-03 |
DE69615385D1 (de) | 2001-10-25 |
JP2000505215A (ja) | 2000-04-25 |
KR19990063714A (ko) | 1999-07-26 |
ATE205946T1 (de) | 2001-10-15 |
EP0852765B1 (en) | 2001-09-19 |
JP2007280428A (ja) | 2007-10-25 |
GB9519669D0 (en) | 1995-11-29 |
CN1197520A (zh) | 1998-10-28 |
EP0852765A1 (en) | 1998-07-15 |
GB2291990A (en) | 1996-02-07 |
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