JP2006293824A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which is capable of detecting erroneous access to restricted resources in the case that a memory size or peripheral functions are restricted in a mask ROM microcomputer chip to be mounted on a final set with respect to an emulation chip supporting software development of the final set. <P>SOLUTION: An access monitor circuit 1003 for monitoring operations of a bus controller 1006 is provided. When being connected to a debugging host as the emulation chip, the access monitor circuit 1003 determines an access from the bus controller 1006 to be invalid in the case that an object address of the access is within an invalid address range set to an invalid address table part 1004 as an invalid access, and causes an invalid access detection interruption to a CPU 1002. The CPU 1002 receives this interruption to inform the debugging host of detection of the invalid access through a debugging I/F 110. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device that provides a software debugging environment according to its base product in a series of microcontrollers and microcomputers having variations in built-in memory size and built-in peripheral circuits.

  In semiconductor device vendors, microcontrollers and microcomputers (hereinafter simply referred to as microcomputers) are usually developed as series products with variations in built-in memory sizes and built-in peripheral circuits. For example, in the product series with a built-in instruction ROM, there are a product using a flash memory for the command ROM and a product using a mask ROM, and a product in which the memory size of the mask ROM is changed is prepared.

  Mask ROM products are often applied from the standpoint of cost when mass production is performed by semiconductor device users.

  In addition, semiconductor device vendors provide development support tools (also called emulators) such as an in-circuit emulator (ICE) and an on-board debugger for conducting software development and system evaluation of a set. The development support tool includes an emulation chip mounted on a set or a wiring board equivalent to the set, and a debug host that controls the emulation chip and exchanges debug information with the set developer.

  A semiconductor device user develops software on a set mounted with an emulation chip or a printed circuit board equivalent to the set (hereinafter simply referred to as a target), and obtains a mask ROM product by turning this software into a mask ROM. Mass-produce the final set.

  However, emulation chips are often created or combined based on products with the largest built-in memory size and peripheral circuit scale among the series products, and the mask ROM types that are applied to set mass production are those with built-in memory size and peripheral functions. It may not always match. Furthermore, the type that is the base of the emulation chip or the type that also serves as the emulation chip is often developed in advance, not simultaneously with the series of mask ROM types. In addition, in the product type that is the base of this emulation chip, the built-in instruction ROM is not a mask ROM, but may be a flash memory or an EPROM to meet the requirements of set prior production.

  That is, the final set may not operate normally because the internal memory size and peripheral functions of the microcomputer executing the software do not always match between the target and the final set.

  In order to solve such a problem fundamentally, it is necessary to create an emulation chip for each type of mask ROM having different built-in memory sizes and peripheral functions, which is very expensive. Also, since the emulation chip is used for software development of the set, it must be created prior to the development of the mask ROM type, which greatly increases the man-hours at the vendor.

As a solution to the above case, there is one disclosed in Patent Document 1 for an emulator in the case of corresponding to a series having different built-in peripheral functions. In the technique disclosed in Patent Document 1, a product type identification register is provided in an emulation chip, and peripheral functions are selectively activated according to the product type code stored in the product type identification register each time the emulator is powered on. It is to become.
Japanese Patent Laid-Open No. 3-263132

  However, even if peripheral functions are selectively activated according to the product code as in the prior art, software that erroneously accesses peripheral functions that are inactive during set development is created, and the mask ROM of the corresponding product code is created. If the flash product of the base product is applied to the pre-production before the product is available, malfunction may occur in the base product. That is, there is no means for detecting that an inactive peripheral function has been accessed by mistake, and this problem occurs because the software developer is not notified.

  Further, in the above prior art, there is a problem that erroneous access to the limited memory area is not detected for the same reason even when the memory size such as ROM and RAM is limited in the mask ROM compared to the base type.

  Furthermore, the peripheral function is, for example, a general-purpose serial circuit, and several serial resources can be selected. However, since the applicable set is determined when the mask ROM is used, the mask ROM product is designed to simplify the circuit. In the case of mounting a dedicated serial circuit, there is a problem that the restriction in the mask ROM product cannot be detected in order to activate the entire general-purpose serial circuit.

  An object of the present invention relates to an emulator for developing software for a mask ROM product that uses an emulation chip using a base product of a series and whose memory size and peripheral functions are limited as compared to the base product. Provided is a semiconductor device capable of providing an emulation chip and a debugging environment corresponding to a semiconductor device to a set developer who is a debugger user at an early stage and at a low cost, and capable of detecting erroneous access to a limited resource. There is.

  A first semiconductor device of the present invention includes a central processing unit and a plurality of internal resources, and is a series product composed of a plurality of products having variations in one or both of the area and function of any of the plurality of internal resources. A debug information input / output device that communicates with an external debug host, and a product information storage area that stores product information of other product types in the series product. When the information input / output device and the debug host are connected, the operation of another product is performed based on the product information stored in the product information storage area.

  Here, the internal resource is a memory or a peripheral circuit built in the semiconductor device. The product type information represents the presence or absence of each internal resource or the effective address range. For example, in the case of a built-in memory, due to the difference in capacity, the corresponding space mapped at the upper level becomes invalid in a small-capacity product compared to a large-capacity product, so such invalid space / effective space information becomes product type information. .

  In addition, the second semiconductor device includes a product information storage area by a debug program that is activated by a debug interrupt and executed by the central processing unit when the debug information input / output device and the debug host are connected in the first semiconductor device. It is characterized in that the product information is written to the device.

  In the third semiconductor device, when the debug information input / output device and the debug host are connected to each other in the first semiconductor device, the product information is written into the product information storage area by a built-in sequencer immediately after startup. It is characterized by that.

  In addition, the fourth semiconductor device is the first to third semiconductor devices, and other types have limited internal resource areas compared to one type, and the debug information input / output device and the debug host. When a restricted internal resource is determined based on the product type information stored in the product type information storage area, and the central processing unit has access to write or read the restricted internal resource area This access is judged to be invalid access and is ignored.

  In addition, the fifth semiconductor device is the first to third semiconductor devices, and other types have limited internal resource areas compared to one type, and the debug information input / output device and the debug host. When a restricted internal resource is determined based on the product type information stored in the product type information storage area, and the central processing unit has access to write or read the restricted internal resource area This access is judged to be invalid access, and it operates to write or read fixed value invalid data.

  In addition, the sixth semiconductor device is the first to third semiconductor devices, and the other resources are limited in the area of any internal resources as compared to the one product, and the debug information input / output device and the debug host. When a restricted internal resource is determined based on the product type information stored in the product type information storage area, and the central processing unit has access to write or read the restricted internal resource area This access is judged to be invalid access, and random invalid data is written or read.

  Also, the seventh semiconductor device is the first to sixth semiconductor devices, and the other types have limited internal resource areas compared to the one type, and the debug information input / output device and the debug host When a restricted internal resource is determined based on the product type information stored in the product type information storage area, and the central processing unit has access to write or read the restricted internal resource area This access is determined to be invalid access, and operates to transmit invalid access detection information to one or both of the central processing unit and the debug information input / output device.

  In addition, the eighth semiconductor device is the first to seventh semiconductor devices, and other types have limited internal resource areas compared to one type, and the debug information input / output device and the debug host When the connection is established, the restricted internal resource is determined based on the product information stored in the product information storage area, and the central processing unit has write access so as to activate the restricted internal resource region. If there is, it is determined that this access is an invalid access, and the operation is performed to transmit invalid access detection information to one or both of the central processing unit and the debug information input / output device.

  According to the first semiconductor device of the present invention, there is provided a debug information input / output device that communicates with an external debug host, and a product information storage area that stores product information of other products of the series, and includes debug information. Emulation chip corresponding to each semiconductor device of the series product type by performing the operation of other product types based on the product type information stored in the product type information storage area when connecting the I / O device and debug host In addition, it is possible to provide a debugging environment to a set developer who is a debugger user early and inexpensively.

  According to the second semiconductor device of the present invention, when connecting to the debug host, the product information is written to the product information storage area by the debug program started by the debug interrupt and executed by the central processing unit. The product information can be sent from the debug host, and it can support various series products.

  According to the third semiconductor device of the present invention, since the product information is written into the product information storage area by the built-in sequencer immediately after startup when connected to the debug host, the product information storage area on the semiconductor device. The product information stored in the nonvolatile or volatile information storage area provided separately can be written without using the debug program, and the operation of the other products in the series is performed before the start of the user program execution. It is possible.

  According to the fourth semiconductor device of the present invention, at the time of connection with the debug host, the restricted internal resource is determined based on the kind information stored in the kind information storage area, and the restricted internal resource area is determined. When there is a write or read access from the central processing unit, this access is judged as invalid access and the operation is ignored, so that the operation of other products in the series can be performed on behalf of the user of that product type. It is possible to reproduce the behavior of the program.

  According to the fifth semiconductor device of the present invention, at the time of connection with the debug host, the restricted internal resource is determined based on the kind information stored in the kind information storage area, and the restricted internal resource area is determined. When there is a write or read access from the central processing unit to this, it is determined that this access is an invalid access, and it operates to write or read fixed-value invalid data. It is possible to detect errors in user programs that erroneously access restricted internal resources.

  According to the sixth semiconductor device of the present invention, at the time of connection with the debug host, the restricted internal resource is determined based on the kind information stored in the kind information storage area, and the restricted internal resource area is determined. When there is a write or read access from the central processing unit, this access is judged to be invalid access, and random invalid data is written or read. It is possible to detect an error in a user program that erroneously accesses a limited internal resource.

  According to the seventh semiconductor device of the present invention, at the time of connection with the debug host, the restricted internal resource is determined based on the kind information stored in the kind information storage area, and the restricted internal resource area is determined. When there is a write or read access from the central processing unit, this access is determined to be invalid access, and invalid access detection information is transmitted to one or both of the central processing unit and debug information input / output device. Since it operates, it is possible to perform operations of other varieties of the series, and it is possible to detect an error of a user program that erroneously accesses a limited internal resource.

  According to the eighth semiconductor device of the present invention, at the time of connection with the debug host, the restricted internal resource is determined based on the product information stored in the product information storage area, and the restricted internal resource area is determined. If there is a write access from the central processing unit so as to activate it, this access is judged as invalid access, and information on invalid access detection is transmitted to one or both of the central processing unit and debug information input / output device. Therefore, it is possible to perform the operations of other varieties of the series, and it is possible to detect an error of the user program that erroneously activates the limited internal resource.

(First embodiment)
A first embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 shows a microcontroller chip according to a first embodiment of the present invention. The microcontroller chip 101 is a series base product and incorporates a flash memory (Flash ROM 103) as an instruction ROM. At the time of pre-set production, the user program can be written in the built-in flash memory (103) and mounted in the final set. The microcontroller chip 101 can also be used as an emulation chip for user program development. When used as an emulation chip, it is mounted on a wiring board equivalent to a set or connected to a debug host to input / output debug information.

  FIG. 2 shows the memory size, its address increase, the presence / absence of peripheral circuits, and the address map of each control register in the base type of the microcontroller shown in FIG. Yes. Mask ROM types A and B have a built-in mask ROM as an instruction ROM, and are mounted on a final set where mass production is performed.

  As shown in FIG. 2, the mask ROM type A has the same base type, memory size, peripheral functions, and their address mapping, but the mask ROM type B differs. That is, the mask ROM type B has a memory size that is halved in both ROM and RAM, and is an effective area only on the younger address side, and no peripheral circuit B is mounted for peripheral functions.

  As shown in FIG. 1, a microcontroller chip 101 of a base type that also serves as an emulation chip includes a CPU 102 that controls the entire chip by executing instructions, and a Flash ROM 103 that stores user programs and supplies user program instructions to the CPU 102. , A bus controller 104 controlled by the CPU 102 and the access monitoring circuit 109 to control the internal bus 105, an SRAM 106 to which data is input / output from the CPU 102 via the internal bus 105, an internal control register, and from the CPU 102 via the internal bus 105. A peripheral circuit A 107 and a peripheral circuit B 108 whose execution of peripheral functions is controlled by setting a value in the control register, an access monitoring circuit 109 that monitors the bus controller 104, and the CPU 102 are connected to the software. And a debug I / F110 to output the debug information to the debug host during wear debugging.

  The access monitoring circuit 109 is set in the invalid address table unit 111 to which invalid address range data corresponding to the mask ROM type is written via the bus controller 104, and the target address and invalid address table unit 111 to be accessed by the bus controller 104. And an address comparison unit 112 for comparing the invalid address range.

  When the invalid address range data is not written in the invalid address table unit 111, the access monitoring circuit 109 does not monitor the access of the bus controller 104 and does not act on the bus controller 104, and the invalid address range data is written. In this case, the access of the bus controller 104 is monitored.

  The access monitoring circuit 109 monitors the access of the bus controller 104, and the result of the address comparison unit 112 indicates that the target address to be accessed by the bus controller 104 is outside the invalid address range, that is, the access to the valid area. If there is, it is determined as a valid access and does not act on the bus controller 104, and if the target address to be accessed by the bus controller 104 is within the invalid address range, this is determined as an invalid access and the access is made. When the address is a write, the bus controller 104 is ignored so that it is not written to the target address. When the access is a read, the target address is not read and the CPU 102 does not read the fixed address as an invalid read value. Bus controller 104 to return It acts.

  Next, the operation of the microcontroller chip 101 will be described. As an example of the operation, a case where a user program is written in the flash ROM 103 of the microcontroller chip 101, mounted in the final set, and operating on the final set will be described with reference to the flowchart of FIG.

  In FIG. 3, a period 301 is an operation until the execution of the user program is started, and the mask ROM microcomputer is the same operation.

  A period 302 is a case where the user program performs a write operation (write operation) on the address of the control register of the peripheral circuit B108. Since invalid address range data is not written in the access monitoring circuit 109, access monitoring is not performed. This write operation is executed as usual, and a value is set in the control register of the peripheral circuit B108.

  Period 303 is a case where the user program performs a read operation (read operation) at address 0x00003000 in the built-in SRAM 106. Since the invalid address range data is not written in the access monitoring circuit 109, access monitoring is not performed. The operation is executed as usual, and the data stored at address 0x00003000 of the built-in SRAM 106 is returned to the CPU 102.

  As the next example of the operation of the microcontroller chip 101, the microcontroller chip 101 is mounted on the set as an emulation chip, connected to the debug host and operates as an emulation chip, and the set developer develops software for the mask ROM type A The case of performing the above will be described with reference to the flowchart of FIG.

  In FIG. 4, a period 401 is an operation until the execution of the user program is started, and the mask ROM microcomputer is the same operation.

  During a period 402, a debug interrupt is issued from the debug host through the debug I / F 110 during execution of the user program. During this period, the invalid address range data of the mask ROM type A passes from the debug host via the debug I / F 110 and the CPU 102 as the type information. Is sent to the access monitoring circuit 109 via the bus controller 104.

  The product type information represents the presence or absence of an internal resource such as a memory or a peripheral circuit, or an effective address range. For example, in the case of a built-in memory, due to the difference in capacity, the corresponding space mapped at the upper level becomes invalid in a small-capacity product compared to a large-capacity product, so such invalid space / effective space information becomes product type information. . Further, when the peripheral circuit B is not mounted as in the ROM type B, information that the address mapping of the peripheral circuit B is invalid becomes the type information.

  Here, since the invalid address range data is written, the access monitoring circuit 109 sets the invalid address range of the mask ROM type A in the invalid address table unit 111 and monitors the operation of the bus controller 104.

  The period 403 is a case where the user program performs a write operation on the address of the control register of the peripheral circuit B108, and the access monitoring circuit 109 monitors the access, but this write operation is performed to an address effective in the mask ROM type A. Since the access monitoring circuit 109 determines that the access is valid and does not act on the bus controller 104, this write operation is executed as usual and a value is set in the control register of the peripheral circuit B108.

  Period 404 is a case where the user program performs a read operation at address 0x00003000 of the built-in SRAM 106, and the access monitoring circuit 109 monitors the access, but this read operation is an access to an address effective in the mask ROM type A. Therefore, the access monitoring circuit 109 determines that the access is valid and does not act on the bus controller 104. Therefore, this read operation is executed as usual, and the data stored at address 0x00003000 in the built-in SRAM 106 is returned to the CPU 102.

  As the next example of the emulation chip operation of the microcontroller chip 101, the microcontroller chip 101 is mounted on the set as an emulation chip, connected to the debug host, and the set developer develops software for the mask ROM type B This case will be described with reference to the flowchart of FIG.

  In FIG. 5, a period 501 is an operation until the execution of the user program is started, and is the same operation as the mask ROM microcomputer.

  During a period 502, a debug interrupt is issued from the debug host through the debug I / F 110 during execution of the user program. During this period, the invalid address range data of the mask ROM type B passes from the debug host via the debug I / F 110 and the CPU 102 as the type information. Is sent to the access monitoring circuit 109 via the bus controller 104.

  Here, since the invalid address range data is written, the access monitoring circuit 109 sets the invalid address range of the mask ROM type B in the invalid address table unit 111 and monitors the operation of the bus controller 104.

  The period 503 is a case where the user program has not been debugged yet, so that the write operation is erroneously performed on the address of the control register of the peripheral circuit B108. The access monitoring circuit 109 monitors the access, and this write operation is performed by the mask ROM. Since the access is to an invalid address that is not mounted in the product type B, the access monitoring circuit 109 determines that the access is invalid and acts on the bus controller 104 not to execute the write operation. Therefore, this write operation is ignored and no value is set in the control register of the peripheral circuit B108, and the initial state remains unchanged.

  A period 504 is a case where the user program has not been debugged yet and the read operation is erroneously performed at address 0x00003000 in the built-in SRAM 106. The access monitoring circuit 109 monitors the access, and this read operation is the mask ROM type B. The access monitoring circuit 109 determines that the access is invalid and does not execute the read operation on the bus controller 104 because the access is to an invalid address that is not implemented in the. Therefore, this read operation is ignored, the read operation is not performed to the built-in SRAM 106, and invalid data is returned to the CPU 102.

  In the case of accessing a valid address, the access monitoring circuit 109 determines that the access is valid and does not act on the bus controller 104, and the bus controller 104 operates normally.

  By operating as described above, the microcontroller chip 101 can operate as a base product, and when connected to a debug host as an emulation chip, product information is sent to the access monitoring circuit 109 by a debug interrupt. By setting, the function of the mask ROM type A or B can be substituted.

  If the function of the mask ROM type B is substituted, the write to the invalid address is ignored and the invalid data is returned for the read to the invalid address as with the mask ROM type B. It is possible to know the behavior of the program in the mask ROM type B, and it is possible to prevent in advance problems when the mask ROM type is applied to the mass production set.

  In the above configuration, invalid address range data is transferred from the debug host as product type information, but it is stored in a flash memory or the like in a non-volatile manner, or a means for holding product type information volatilely on the chip is provided for debugging. The same effect can be obtained even when the product information is set in advance.

  In the above configuration, invalid address range data that varies depending on the product type is transferred and stored in the invalid address table unit 111. However, it is also possible to transfer the product number information and decode the invalid address range data from the product number information. It is.

  In the above configuration, for simplicity of explanation, one instruction ROM and one SRAM and two peripheral circuits are mounted. However, depending on the configuration or elements each element has one or more, it is not mounted. A configuration is also possible.

  In the above configuration, the invalid data is set to the fixed value all_0, but the same effect can be obtained with any other fixed value.

  Further, in the above configuration, the read operation to the target address is not performed at the time of invalid access, but the read operation to the target address may be performed and invalid data may be returned to the CPU 102.

  Further, in the above configuration, the write operation to the target address is not performed at the time of invalid access, but the configuration may be such that the write operation of fixed value invalid data to the target address is performed.

  In the above configuration, the product information is transferred from the debug host after the start of execution of the user program, but the product information is transferred from the debug host before execution of the user program. Good.

(Second Embodiment)
A second embodiment of the present invention will be described with reference to FIGS.

  FIG. 6 shows a microcontroller chip according to a second embodiment of the present invention. Like the microcontroller chip 101, this microcontroller chip 601 is a base product of the series and has a built-in flash memory (FlashROM 603) as an instruction ROM, which can be mounted in the final set and is an emulation for user program development. It can also be used as a chip.

  As shown in FIG. 6, the microcontroller chip 601 of the base type also serving as an emulation chip includes an access monitoring circuit 602 that monitors the operation of the bus controller 104, a user ROM area 604 that stores a user program, and an invalid address of the mask ROM type. A flash ROM 603 having a product type data area 605 for storing range data and supplying user program instructions to the CPU 608; a sequencer 606 for automatically transferring invalid address range data stored in the product data area 605 of the flash ROM 603 to the access monitoring circuit 602; A debug I / F 607 that transmits the connection status with the debug host to the sequencer 606, connects to the CPU 608, and inputs / outputs debug information to / from the debug host during software debugging, 606 is controlled count start suppression of the program counter by comprises a CPU608 for controlling the entire chip by executing the instruction, the same components (105, 106, 107, 108) and the microcontroller chip 101 to other.

  The sequencer 606 is activated when the microcontroller chip 601 is connected to the debug host, and transfers invalid address range data stored in the product data area 605 of the Flash ROM 603 to the access monitoring circuit 602 until the start of user program execution. .

  The access monitoring circuit 602 sets the invalid address table unit 609 to which an invalid address range corresponding to the mask ROM type is written via the internal bus 105 by the sequencer 606, and the address to be accessed by the bus controller 104 and the invalid address table unit 609. And an address comparison unit 610 that compares the invalid address range.

  When the invalid address range data is not written in the invalid address table unit 609, the access monitoring circuit 602 does not monitor the access of the bus controller 104 and does not act on the bus controller 104, and the invalid address range data is written. In this case, the access of the bus controller 104 is monitored.

  The access monitoring circuit 602 monitors the access of the bus controller 104, and the result of the address comparison unit 610 indicates that the address to be accessed by the bus controller 104 is outside the invalid address range, that is, an access to a valid area. If the address is determined to be valid access and does not act on the bus controller 104, and the address to be accessed by the bus controller 104 is within the invalid address range, this is determined to be invalid access and the invalid address is set. In the case of writing, the bus controller 104 is ignored so that it is not written to the target address. In the case of reading an invalid address, the target address is not read and the CPU 608 has a fixed value as an invalid read value. bus controller 10 to return all_0 Acting on.

  Next, the operation of the microcontroller chip 601 will be described. The case where the user program is written in the flash ROM 603 of the microcontroller chip 601 and is mounted on the final set and is operating on the final set is the same as that of the microcontroller chip 101.

  As an example of the emulation chip operation of the microcontroller chip 601, the microcontroller chip 601 is mounted on the set as an emulation chip, connected to the debug host, and the set developer uses the software for the mask ROM type B shown in FIG. A case where development is performed will be described with reference to the flowchart of FIG. Prior to set debugging, the type information of the mask ROM type B is written in the type data area 605 of the flash ROM 603 by a ROM writer or the like, and the type information is held in a nonvolatile manner.

  In FIG. 7, a period 701 is an operation until the execution of the user program is started. Since the debug I / F 607 detects that the microcontroller chip 601 is connected to the debug host, the sequencer immediately after the internal reset is released. 606 starts.

  In the period 702, the sequencer 606 suppresses the start of counting of the program counter of the CPU 608 by the activation of the sequencer 606, and the invalid address range data of the mask ROM type B stored in the type data area 605 of the FlashROM 603 during the program count suppression. The data is transferred via the internal bus 105 and written to the access monitoring circuit 602. Since the invalid address range data is written, the access monitoring circuit 602 sets the invalid address range corresponding to the mask ROM type B in the invalid address table unit 609 and monitors the operation of the bus controller 104. When the transfer of the invalid address range data to the access monitoring circuit 602 is completed, the sequencer 606 cancels the count start suppression of the program counter of the CPU 608, so the CPU 608 starts executing the user program.

  The period 703 is a case where the user program has not been debugged yet, so that the write operation is erroneously performed on the address of the control register of the peripheral circuit B108. The access monitoring circuit 602 monitors the access, and this write operation is performed by the mask ROM. Since the access is to an invalid address that is not mounted in the product type B, the access monitoring circuit 602 determines that the access is invalid and acts on the bus controller 104 not to execute the write operation. Therefore, this write operation is ignored and no value is set in the control register of the peripheral circuit B108, and the initial state remains unchanged.

  The period 704 is a case where the user program has not been debugged yet, so that the read operation is mistakenly performed at the address 0x00003000 of the built-in SRAM 106. The access monitoring circuit 602 monitors the access. The access monitoring circuit 602 determines that the access is invalid, and thus does not execute the read operation on the bus controller 104. Therefore, this read operation is ignored, the read operation is not performed on the built-in SRAM 106, and invalid data is returned to the CPU 608.

  In the case of accessing a valid address, the access monitoring circuit 602 determines that the access is valid and does not act on the bus controller 104, and the bus controller 104 operates normally.

  By operating as described above, the microcontroller chip 601 can operate as a base product, and when connected to a debug host as an emulation chip, product information is automatically set before executing a user program. Therefore, the function of the mask ROM type A or B can be substituted.

  If the function of the mask ROM type B is substituted, the write to the invalid address is ignored and the invalid data is returned for the read to the invalid address as with the mask ROM type B. It is possible to know the behavior of the program in the mask ROM type B, and it is possible to prevent in advance problems when the mask ROM type is applied to the mass production set.

  In the above configuration, the product information is stored in the flash memory in a nonvolatile manner. However, the product information is volatilely stored, and the product information is directly set from the debug host before the sequencer 606 is started. Even if this is done, the same effect can be obtained.

  In the above configuration, invalid address range data that differs depending on the product type is transferred and stored in the invalid address table unit 609. However, it is also possible to transfer the product number information and decode the invalid address range data from the product number information. It is.

  In the above configuration, for simplicity of explanation, one instruction ROM and one SRAM and two peripheral circuits are mounted. However, depending on the configuration or elements each element has one or more, it is not mounted. A configuration is also possible.

  In the above configuration, the invalid data is set to the fixed value all_0, but the same effect can be obtained with any other fixed value.

  In the above configuration, the read operation to the target address is not performed at the time of invalid access. However, the read operation to the target address may be performed and invalid data may be returned to the CPU 608.

  Further, in the above configuration, the write operation to the target address is not performed at the time of invalid access, but the configuration may be such that the write operation of fixed value invalid data to the target address is performed.

  In the above configuration, the sequencer 606 is activated after the internal reset is released when the debug host is connected. However, the sequencer 606 may be activated before the internal reset is released when the debug host is connected. .

(Third embodiment)
A third embodiment of the present invention will be described with reference to FIGS.

  FIG. 8 shows a microcontroller chip according to a third embodiment of the present invention. Like the microcontroller chip 101, this microcontroller chip 801 is a base product of the series and incorporates a flash memory (Flash ROM 103) as an instruction ROM, can be mounted in the final set, and is an emulation for user program development. It can also be used as a chip.

  As shown in FIG. 8, a microcontroller chip 801 of the base type that also serves as an emulation chip includes a bus controller 802 that is controlled by the CPU 102 and the access monitoring circuit 803 to control the internal bus 105, a random number generator 804, and a bus controller 802. An access monitoring circuit 803 that monitors the operation and other components (102, 103, 105, 106, 107, 108, 110) similar to the microcontroller chip 101 are provided.

  The access monitoring circuit 803 includes a random number generator 804, an invalid address table unit 805 to which invalid address range data corresponding to the mask ROM type is written via the internal bus 105, and an address and invalid address table to be accessed by the bus controller 802. An address comparison unit 806 that compares the invalid address range set in the unit 805.

  When the invalid address range data is not written in the invalid address table unit 805, the access monitoring circuit 803 does not monitor the access of the bus controller 802 and does not act on the bus controller 802, and invalid address range data is written. In this case, the access of the bus controller 802 is monitored.

  The access monitoring circuit 803 monitors the access of the bus controller 802, and the result of the address comparison unit 806 indicates that the address to be accessed by the bus controller 802 is outside the invalid address range, that is, an access to a valid area. If it is determined that the access is valid, it does not act on the bus controller 802, and if the address to be accessed by the bus controller 802 is within the invalid address range, it is determined that the access is invalid and the invalid address is entered. In the case of writing, the bus controller 802 is ignored so that it is not written to the target address. In the case of reading the invalid address, the random number generator 804 is built in as an invalid read value without reading the target address. Is a random value that occurs each time the CPU 102 Acting on the bus controller 802 to return.

  Next, the operation of the microcontroller chip 801 will be described. The case where the user program is written in the built-in flash memory of the microcontroller chip 801, mounted in the final set, and operating on the final set is the same as that of the microcontroller chip 101.

  As an example of the emulation chip operation of the microcontroller chip 801, the microcontroller chip 801 is mounted as an emulation chip in a set, connected to a debug host, and the set developer uses the software for the mask ROM type B shown in FIG. A case where development is performed will be described with reference to the flowchart of FIG.

  In FIG. 9, a period 901 is an operation until the execution of the user program is started, and is the same operation as the mask ROM microcomputer.

  During a period 902, a debug interrupt is received from the debug host through the debug I / F 110 during execution of the user program. During this period, the invalid address range data of the mask ROM type B passes from the debug host via the debug I / F 110 and the CPU 102 as the type information. Are sent to the access monitoring circuit 803 via the bus controller 802. Since the invalid address range data is written, the access monitoring circuit 803 sets the invalid address range corresponding to the mask ROM type B in the invalid address table unit 805 and monitors the operation of the bus controller 802.

  A period 903 is a case where the write operation is erroneously performed on the address of the control register of the peripheral circuit B 108 because debugging of the user program is not completed. The access monitoring circuit 803 monitors the access, and this write operation is performed by the mask ROM. Since the access is to an invalid address that is not mounted in the product type B, the access monitoring circuit 803 determines that the access is invalid and acts on the bus controller 802 not to execute the write operation. Therefore, this write operation is ignored and no value is set in the control register of the peripheral circuit B108, and the initial state remains unchanged.

  A period 904 is a case where the user program has not been debugged yet, so that the read operation is mistakenly performed at the address 0x00003000 of the built-in SRAM 106. The access monitoring circuit 803 monitors the access. The access monitoring circuit 803 determines that the access is invalid and does not execute the read operation on the bus controller 802 because the access is to an invalid address that is not implemented in the. Therefore, the read operation is not performed on the built-in SRAM 106, and the random value generated by the random number generator 804 is transferred to the CPU 102 as invalid data.

  In the case of accessing a valid address, the access monitoring circuit 803 determines that the access is valid and does not act on the bus controller 802, and the bus controller 802 operates normally.

  By operating as described above, the microcontroller chip 801 can operate as a base product, and when connected to a debug host as an emulation chip, mask information can be obtained by transferring product information by a debug interrupt. The function of ROM type A or B can be substituted.

  If the function of the mask ROM type B is substituted, the write to the invalid address is ignored as in the mask ROM type B, and a random value is returned as invalid data for the read to the invalid address. The developer can know the behavior of the program in the mask ROM type B, and when an invalid read operation is performed, a random value is read from the target address unlike the first and second embodiments. Since it operates, it becomes easy to find a program error, and it is possible to prevent in advance problems when a mask ROM type is applied to a mass production set.

  In the above configuration, invalid address range data is transferred from the debug host as product type information, but it is stored in a flash memory or the like in a non-volatile manner, or a means for holding product type information volatilely on the chip is provided for debugging. The same effect can be obtained even when the product information is set in advance.

  In the above configuration, invalid address range data that differs depending on the product type is transferred to and stored in the invalid address table unit 805. However, it is also possible to transfer the product number information and decode the invalid address range data from the product number information. It is.

  In the above configuration, for simplicity of explanation, one instruction ROM and one SRAM and two peripheral circuits are mounted. However, depending on the configuration or elements each element has one or more, it is not mounted. A configuration is also possible.

  Further, in the above configuration, the read operation to the target address is not performed at the time of invalid access, but the read operation to the target address may be performed and invalid data may be returned to the CPU 102.

  In the above configuration, the write operation is ignored for the invalid access write operation, but the random value generated by the random number generator 804 may be written.

  In the above configuration, the product information is transferred from the debug host after the start of execution of the user program, but the product information is transferred from the debug host before execution of the user program. Good.

  In the above configuration, a debug interrupt is issued from the debug host for transferring the product type information. However, as in the second embodiment, a sequencer may be provided.

(Fourth embodiment)
A fourth embodiment of the present invention will be described with reference to FIGS.

  FIG. 10 shows a microcontroller chip according to a fourth embodiment of the present invention. Like the microcontroller chip 101, the microcontroller chip 1001 is a base product of the series and has a built-in flash memory (FlashROM 103) as an instruction ROM. The microcontroller chip 1001 can be mounted in a final set, and is an emulation for developing a user program. It can also be used as a chip.

  As shown in FIG. 10, the microcontroller chip 1001 of the base type also used as an emulation chip monitors the operation of the CPU 1002 that controls the entire chip by executing instructions and the bus controller 1006, and when there is an invalid access. An access monitoring circuit 1003 that issues an invalid access detection interrupt to the CPU 1002, a bus controller 1006 that is controlled by the CPU 1002 and controls the internal bus 105, and other components (103, 105, 106, 107, 108 similar to the microcontroller chip 101) 110).

  The access monitoring circuit 1003 is set in the invalid address table unit 1004 to which invalid address range data corresponding to the mask ROM type is written via the bus controller 1006, and the target address and invalid address table unit 1004 to be accessed by the bus controller 1006. And an address comparison unit 1005 for comparing the invalid address range.

  The access monitoring circuit 1003 does not monitor the access of the bus controller 1006 when the invalid address range data is not written in the invalid address table unit 1004, does not act on the CPU 1002, and when invalid address range data is written. Monitors the access of the bus controller 1006.

  The access monitoring circuit 1003 monitors the bus controller 1006, and the result of the address comparison unit 1005 indicates that the target address to be accessed by the bus controller 1006 is outside the invalid address range, that is, an access to a valid area. In this case, it is determined that the access is valid and does not act on the CPU 1002, and when the target address to be accessed by the bus controller 1006 is within the invalid address range, this is determined to be invalid access, and the CPU 1002 is invalid accessed. Acts as a detection interrupt.

  Next, the operation of the microcontroller chip 1001 will be described. The case where the user program is written in the flash ROM 103 of the microcontroller chip 1001, is mounted on the final set, and operates on the final set, is the same as that of the microcontroller chip 101.

  As an example of the emulation chip operation of the microcontroller chip 1001, the microcontroller chip 1001 is mounted as an emulation chip in a set, connected to a debug host, and the set developer uses software for the mask ROM type B shown in FIG. A case where development is performed will be described with reference to the flowchart of FIG.

  In FIG. 11, a period 1101 is an operation until the execution of the user program is started, and is the same operation as the mask ROM microcomputer.

  During the period 1102, a debug interrupt is received from the debug host through the debug I / F 110 during execution of the user program. During this period, the invalid address range data of the mask ROM type B is sent from the debug host via the debug I / F 110 and the CPU 1002 as the type information. Are sent to the access monitoring circuit 1003 via the bus controller 1006. Since the invalid address range data is written, the access monitoring circuit 1003 sets the invalid address range corresponding to the mask ROM type B in the invalid address table unit 1004 and monitors the operation of the bus controller 1006.

  The period 1103 is a case where the user program has not been debugged yet and the write operation is erroneously performed on the address of the control register of the peripheral circuit B108. The access monitoring circuit 1003 monitors the access, and this write operation is performed by the mask ROM. Since access is to an invalid address that is not implemented in the product type B, the access monitoring circuit 1003 determines that the access is invalid and acts to interrupt the CPU 1002. Since an interrupt has occurred, the CPU 1002 notifies the debug host of detection of invalid access through the debug I / F 110.

  The period 1104 is a case where the user program has not been debugged and the read operation is erroneously performed at address 0x00003000 of the built-in SRAM 106. The access monitoring circuit 1003 monitors the access, and this read operation is the mask ROM type B. The access monitoring circuit 1003 determines that it is an invalid access, and acts to interrupt the CPU 1002 because it is an access to an invalid address that is not implemented in. Since an interrupt has occurred, the CPU 1002 notifies the debug host of detection of invalid access through the debug I / F 110.

  In the case of accessing a valid address, the access monitoring circuit 1003 determines that the access is valid and does not act on the CPU 1002, and the CPU 1002 and the debug I / F 110 operate normally.

  By operating as described above, the microcontroller chip 1001 can operate as a base product, and when connected to a debug host as an emulation chip, mask information can be obtained by transferring product information by a debug interrupt. The function of ROM type A or B can be substituted.

  When the function of the mask ROM type B is substituted, the write to and read from the invalid address is interrupted to the CPU 1002 in the same manner as the mask ROM type B, so that the detection of invalid access can be notified, and the software of the set The software developer can detect a problem of the program in the mask ROM type B at an early stage, and can prevent a problem when the mask ROM type is applied to the mass production set in advance.

  In the above configuration, invalid address range data is transferred from the debug host as product type information, but it is stored in a flash memory or the like in a non-volatile manner, or a means for holding product type information volatilely on the chip is provided for debugging. The same effect can be obtained even when the product information is set in advance.

  In the above configuration, invalid address range data that differs depending on the product type is transferred and stored in the invalid address table unit 1004. However, it is also possible to transfer the product number information and decode the invalid address range data from the product number information. It is.

  In the above configuration, for simplicity of explanation, one instruction ROM and one SRAM and two peripheral circuits are mounted. However, depending on the configuration or elements each element has one or more, it is not mounted. A configuration is also possible.

  In the above configuration, the CPU 1002 is interrupted when reading to an invalid address. However, in addition to the generation of an interrupt, the read operation to the target address is not performed or the read operation to the target address is performed. It is good.

  In the above configuration, the CPU 1002 is interrupted when writing to an invalid address. However, in addition to the generation of an interrupt, a write operation is performed or the write operation is ignored, or a random number generator is used as in the third embodiment. A random value may be written in advance.

  In the above configuration, the product information is transferred from the debug host after the start of execution of the user program, but the product information is transferred from the debug host before execution of the user program. Good.

In the above configuration, a debug interrupt is issued from the debug host for transferring the product type information. However, as in the second embodiment, a sequencer may be provided.
In the above configuration, the CPU 1002 is interrupted when invalid access is detected, and the detection of invalid access is notified from the CPU 1002 to the debug I / F 110. However, the access monitor circuit 1003 notifies the debug I / F 110 when invalid access is made. It may be configured to notify detection of direct invalid access.

(Fifth embodiment)
A fifth embodiment of the present invention will be described with reference to FIGS.

  FIG. 12 shows a microcontroller chip according to a fifth embodiment of the present invention. Like the microcontroller chip 101, the microcontroller chip 1201 is a series base product, and includes a flash memory (FlashROM 103) as an instruction ROM, which can be mounted in the final set, and is an emulation for developing a user program. It can also be used as a chip.

  As shown in FIG. 12, the microcontroller chip 1201 of the base type that also serves as an emulation chip includes a CPU 1202 that controls the entire chip by executing instructions, an internal control register 1204, and a resource invalidation register 1205. A peripheral circuit A 1203 controlled by setting values in the control register 1204 and the resource invalidation register 1205 via the internal control register 1207 and the resource invalidation register 1208 provided therein, and the control register 1207 and the resource via the internal bus 105. A peripheral circuit C1206 controlled by setting a value in the invalidation register 1208, a bus controller 1209 controlled by the CPU 1202 to control the internal bus 105, and other components similar to those of the microcontroller chip 101 (103,105,106,110) and a.

  The resource invalidation register 1205 of the peripheral circuit A 1203 has an initial value of 0. When the value of the resource invalidation register 1205 is 0, the peripheral circuit A 1203 does not invalidate the resource of the peripheral circuit A 1203 without acting on the control register 1204. However, if a value other than 0 is written to the resource invalidation register 1205 when the debug host is connected, it acts on the control register 1204 according to the value and invalidates some or all of the resources of the peripheral circuit A1203. At the same time, the bus access to the peripheral circuit A 1203 is monitored.

  While monitoring the bus access to the peripheral circuit A 1203, if there is a bus access that enables the resource against the setting of the resource invalidation register 1205 of the peripheral circuit A 1203, it is determined that the access is invalid. This acts to give an invalid access detection interrupt to the CPU 1202.

  The peripheral circuit C1206 is similar to the peripheral circuit A1203.

  FIG. 13 shows the difference in memory size and peripheral circuit between the base type of the microcontroller shown in FIG. 12 and the mask ROM types A and C which are the series development products. The mask ROM types A and C have a built-in mask ROM as an instruction ROM, and are mounted on a final set where mass production is performed.

  As shown in FIG. 13, the base type also serves as an emulation chip, and has a resource invalidation register for each peripheral circuit as compared with the mask ROM type. The mask ROM type A has the same memory size and peripheral functions as the base type, except that it does not have a resource invalidation register. The mask ROM type C is different from the base type in that it does not have a resource invalidation register, but has a difference in memory size and peripheral functions. That is, in the mask ROM type C, the memory size is reduced by half for both ROM and RAM, and a part of the peripheral circuit C is not mounted for peripheral functions.

  The peripheral circuit C is a general-purpose serial in which either the UART or the clock synchronous serial function can be selected by the protocol selection bit of the control register in the base type and the mask ROM type A. It has a configuration. That is, the UART becomes an invalid resource in the peripheral circuit C of the mask ROM type C.

  FIG. 14 shows a control register of the peripheral circuit C mounted on the base type and the mask ROM type A. The control register 1401 includes a protocol selection bit 1402, and the protocol selection bit 1402 selects a clock synchronous serial as an initial value and can be rewritten.

  FIG. 15 shows a control register of the peripheral circuit C mounted on the mask ROM type C. The control register 1501 includes a protocol selection bit 1502, but the protocol selection bit 1502 has a fixed initial value and selects a clock synchronous serial and cannot be rewritten. If there is an access to rewrite the protocol selection bit 1502 in the mask ROM type C, the protocol selection bit 1502 ignores this access.

  FIG. 16 shows the operation of each peripheral circuit C of the base type, the mask ROM type A, and the mask ROM type C.

  As shown in FIG. 16, in the base type and the mask ROM type A, the initial value of the protocol selection bit 1502 is 0 and the clock synchronous serial is selected as the protocol, but the access for rewriting the value of the protocol selection bit 1502 to 1 If there is, the protocol selection bit 1502 is rewritten to 1 to select UART as the protocol.

  As shown in FIG. 16, in the mask ROM type C, the initial value of the protocol selection bit 1502 is 0 and the clock synchronous serial is selected as the protocol. However, there is an access to rewrite the value of the protocol selection bit 1502 to 1. In this case, the protocol selection bit 1502 ignores this access and holds 0 to select the clock synchronous serial as the protocol.

  FIG. 17 shows the operation of the peripheral circuit C1206 when information for each product type is set in the base product chip performing the emulation operation and the operation of the base product, mask ROM product type A or mask ROM product type C is emulated.

  As shown in FIG. 17, when emulating the operation of the base type or the mask ROM type A, it is connected to the debug host, and the same 0 as the initial value is written in the resource invalidation register 1208 of the peripheral circuit C1206. Since the value of the resource invalidation register 1208 is 0, the protocol selection bit 1502 of the peripheral circuit C1206 of the emulation chip can be rewritten, and the protocol corresponding to the value of the protocol selection bit 1502 is selected for the peripheral circuit C1206.

  As shown in FIG. 17, when emulating the operation of the mask ROM type C, the resource invalidation register 1208 of the peripheral circuit C 1206 is rewritten to 1 by connecting to the debug host. Since the value of the resource invalidation register 1208 is 1, the protocol selection bit 1502 of the peripheral circuit C1206 of the emulation chip cannot be rewritten, and the clock synchronization serial protocol corresponding to the value 0 of the protocol selection bit 1502 is selected for the peripheral circuit C1206. Further, when the value of the resource invalidation register 1208 is 1, the protocol selection bit 1502 of the peripheral circuit C1206 of the emulation chip cannot be rewritten. On the other hand, the protocol is selected so that the UART protocol that is not implemented in the mask ROM type C is selected. When there is an access for rewriting the value of the selection bit 1502, the access is ignored and it is determined as an invalid access, and an invalid access detection interrupt is applied to the CPU 1202.

  Next, the operation of the microcontroller chip 1201 will be described. The case where the user program is written in the built-in flash memory of the microcontroller chip 1201, is mounted on the final set, and operates on the final set, is the same as that of the microcontroller chip 101.

  As an example of the emulation chip operation of the microcontroller chip 1201, when the microcontroller chip 1201 is mounted on the set as an emulation chip and connected to the debug host, the set developer is developing software for the mask ROM type C Will be described with reference to FIG.

  In FIG. 18, a period 1801 is an operation until the execution of the user program is started, and is the same operation as the mask ROM microcomputer.

  During a period 1802, a debug interrupt is issued from the debug host through the debug I / F 110 during execution of the user program. During this period, invalid resource data of the mask ROM type C is sent from the debug host via the debug I / F 110 and the CPU 1202 as product type information. And is written to the resource invalidation register 1205 of the peripheral circuit A 1203 and the resource invalidation register 1208 of the peripheral circuit C 1206 via the bus controller 104.

  As shown in FIG. 13, in this ROM mask type C, the peripheral circuit A 1203 has the same function as the peripheral circuit A of the base type and ROM mask type A, so all the resources of the peripheral circuit A 1203 are valid and the resource is invalid. The invalid resource data “0” of the mask ROM type C is written in the generalization register 1205 as the type information. Since the value of the resource invalidation register 1205 of the peripheral circuit A 1203 is “0”, it does not act on the control register 1204, does not monitor bus access to the peripheral circuit A 1203, and does not act on the CPU 1202.

  Further, as shown in FIG. 13, in this ROM mask type C, the peripheral circuit C 1206 is limited compared to the peripheral circuit C of the base type and ROM mask type A, and only the clock synchronous serial function of the peripheral circuit C 1206 is effective. In the invalidation register 1208, invalid resource data “1” of the mask ROM type C is written as type information. Since the value of the resource invalidation register 1208 of the peripheral circuit C 1206 is “1”, it acts on the control register 1207 to monitor the bus access to the peripheral circuit C 1206.

  In period 1803, since the debugging of the user program is incomplete, a write operation is performed on the control register 1207 of the peripheral circuit C1206, and the protocol selection bit 1502 is rewritten in an attempt to erroneously enable UART, which is a limited resource in the mask ROM type C In this case, the resource invalidation register 1208 of the peripheral circuit C1206 monitors the bus access to the peripheral circuit C1206, and this write operation validates UART, which is a resource restricted in the mask ROM type C. Because of the access to be attempted, the resource invalidation register 1208 of the peripheral circuit C 1206 determines this access as invalid access and generates an invalid access detection interrupt to the CPU 1202. Since an invalid access detection interrupt has occurred, the CPU 1202 notifies the debug host through the debug I / F 110 that invalid access has been detected.

  By operating as described above, the microcontroller chip 1201 can operate as a base product, and when connected to a debug host as an emulation chip, mask information can be obtained by transferring product information by a debug interrupt. The operation of the ROM type A or C can be substituted.

  When the operation of the mask ROM type C is performed on behalf, an invalid write access to a resource restricted in the mask ROM type C generates an interrupt to the CPU 1202, so that the detection of the invalid access can be notified. The software developer can detect a problem of the program in the mask ROM type C at an early stage, and can prevent a problem when the mask ROM type is applied to the mass production set in advance.

  In the above configuration, invalid address range data is transferred from the debug host as product type information, but it is stored in a flash memory or the like in a non-volatile manner, or a means for holding product type information volatilely on the chip is provided for debugging. The same effect can be obtained even when the product information is set in advance.

  In the above configuration, for simplicity of explanation, one instruction ROM and one SRAM and two peripheral circuits are mounted. However, depending on the configuration or elements each element has one or more, it is not mounted. A configuration is also possible.

  In the above configuration, the CPU 1202 is interrupted at the time of writing to effectively set the resource limited by the product type setting. However, in addition to the generation of the interrupt, the write operation is performed or the write operation is ignored. As in the third embodiment, a random number generator may be provided and a random value may be written.

  In the above configuration, the product information is transferred from the debug host after the start of execution of the user program, but the product information is transferred from the debug host before execution of the user program. Good.

  In the above configuration, a debug interrupt is issued from the debug host for transferring the product type information. However, as in the second embodiment, a sequencer may be provided.

  In the above-described configuration, the CPU 1202 is interrupted when invalid access is detected, and the invalid access is notified from the CPU 1202 to the debug I / F 110. However, the invalid access is directly notified to the debug I / F 110 when invalid access is performed. It is good.

  Further, in addition to the above configuration, an access monitoring circuit is provided as in the first to fourth embodiments, and when invalid access is monitored and invalid access is detected, the configuration operates as in the first to fourth embodiments. It is good.

  The semiconductor device according to the present invention is useful as an emulation chip or the like for providing a software debugging environment depending on the base product in a series of microcontrollers and microcomputers having variations in built-in memory size and built-in peripheral circuit.

1 is a block diagram of a microcontroller chip according to a first embodiment of the present invention. It is a figure which shows the comparison table of the memory size and peripheral function of the base kind of the microcomputer series of 1st-4th Embodiment, and ROM kind. It is a flowchart which shows the example of operation | movement in case the base kind of 1st Embodiment performs a user program. It is a flowchart which shows the example of operation | movement when the base kind of 1st Embodiment substitutes the function of the mask ROM kind A as an emulation chip. It is a flowchart which shows the example of operation | movement when the base kind of 1st Embodiment substitutes the function of the mask ROM kind B as an emulation chip. It is a block diagram of the microcontroller chip | tip of the 2nd Embodiment of this invention. It is a flowchart which shows the example of operation | movement when the base kind of 2nd Embodiment substitutes the function of the mask ROM kind B as an emulation chip. It is a block diagram of the microcontroller chip | tip of the 3rd Embodiment of this invention. It is a flowchart which shows the example of operation | movement when the base kind of 3rd Embodiment substitutes the function of the mask ROM kind B as an emulation chip. It is a block diagram of the microcontroller chip | tip of the 4th Embodiment of this invention. It is a flowchart which shows the example of operation | movement when the base kind of 4th Embodiment substitutes the function of the mask ROM kind B as an emulation chip. It is a block diagram of the microcontroller chip | tip of the 5th Embodiment of this invention. It is a figure which shows the comparison table of the memory size and peripheral function of the base kind and ROM kind of microcomputer series of 5th Embodiment. It is a block diagram of the control register of the peripheral circuit B of the base type and mask ROM type A of the fifth embodiment. It is a block diagram of the control register of the peripheral circuit B of the mask ROM type C of the fifth embodiment. It is a figure which shows the operation | movement comparison table of the peripheral circuit C of the base kind and ROM kind of microcomputer series of 5th Embodiment. It is a figure which shows the operation | movement comparison table of the peripheral circuit C when the base kind of 5th Embodiment substitutes the function of a base kind and ROM kind as an emulation chip. It is a flowchart which shows the example of operation | movement when the base kind of 5th Embodiment substitutes the function of the mask ROM kind C as an emulation chip.

Explanation of symbols

101: Microcontroller chip 102: CPU
103: FlashROM
104: Bus controller 105: Internal bus 106: SRAM
107: Peripheral circuit A
108: Peripheral circuit B
109: Access monitoring circuit 110: Debug I / F
111: Invalid address table unit 112: Address comparison unit 601: Microcontroller chip 602: Access monitoring circuit 603: Flash ROM
604: User ROM area 605: Product data area 606: Sequencer 607: Debug I / F
608: CPU
609: Invalid address table unit 610: Address comparison unit 801: Microcontroller chip 802: Bus controller 803: Access monitoring circuit 804: Random number generator 805: Invalid address table unit 806: Address comparison unit 1001: Microcontroller chip 1002: CPU
1003: Address monitoring circuit 1004: Invalid address table unit 1005: Address comparison unit 1006: Bus controller 1201: Microcontroller chip 1202: CPU
1203: Peripheral circuit A
1204: Control register 1205: Resource invalidation register 1206: Peripheral circuit C
1207: Control register 1208: Resource invalidation register 1209: Bus controller 1401: General-purpose serial control register 1402: Protocol selection bit 1501: Clock synchronous serial control register 1502: Protocol selection bit

Claims (8)

A semiconductor device of one type of a series product comprising a plurality of types having a central processing unit and a plurality of internal resources and having variations in either or both of the internal resource area and function Because
A debug information input / output device that communicates with an external debug host and a product information storage area for storing product information of other products of the series are provided, and the debug information input / output device and the debug host are connected. 2. A semiconductor device according to claim 1, wherein an operation of the other product is performed on the basis of product information stored in the product information storage area.   When the debug information input / output device and the debug host are connected, the product information is written into the product information storage area by a debug program that is activated by a debug interrupt and executed by the central processing unit. The semiconductor device according to claim 1.   2. The semiconductor device according to claim 1, wherein when the debug information input / output device is connected to the debug host, the product information is written into the product information storage area by a built-in sequencer immediately after startup. The other resource has a limited area of any of the internal resources compared to the one product.
When the debug information input / output device and the debug host are connected, the restricted internal resource is determined based on the product information stored in the product information storage region, and the restricted internal resource region is transferred to the restricted internal resource region. 4. The semiconductor device according to claim 1, wherein when there is a write or read access from the central processing unit, the access is determined to be an invalid access and ignored. The other resource has a limited area of any of the internal resources compared to the one product.
When the debug information input / output device and the debug host are connected, the restricted internal resource is determined based on the kind information stored in the kind information storage area, and the restricted internal resource area is centralized. 4. When there is a write or read access from a processing device, this access is determined to be invalid access, and operation is performed to write or read fixed value invalid data. The semiconductor device described. The other resource has a limited area of any of the internal resources compared to the one product.
When the debug information input / output device and the debug host are connected, the restricted internal resource is determined based on the kind information stored in the kind information storage area, and the restricted internal resource area is centralized. 4. When there is a write or read access from a processing device, this access is judged as an invalid access, and random invalid data is written or read out. Semiconductor device. The other resource has a limited area of any of the internal resources compared to the one product.
When the debug information input / output device and the debug host are connected, the restricted internal resource is determined based on the kind information stored in the kind information storage area, and the restricted internal resource area is centralized. When there is a write or read access from the processing device, this access is determined to be invalid access, and invalid access detection information is transmitted to one or both of the central processing unit and the debug information input / output device. The semiconductor device according to claim 1, wherein the semiconductor device operates. The other resource has a limited area of any of the internal resources compared to the one product.
When the debug information input / output device and the debug host are connected, the restricted internal resource is determined based on the kind information stored in the kind information storage area, and the restricted internal resource area is activated. If there is a write access from the central processing unit, the access is determined as invalid access, and invalid access detection information is sent to one or both of the central processing unit and the debug information input / output device. The semiconductor device according to claim 1, wherein the semiconductor device operates to transmit.

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