JP2006278515A - Method for evaluating semiconductor wafer and process for producing semiconductor wafer - Google Patents

Method for evaluating semiconductor wafer and process for producing semiconductor wafer Download PDF

Info

Publication number
JP2006278515A
JP2006278515A JP2005092557A JP2005092557A JP2006278515A JP 2006278515 A JP2006278515 A JP 2006278515A JP 2005092557 A JP2005092557 A JP 2005092557A JP 2005092557 A JP2005092557 A JP 2005092557A JP 2006278515 A JP2006278515 A JP 2006278515A
Authority
JP
Japan
Prior art keywords
semiconductor wafer
haze value
wafer
light reception
angle light
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2005092557A
Other languages
Japanese (ja)
Other versions
JP4385978B2 (en
Inventor
Miho Iwabuchi
美保 岩渕
Yutaka Kitagawara
豊 北川原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Handotai Co Ltd
Original Assignee
Shin Etsu Handotai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Priority to JP2005092557A priority Critical patent/JP4385978B2/en
Publication of JP2006278515A publication Critical patent/JP2006278515A/en
Application granted granted Critical
Publication of JP4385978B2 publication Critical patent/JP4385978B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for evaluating microroughness of semiconductor wafer surface easily in order to perform polishing and cleaning of a semiconductor wafer effectively during production thereof, and to provide a process for producing a semiconductor wafer by using that evaluation method. <P>SOLUTION: In the method for evaluating a semiconductor wafer, haze value of semiconductor wafer surface is measured previously for vertical irradiation/high angle light reception and/or oblique irradiation/low angle light reception, surface profile of the wafer is measured and its data converted into power spectrum, and then correlation of power spectral density of that power spectrum and the haze value for vertical irradiation/high angle light reception at space wavelength of 1 μm and/or correlation of power spectral density and the haze value for oblique irradiation/low angle light reception at space wavelength of 0.1 μm are determined. A process for producing a semiconductor wafer by evaluating the surface profile of wafer using that method and adjusting the polishing conditions and/or the cleaning conditions depending on the evaluation results is also provided. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体ウエーハの評価方法及び製造方法に関するものであり、より詳しくは半導体ウエーハ表面のマイクロラフネスの評価方法及び前記評価方法を用いた半導体ウエーハの製造方法に関する。   The present invention relates to a semiconductor wafer evaluation method and manufacturing method, and more particularly to a semiconductor wafer surface microroughness evaluation method and a semiconductor wafer manufacturing method using the evaluation method.

近年のデバイスの高集積化、高精度化によりシリコンウエーハへの要求品質はますます高度化しており、特にシリコンウエーハ表面の平坦度や表面粗さを改善することは、デバイスの電気特性を向上するために必要となっている。   The required quality of silicon wafers has become increasingly sophisticated due to the recent high integration and high precision of devices. In particular, improving the flatness and surface roughness of the silicon wafer surface improves the electrical characteristics of the device. It is necessary for.

すなわち、ウエーハ表面におけるマイクロラフネスが、デバイスの電気特性に影響を与えていることが分かってきており、例えば、マイクロラフネスが大きければ酸化膜耐圧は低下し、更にゲート酸化膜下チャンネルではマイクロラフネスが大きくなると電子の散乱が起こり電子の移動度は小さくなること等が知られている。特に、ウエーハ表面における空間波長が0.01〜5μm程度の凹凸であるヘイズについては、デバイスの電気特性の信頼性試験、特に酸化膜の経時絶縁破壊特性(TDDB)に影響を与えることが分かっている。   That is, it has been found that the microroughness on the wafer surface has an influence on the electrical characteristics of the device. For example, if the microroughness is large, the oxide film breakdown voltage decreases, and further, the microroughness is reduced in the channel below the gate oxide film. It is known that when it becomes larger, electron scattering occurs and the electron mobility becomes smaller. In particular, it has been found that haze, which has irregularities with a spatial wavelength of about 0.01 to 5 μm on the wafer surface, affects the reliability test of the electrical characteristics of the device, particularly the time-dependent dielectric breakdown characteristics (TDDB) of the oxide film. Yes.

従って、今後のデバイスの電気特性を向上させるためには、シリコンウエーハのヘイズ等のマイクロラフネスを改善する必要があり、これらの改善方法が開示されている(例えば特許文献1)。   Therefore, in order to improve the electrical characteristics of future devices, it is necessary to improve the microroughness such as haze of the silicon wafer, and these improvement methods have been disclosed (for example, Patent Document 1).

一方、ウエーハ表面における空間波長が数mm〜20mm程度の凹凸であるうねりについても、デバイス作製工程におけるフォトリソグラフィーや素子分離等において問題となる。これに対して、ウエーハ裏面の表面形状を測定し、そこからパワースペクトル密度を求め、その空間波長10mmのパワースペクトル密度を10μm以下とすることが開示されている(特許文献2)。 On the other hand, waviness having irregularities with a spatial wavelength on the wafer surface of several millimeters to 20 mm is also a problem in photolithography, element separation, and the like in the device manufacturing process. On the other hand, it is disclosed that the surface shape of the back surface of the wafer is measured, the power spectral density is obtained therefrom, and the power spectral density at a spatial wavelength of 10 mm is set to 10 μm 3 or less (Patent Document 2).

特許第3536618号公報Japanese Patent No. 3536618 特許第3358549号公報Japanese Patent No. 3358549

本発明の目的は、半導体ウエーハの製造時における研磨や洗浄を効果的に行なうために半導体ウエーハ表面のマイクロラフネスを短時間で簡易的に評価する半導体ウエーハの評価方法及び前記評価方法を用いた半導体ウエーハの製造方法を提供することにある。   SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor wafer evaluation method for easily evaluating the microroughness of a semiconductor wafer surface in a short time in order to effectively perform polishing and cleaning at the time of manufacturing a semiconductor wafer, and a semiconductor using the evaluation method The object is to provide a method for manufacturing a wafer.

上記目的達成のため、本発明は、半導体ウエーハの評価方法であって、少なくとも、予め半導体ウエーハ表面の垂直照射・高角度受光のヘイズ値及び/又は斜角照射・低角度受光のヘイズ値を測定すると共に、該ウエーハの表面形状を測定し、該測定したウエーハの表面形状のデータをパワースペクトルに変換し、該パワースペクトルにおいて、空間波長1μmでのパワースペクトル密度と前記垂直照射・高角度受光ヘイズ値との相関関係及び/又は空間波長0.1μmでのパワースペクトル密度と前記斜角照射・低角度受光ヘイズ値との相関関係を求めておくことを特徴とする半導体ウエーハの評価方法を提供する(請求項1)。   In order to achieve the above object, the present invention is a method for evaluating a semiconductor wafer, and measures at least the haze value of vertical irradiation / high angle light reception and / or the oblique irradiation / low angle light reception of a semiconductor wafer surface in advance. And measuring the surface shape of the wafer, converting the measured surface shape data into a power spectrum, and in the power spectrum, the power spectrum density at a spatial wavelength of 1 μm and the vertical irradiation / high angle light receiving haze. There is provided a semiconductor wafer evaluation method characterized by obtaining a correlation between a value and / or a correlation between a power spectral density at a spatial wavelength of 0.1 μm and the oblique angle irradiation / low angle light receiving haze value. (Claim 1).

このように、予め半導体ウエーハ表面の垂直照射・高角度受光のヘイズ値及び/又は斜角照射・低角度受光のヘイズ値を測定すると共に、該ウエーハの表面形状を測定し、これをパワースペクトルに変換し、該パワースペクトルにおいて、空間波長1μmでのパワースペクトル密度と垂直照射・高角度受光ヘイズ値との相関関係及び/又は空間波長0.1μmでのパワースペクトル密度と斜角照射・低角度受光ヘイズ値との相関関係を求めておけば、特にウエーハの研磨、洗浄条件の影響が現れ易い空間波長におけるパワースペクトル密度と、より簡易的に測定できる前記ヘイズ値との相関関係が明らかとなり、これを研磨や洗浄を効果的に行なうためのウエーハの表面形状の定量的な評価に用いることができる。   In this way, the haze value of vertical irradiation / high angle light reception and / or the oblique angle irradiation / low angle light reception haze value of the semiconductor wafer surface is measured in advance, and the surface shape of the wafer is measured, and this is converted into a power spectrum. In the power spectrum, the correlation between the power spectral density at a spatial wavelength of 1 μm and the vertical irradiation / high angle light receiving haze value and / or the power spectral density at a spatial wavelength of 0.1 μm and oblique irradiation / low angle light reception If the correlation with the haze value is obtained, the correlation between the power spectral density at a spatial wavelength where the influence of wafer polishing and cleaning conditions is likely to appear and the haze value that can be measured more easily becomes clear. Can be used for quantitative evaluation of the surface shape of the wafer for effective polishing and cleaning.

なお、ここで垂直照射・高角度受光ヘイズ値とは、ウエーハ表面に垂直方向から試験光を照射し、ウエーハ表面から約80°の角度の方向に散乱された光を受光器により受光して計測した場合のヘイズ値であり、斜角照射・低角度受光ヘイズ値とは、ウエーハ表面から約45°の角度の方向から試験光を照射し、ウエーハ表面から約45°の角度の方向に散乱された光を受光器により受光して計測した場合のヘイズ値である。   Here, the vertical irradiation / high-angle light receiving haze value is measured by irradiating the wafer surface with test light from the vertical direction and receiving light scattered in the direction of an angle of about 80 ° from the wafer surface with a light receiver. Haze value in the case of oblique angle irradiation / low angle light receiving haze value is a test light irradiated from an angle direction of about 45 ° from the wafer surface and scattered in an angle direction of about 45 ° from the wafer surface. It is a haze value when the received light is received by a light receiver and measured.

この場合、半導体ウエーハ表面の垂直照射・高角度受光のヘイズ値及び/又は斜角照射・低角度受光のヘイズ値を測定し、該ヘイズ値と前記相関関係とを用いて前記空間波長におけるパワースペクトル密度を算出することにより、該半導体ウエーハの表面形状を評価することが好ましい(請求項2)。
このように、半導体ウエーハ表面の垂直照射・高角度受光のヘイズ値及び/又は斜角照射・低角度受光のヘイズ値を測定し、測定したヘイズ値と前記相関関係とを用いて前記空間波長におけるパワースペクトル密度を算出することにより、半導体ウエーハの表面形状を評価すれば、評価の度に表面形状を測定してこれをパワースペクトルに変換し、そこからパワースペクトル密度を求める場合と比較して、短時間で簡易的な表面形状の評価ができる。
In this case, the haze value of vertical irradiation / high-angle light reception and / or haze value of oblique-angle irradiation / low-angle light reception on the semiconductor wafer surface is measured, and the power spectrum at the spatial wavelength is measured using the haze value and the correlation. It is preferable to evaluate the surface shape of the semiconductor wafer by calculating the density (claim 2).
As described above, the haze value of vertical irradiation / high angle light reception and / or the oblique angle irradiation / low angle light reception haze value of the semiconductor wafer surface is measured, and the measured haze value and the correlation are used in the spatial wavelength. By calculating the power spectral density, if the surface shape of the semiconductor wafer is evaluated, the surface shape is measured each time the evaluation is performed, and this is converted into a power spectrum. Simple surface shape evaluation can be performed in a short time.

また、前記ヘイズ値をパーティクルカウンターで測定することができる(請求項3)。
このように、ヘイズ値をパーティクルカウンターで測定することにより、従来の測定装置を用いて容易に測定を行なうことができる。
The haze value can be measured with a particle counter.
Thus, by measuring the haze value with a particle counter, the measurement can be easily performed using a conventional measuring apparatus.

この場合、前記半導体ウエーハの表面形状を、原子間力顕微鏡法、触針法、光干渉法、位相シフト干渉法、光散乱トポグラフィ法のいずれかで測定することができる(請求項4)。
このように、半導体ウエーハの表面形状を、原子間力顕微鏡法、触針法、光干渉法、位相シフト干渉法、光散乱トポグラフィ法のいずれかで測定することにより、従来の測定装置を用いて容易かつ迅速に測定を行なうことができる。
In this case, the surface shape of the semiconductor wafer can be measured by any one of an atomic force microscope method, a stylus method, a light interference method, a phase shift interference method, and a light scattering topography method.
Thus, by measuring the surface shape of a semiconductor wafer by any of atomic force microscopy, stylus method, optical interferometry, phase shift interferometry, or light scattering topography, a conventional measuring device can be used. Measurement can be performed easily and quickly.

また、本発明は、少なくとも、半導体インゴットをスライスして得られたウエーハを研磨した後に洗浄する半導体ウエーハの製造方法であって、上記のいずれかの方法により前記ウエーハの表面形状を評価し、該評価結果に応じて、研磨条件及び/又は洗浄条件を調整することを特徴とする半導体ウエーハの製造方法を提供する(請求項5)。   Further, the present invention is a method for producing a semiconductor wafer, wherein at least a wafer obtained by slicing a semiconductor ingot is polished and then washed, and the surface shape of the wafer is evaluated by any of the above methods, According to the evaluation result, there is provided a method for producing a semiconductor wafer, characterized in that polishing conditions and / or cleaning conditions are adjusted.

このように、上記のいずれかの方法によりウエーハの表面形状を評価し、その評価結果に応じて、研磨条件及び/又は洗浄条件を調整すれば、特にウエーハの研磨、洗浄条件の影響が現れ易い空間波長と相関関係のあるヘイズ値に応じて、ウエーハ表面のマイクロラフネスを改善するために最適な研磨条件及び/又は洗浄条件に調整して、効果的に研磨及び/又は洗浄を行なって高品質の半導体ウエーハを製造することが可能となる。   As described above, if the surface shape of the wafer is evaluated by any of the above methods, and the polishing conditions and / or the cleaning conditions are adjusted according to the evaluation results, the influence of the polishing and cleaning conditions of the wafer is particularly likely to appear. High quality by effectively polishing and / or cleaning by adjusting to optimum polishing conditions and / or cleaning conditions to improve the microroughness of the wafer surface according to the haze value correlated with the spatial wavelength This makes it possible to manufacture a semiconductor wafer.

この場合、垂直照射・高角度受光のヘイズの評価結果に応じて前記研磨条件を調整し及び/又は斜角照射・低角度受光のヘイズの評価結果に応じて前記洗浄条件を調整することが好ましい(請求項6)。
このように、垂直照射・高角度受光のヘイズの評価結果に応じて研磨条件を調整し及び/又は斜角照射・低角度受光のヘイズの評価結果に応じて洗浄条件を調整すれば、空間波長1μm及び/又は空間波長0.1μmにおけるパワースペクトル密度を効果的に減少させることができ、ウエーハ表面のマイクロラフネスを効果的に改善することが可能となる。
In this case, it is preferable to adjust the polishing conditions according to the evaluation result of haze of vertical irradiation / high angle light reception and / or adjust the cleaning condition according to the evaluation result of haze of oblique angle irradiation / low angle light reception. (Claim 6).
As described above, if the polishing conditions are adjusted according to the evaluation result of haze of vertical irradiation / high angle light reception and / or the cleaning conditions are adjusted according to the evaluation result of haze of oblique angle irradiation / low angle light reception, the spatial wavelength The power spectral density at 1 μm and / or the spatial wavelength of 0.1 μm can be effectively reduced, and the microroughness of the wafer surface can be effectively improved.

また、少なくとも垂直照射・高角度受光のヘイズ値が10ppb以下及び斜角照射・低角度受光のヘイズ値が2ppb以下になるように研磨条件及び洗浄条件の調整を行なうことが好ましい(請求項7)。
このように、少なくとも垂直照射・高角度受光のヘイズ値が10ppb以下及び斜角照射・低角度受光のヘイズ値が2ppb以下になるように研磨条件及び洗浄条件の調整を行なえば、ウエーハ表面のマイクロラフネスが十分に小さくなり、近年のデバイスの高集積化、高精度化により要求される電気特性を達成するのに十分なマイクロラフネスの小さい表面を有する半導体ウエーハを製造することが可能となる。
Further, it is preferable to adjust the polishing conditions and the cleaning conditions so that at least the haze value of vertical irradiation / high angle light reception is 10 ppb or less and the haze value of oblique irradiation / low angle light reception is 2 ppb or less. .
Thus, if the polishing conditions and the cleaning conditions are adjusted so that at least the haze value for vertical irradiation / high-angle light reception is 10 ppb or less and the haze value for oblique irradiation / low-angle light reception is 2 ppb or less, the micro- The roughness becomes sufficiently small, and it becomes possible to manufacture a semiconductor wafer having a surface with a small microroughness sufficient to achieve electrical characteristics required by high integration and high precision of recent devices.

本発明に従い、予め半導体ウエーハ表面の垂直照射・高角度受光のヘイズ値及び/又は斜角照射・低角度受光のヘイズ値を測定すると共に、該ウエーハの表面形状を測定し、これをパワースペクトルに変換し、該パワースペクトルにおいて、空間波長1μmでのパワースペクトル密度と前記垂直照射・高角度受光ヘイズ値との相関関係及び/又は空間波長0.1μmでのパワースペクトル密度と前記斜角照射・低角度受光ヘイズ値との相関関係を求めておけば、特にウエーハの研磨、洗浄条件の影響が現れ易い空間波長におけるパワースペクトル密度と、より簡易的に測定できる前記ヘイズ値との相関関係が明らかとなり、これを研磨や洗浄を効果的に行なうためのウエーハの表面形状の定量的な評価に用いることができる。   According to the present invention, the haze value of vertical irradiation / high angle light reception and / or the oblique angle irradiation / low angle light reception haze value of the semiconductor wafer surface is measured in advance, and the surface shape of the wafer is measured, and this is converted into a power spectrum. In the power spectrum, the correlation between the power spectral density at a spatial wavelength of 1 μm and the vertical irradiation / high angle light-receiving haze value and / or the power spectral density at a spatial wavelength of 0.1 μm and the oblique irradiation / low If the correlation with the angle light reception haze value is obtained, the correlation between the power spectral density at a spatial wavelength that is particularly susceptible to wafer polishing and cleaning conditions and the haze value that can be measured more easily becomes clear. This can be used for quantitative evaluation of the surface shape of the wafer for effective polishing and cleaning.

本発明者らは、半導体ウエーハの製造において、研磨条件の影響が現れ易い空間波長1μmでのパワースペクトル密度と垂直照射・高角度受光ヘイズ値とに相関関係があること、及び洗浄条件の影響が現れ易い空間波長0.1μmでのパワースペクトル密度と斜角照射・低角度受光ヘイズ値とに相関関係があることを見出した。そして、従来ウエーハ表面のパワースペクトルを求めるには、ウエーハの表面形状を測定し、これをパワースペクトルに変換しなければならなかったが、表面形状の測定には時間が掛かるという問題点があることに鑑み、予めより簡易に測定できるヘイズ値についても測定し、これと上記所定の空間波長におけるパワースペクトル密度との相関関係を求めておくことに想到した。そうすれば、ウエーハの評価の度に表面形状を測定するのではなく、ヘイズ値のみを測定して、このヘイズ値から前記相関関係を用いて所定の空間波長でのパワースペクトル密度を算出すれば、ウエーハ表面のマイクロラフネスの評価が短時間で簡易的に行なえることに想到し、本発明を完成させた。   In the manufacture of semiconductor wafers, the inventors have a correlation between the power spectral density at a spatial wavelength of 1 μm and the vertical irradiation / high-angle light-receiving haze value, which are easily affected by polishing conditions, and the influence of cleaning conditions. It has been found that there is a correlation between the power spectral density at an easily appearing spatial wavelength of 0.1 μm and the oblique angle irradiation / low angle light receiving haze value. In order to obtain the power spectrum of the wafer surface in the past, the surface shape of the wafer had to be measured and converted to a power spectrum, but there was a problem that it took time to measure the surface shape. In view of the above, it has been conceived that a haze value that can be more easily measured in advance is also measured, and a correlation between the haze value and the power spectral density at the predetermined spatial wavelength is obtained. Then, instead of measuring the surface shape each time the wafer is evaluated, only the haze value is measured, and the power spectral density at a predetermined spatial wavelength is calculated from the haze value using the correlation. The present invention has been completed by conceiving that the microroughness of the wafer surface can be easily evaluated in a short time.

以下では、本発明の実施の形態について図面を用いて説明するが、本発明はこれに限定されるものではない。   Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited thereto.

図1は、本発明に係る半導体ウエーハの評価方法の一例を示す工程図である。
まず、表面形状のパワースペクトルとヘイズ値との相関関係を求めるための半導体ウエーハを用意する(工程A)。
この半導体ウエーハは、例えばCZ法やFZ法で育成された、シリコンや他の化合物半導体等の半導体インゴットをスライスし、従来法により面取り、ラッピング、エッチング、研磨、洗浄等の工程を適宜行なって得られたものであるが、特に限定はされない。
FIG. 1 is a process diagram showing an example of a semiconductor wafer evaluation method according to the present invention.
First, a semiconductor wafer for obtaining the correlation between the power spectrum of the surface shape and the haze value is prepared (step A).
This semiconductor wafer is obtained by, for example, slicing a semiconductor ingot such as silicon or another compound semiconductor grown by the CZ method or the FZ method, and appropriately performing steps such as chamfering, lapping, etching, polishing, and cleaning by a conventional method. However, there is no particular limitation.

なお、従来の研磨工程では、エッチング工程等の後のウエーハ表面の平坦度を上げるために行う一次研磨(粗研磨)と、ヘイズを低減して鏡面を得ると共に、粗研磨で発生したスクラッチを除去するための仕上げ研磨とを行なうことができる。粗研磨においては、研磨布としてポリエステルフェルト(組織はランダムな構造)にポリウレタンを含侵させたアスカーC強度で80程度の比較的硬質なものを用い、研磨剤としてアルカリベースの水溶液にコロイダルシリカを含有したものを用いることができる。一方仕上げ研磨においては、研磨布として軟質な発泡ウレタンよりなるスエード調の人工皮革からなるものを用い、研磨剤としてアルカリベースの水溶液にコロイダルシリカを含有したものを用いることができる。   In the conventional polishing process, primary polishing (rough polishing) performed to increase the flatness of the wafer surface after the etching process, etc., and a mirror surface is obtained by reducing haze, and scratches generated by the rough polishing are removed. And finish polishing for the purpose. In rough polishing, a relatively hard material with an Asker C strength of about 80 in which polyurethane is impregnated with polyester felt (a random structure) is used as an abrasive cloth, and colloidal silica is used as an abrasive in an alkali-based aqueous solution. What was contained can be used. On the other hand, in the finish polishing, a polishing cloth made of a suede-like artificial leather made of soft foamed urethane can be used, and an alkali-based aqueous solution containing colloidal silica can be used as an abrasive.

また、洗浄工程では、従来の薬品によるウエーハ表面の異物除去、純水によるリンスの組み合わせからなるRCA洗浄等の洗浄工程を用いることができる。例えばRCA洗浄の代表的な工程手順は次のように行なわれる。すなわち、1)SC−1洗浄(アンモニア:過酸化水素水:水=1:1:5〜7)、2)純水リンス、3)フッ酸洗浄、4)、純水リンス、5)SC−2洗浄(塩酸:過酸化水素水:水=1:1〜2:6〜8)、6)純水リンス、7)スピンドライ、である。純水リンス工程は複数回繰り返す場合もある。   Further, in the cleaning process, a conventional cleaning process such as RCA cleaning, which is a combination of removing foreign substances on the wafer surface with chemicals and rinsing with pure water, can be used. For example, a typical process procedure for RCA cleaning is performed as follows. That is, 1) SC-1 cleaning (ammonia: hydrogen peroxide water: water = 1: 1: 5-7), 2) pure water rinse, 3) hydrofluoric acid cleaning, 4) pure water rinse, 5) SC- 2 cleaning (hydrochloric acid: hydrogen peroxide water: water = 1: 1 to 2: 6 to 8), 6) pure water rinse, and 7) spin dry. The pure water rinsing process may be repeated multiple times.

次に、このように用意した半導体ウエーハ表面の垂直照射・高角度受光のヘイズ値及び/又は斜角照射・低角度受光のヘイズ値を測定する(工程B)。
このときの測定方法、測定装置については、垂直照射・高角度受光のヘイズ値及び/又は斜角照射・低角度受光のヘイズ値を測定できるものであれば特に限定されないが、測定装置としてパーティクルカウンターを用いれば、従来の測定装置により容易にヘイズ値の測定ができる。このようなパーティクルカウンターとしては、KLA−Tencor社製のSP−1が挙げられ、垂直照射・高角度受光のヘイズ値はこの装置に備えられたDNN(Dark−field Narrow Normal)モードで測定でき、斜角照射・低角度受光のヘイズ値はこの装置に備えられたDWO(Dark−field Wide Oblique)モードで測定できる。
以下、垂直照射・高角度受光のヘイズ値をDNN値、斜角照射・低角度受光のヘイズ値をDWO値と記載する場合がある。
Next, the haze value of vertical irradiation / high-angle light reception and / or haze value of oblique-angle irradiation / low-angle light reception on the surface of the semiconductor wafer thus prepared is measured (step B).
The measuring method and measuring device at this time are not particularly limited as long as they can measure the haze value of vertical irradiation / high angle light reception and / or the haze value of oblique irradiation / low angle light reception. Can be used to easily measure the haze value with a conventional measuring apparatus. Examples of such a particle counter include SP-1 manufactured by KLA-Tencor, and the haze value of vertical irradiation and high-angle light reception can be measured in a DNN (Dark-field Narrow Normal) mode provided in this apparatus. Haze values for oblique angle irradiation and low angle light reception can be measured in a DWO (Dark-Field Wide Oblique) mode provided in this apparatus.
Hereinafter, the haze value for vertical irradiation / high angle light reception may be referred to as DNN value, and the haze value for oblique irradiation / low angle light reception may be described as DWO value.

次に、用意した半導体ウエーハの表面形状を測定する(工程C)。
この表面形状の測定方法は特に限定されないが、原子間力顕微鏡法、触針法、光干渉法、位相シフト干渉法、光散乱トポグラフィ法のいずれかで測定することができる。原子間力顕微鏡法で測定する場合には、例えば日立建機ファインテック社製の原子間力顕微鏡(AFM)を用いることができる。またその他の方法であっても、表面形状を測定できればよく、従来の測定装置を用いて容易に測定を行なうことができる。測定エリアとしては、例えば1μm×1μmとできるが、特に限定はされない。
Next, the surface shape of the prepared semiconductor wafer is measured (step C).
The method for measuring the surface shape is not particularly limited, and can be measured by any of atomic force microscopy, stylus method, light interferometry, phase shift interferometry, and light scattering topography. For measurement by atomic force microscopy, for example, an atomic force microscope (AFM) manufactured by Hitachi Construction Machinery Finetech Co., Ltd. can be used. In addition, other methods may be used as long as the surface shape can be measured, and the measurement can be easily performed using a conventional measuring apparatus. The measurement area can be, for example, 1 μm × 1 μm, but is not particularly limited.

次に、このように測定した表面形状をパワースペクトルに変換する(工程D)。
この場合、例えば測定した表面形状のデータを、イメージメトロロジ社製のソフトウェア「SPIP」によりフーリエ変換を用いて処理し、この処理により出力されたデータに2πd/N(Nはデータ数、dはサンプリング間隔)を掛けることにより、パワースペクトルに変換することができる。データ数は例えば100〜1000、サンプリング間隔は例えば0.01μmとできるが、特に限定はされない。
Next, the surface shape measured in this way is converted into a power spectrum (step D).
In this case, for example, the measured surface shape data is processed using Fourier transform by software “SPIP” manufactured by Image Metrology Co., and 2πd / N (N is the number of data, d is the number of data) By multiplying the sampling interval, it can be converted into a power spectrum. The number of data can be, for example, 100 to 1000, and the sampling interval can be, for example, 0.01 μm, but is not particularly limited.

なお、工程Bのヘイズ値を測定する工程と、工程C〜Dの表面形状を測定し、これをパワースペクトルに変換する工程は、いずれを先に行なってもよい。また、次工程のために、ヘイズ値及びパワースペクトルのデータは、研磨条件や洗浄条件を変えて測定したものを複数用意する。このとき、研磨条件や洗浄条件を変えて測定を行なうために、一つのウエーハだけを用いてもよいし、複数のウエーハを用いてもよい。   In addition, you may perform any of the process of measuring the haze value of the process B, and the process of measuring the surface shape of processes C-D and converting this into a power spectrum. For the next step, a plurality of haze values and power spectrum data measured by changing polishing conditions and cleaning conditions are prepared. At this time, only one wafer or a plurality of wafers may be used in order to perform measurement while changing the polishing conditions and the cleaning conditions.

次に、このように変換したパワースペクトルにおいて、空間波長1μmでのパワースペクトル密度と垂直照射・高角度受光ヘイズ値(DNN値)との相関関係及び/又は空間波長0.1μmでのパワースペクトル密度と斜角照射・低角度受光ヘイズ値(DWO値)との相関関係を求める(工程E)。
例えば、研磨条件や洗浄条件を変えて測定して得た空間波長1μmでのパワースペクトル密度とDNN値とのデータの組を最小二乗法により一次関数で近似するなどして、これらの相関関数を求める。空間波長0.1μmでのパワースペクトル密度とDWO値との相関関数も同様にして求める。本発明者らが見出したように、これらの値は相関関係を有するので、精度の高い相関関数が得られる。
Next, in the power spectrum thus converted, the correlation between the power spectral density at a spatial wavelength of 1 μm and the vertical irradiation / high-angle received haze value (DNN value) and / or the power spectral density at a spatial wavelength of 0.1 μm. And the oblique angle irradiation / low angle light receiving haze value (DWO value) is obtained (step E).
For example, the correlation function is obtained by approximating a data set of power spectral density and DNN value at a spatial wavelength of 1 μm obtained by changing polishing conditions and cleaning conditions by a linear function using the least square method. Ask. The correlation function between the power spectral density at a spatial wavelength of 0.1 μm and the DWO value is obtained in the same manner. As the present inventors have found, since these values have a correlation, a highly accurate correlation function can be obtained.

そして、工程Aと同様にして表面形状を評価するための半導体ウエーハを用意し(工程F)、ウエーハ表面のDNN値及び/又はDWO値を測定し、これらのヘイズ値と、工程Eで求めた相関関係とを用いて空間波長1μm及び/又は0.1μmでのパワースペクトル密度を算出することにより、半導体ウエーハの表面形状を評価する(工程G)。
パワースペクトルにおいてこれらの空間波長の近傍は、特にウエーハの製造工程における研磨、洗浄条件の影響が現れ易い波長であるから、ヘイズ値との相関関係からこれらの空間波長でのパワースペクトル密度を求めれば、研磨や洗浄を効果的に行なうための、半導体ウエーハの表面のマイクロラフネスの定量的な評価が可能となる。
Then, a semiconductor wafer for evaluating the surface shape was prepared in the same manner as in Step A (Step F), the DNN value and / or DWO value of the wafer surface was measured, and these haze values were obtained in Step E. The surface shape of the semiconductor wafer is evaluated by calculating the power spectral density at a spatial wavelength of 1 μm and / or 0.1 μm using the correlation (Step G).
Since the vicinity of these spatial wavelengths in the power spectrum is a wavelength that is particularly susceptible to polishing and cleaning conditions in the wafer manufacturing process, if the power spectral density at these spatial wavelengths is determined from the correlation with the haze value, Therefore, it is possible to quantitatively evaluate the microroughness of the surface of the semiconductor wafer for effective polishing and cleaning.

すなわち、従来のマイクロラフネスを表す平均粗さ(Ra)等の一般的なパラメータでは、マイクロラフネスの高さの情報しか含まれないので、表面状態が異なるウエーハであっても、それがパラメータに現れにくかった。一方、例えば従来のパーティクルカウンター等でヘイズ値を測る方法では、同一のウエーハを測定した場合でも、測定器毎に測定値の差が大きくなる場合があり、相対的評価しかできず定量化が難しかった。しかし本発明に係る評価方法であれば、定量化が可能なパワースペクトル密度との相関関係に基づいてヘイズ値を評価に用いるので、上記の定量化が難しいという問題も解消できる。そして、このように一度相関関係を求めておけば、評価の度に表面形状を測定してパワースペクトルを求める必要がなく、ヘイズ値の測定だけで所定の空間波長におけるパワースペクトル密度を求めることができるので、短時間で簡易的にウエーハの評価ができる。   In other words, conventional parameters such as average roughness (Ra) representing microroughness only include information on the height of microroughness, so even if the wafer has a different surface state, it appears in the parameter. It was difficult. On the other hand, for example, in the conventional method of measuring the haze value with a particle counter or the like, even when the same wafer is measured, the difference in the measured value may be large for each measuring instrument, and only a relative evaluation can be performed, making it difficult to quantify. It was. However, with the evaluation method according to the present invention, the haze value is used for evaluation based on the correlation with the quantifiable power spectral density, so that the problem that the above quantification is difficult can be solved. Once the correlation is obtained in this way, it is not necessary to obtain the power spectrum by measuring the surface shape for each evaluation, and the power spectrum density at a predetermined spatial wavelength can be obtained only by measuring the haze value. Therefore, the wafer can be easily evaluated in a short time.

次に、本発明に係る半導体ウエーハの製造方法について説明する。本発明に係る半導体ウエーハの製造方法は、少なくとも、半導体インゴットをスライスして得られたウエーハを研磨した後に洗浄する半導体ウエーハの製造方法であって、上記のいずれかの方法によりウエーハの表面形状を評価し、該評価結果に応じて、研磨条件及び/又は洗浄条件を調整することを特徴とするものである。   Next, a method for manufacturing a semiconductor wafer according to the present invention will be described. A method for producing a semiconductor wafer according to the present invention is a method for producing a semiconductor wafer, wherein at least a wafer obtained by slicing a semiconductor ingot is polished and then cleaned, and the surface shape of the wafer is formed by any of the above methods. Evaluation is performed, and polishing conditions and / or cleaning conditions are adjusted according to the evaluation results.

すなわち、上記のいずれかの方法によりウエーハ表面の表面形状を評価すれば、特に研磨、洗浄条件の影響が現れ易い所定の空間波長におけるパワースペクトル密度と相関関係があるDNN値、DWO値により定量的に評価を行なうことができるので、この評価結果に応じて、研磨条件及び/又は洗浄条件を調整すれば、ウエーハ表面のマイクロラフネスを改善するために最適な研磨条件及び/又は洗浄条件で半導体ウエーハを製造できる。   That is, if the surface shape of the wafer surface is evaluated by any one of the methods described above, it is quantitatively determined based on the DNN value and DWO value that have a correlation with the power spectral density at a predetermined spatial wavelength that is particularly susceptible to polishing and cleaning conditions. Therefore, if the polishing conditions and / or the cleaning conditions are adjusted according to the evaluation results, the semiconductor wafer can be used under the optimum polishing conditions and / or cleaning conditions in order to improve the microroughness of the wafer surface. Can be manufactured.

特に、垂直照射・高角度受光のヘイズの評価結果に応じて研磨条件を調整し、斜角照射・低角度受光のヘイズの評価結果に応じて洗浄条件を調整することが好ましい。研磨条件の影響は特にDNN値と相関関係のある空間波長1μmでのパワースペクトル密度に現れ易く、また洗浄条件の影響は特にDWO値と相関関係のある空間波長0.1μmでのパワースペクトル密度に現れ易いからである。従って、各ヘイズの評価結果に応じて研磨、洗浄条件を調整すれば、各空間波長におけるパワースペクトル密度を効果的に減少させることができ、ウエーハ表面のマイクロラフネスを効果的に改善することが可能となる。   In particular, it is preferable to adjust the polishing conditions according to the evaluation result of haze for vertical irradiation and high angle light reception, and to adjust the cleaning condition according to the evaluation result of haze for oblique angle irradiation and low angle light reception. The influence of polishing conditions is particularly likely to appear in the power spectral density at a spatial wavelength of 1 μm, which is correlated with the DNN value, and the influence of cleaning conditions is particularly dependent on the power spectral density at a spatial wavelength of 0.1 μm, which is correlated with the DWO value. It is easy to appear. Therefore, if the polishing and cleaning conditions are adjusted according to the evaluation results of each haze, the power spectral density at each spatial wavelength can be effectively reduced, and the microroughness of the wafer surface can be effectively improved. It becomes.

研磨条件の調整としては、例えば研磨布の表面粗さの調整や、研磨剤のpHの調整等が挙げられる。また、洗浄条件の調整としては、例えばRCA洗浄から2流体洗浄への変更、洗浄液の濃度や種類の変更等が挙げられる。   Examples of the adjustment of the polishing conditions include adjustment of the surface roughness of the polishing cloth and adjustment of the pH of the abrasive. Examples of the adjustment of the cleaning conditions include a change from RCA cleaning to two-fluid cleaning, a change in the concentration and type of cleaning liquid, and the like.

2流体洗浄とは、2種以上の流体を混合して、その混合流体をウエーハ表面に噴射して不純物の除去を行なうものであり、2流体洗浄によってヘイズを減少させることができる。例えば二酸化炭素が添加された超純水と窒素ガスとを混合し、この混合流体をウエーハ表面に噴射することによって、2流体洗浄を行なうことができる。このように二酸化炭素が添加された超純水を洗浄液として使用すれば、半導体ウエーハの表面と洗浄液との摩擦により発生する静電気を抑制することができる。また、気体として用いるガスとしては不活性ガスである窒素ガスが好適であるが、その他、空気やアルゴンガス等も用いることができる。また、洗浄液として超純水の代わりにアンモニア水と過酸化水素水と水との混合水溶液を用いれば、エッチング作用のある洗浄を行なうことができる。   In the two-fluid cleaning, two or more kinds of fluids are mixed, and the mixed fluid is jetted onto the wafer surface to remove impurities, and haze can be reduced by the two-fluid cleaning. For example, two-fluid cleaning can be performed by mixing ultrapure water to which carbon dioxide has been added and nitrogen gas and injecting this mixed fluid onto the wafer surface. If the ultrapure water to which carbon dioxide is added is used as a cleaning liquid, static electricity generated by friction between the surface of the semiconductor wafer and the cleaning liquid can be suppressed. Further, as the gas used as the gas, nitrogen gas which is an inert gas is suitable, but air, argon gas or the like can also be used. If a mixed aqueous solution of ammonia water, hydrogen peroxide water and water is used as the cleaning liquid instead of ultrapure water, cleaning with an etching action can be performed.

また、少なくとも垂直照射・高角度受光のヘイズ値が10ppb以下及び斜角照射・低角度受光のヘイズ値が2ppb以下になるように研磨条件及び洗浄条件の調整を行なえば、近年のデバイスの高集積化、高精度化により要求される電気特性を達成するのに十分なマイクロラフネスの小さい表面を有する半導体ウエーハにできる。このような低いヘイズ値は、例えば前述の2流体洗浄を行なうことにより達成できるが、これを達成する方法については特に限定はされない。   Also, if the polishing conditions and the cleaning conditions are adjusted so that at least the haze value for vertical irradiation / high angle light reception is 10 ppb or less and the haze value for oblique irradiation / low angle light reception is 2 ppb or less, high integration of recent devices Thus, a semiconductor wafer having a surface with a small microroughness sufficient to achieve the required electrical characteristics can be achieved. Such a low haze value can be achieved, for example, by performing the above-described two-fluid cleaning, but the method for achieving this is not particularly limited.

以下に本発明の実施例をあげてさらに具体的に説明するが、本発明はこれらに限定されるものではない。
(実験1)
CZ法で育成したシリコン単結晶インゴットをスライスし、従来法により面取り、ラッピング、エッチング、研磨、洗浄を行なって、直径300mmのシリコンウエーハを作製した。このときの研磨条件は従来の粗研磨、仕上げ研磨によるものであり、洗浄条件も従来のRCA洗浄によるものである。次に、このシリコンウエーハ表面のDNN値、DWO値を、パーティクルカウンターであるKLA−Tencor社製のSP−1のDNNモード、DWOモードで測定した。このとき、DNN値は約50ppb、DWO値は約12ppbであった。次に、その表面形状を、測定エリア1μm×1μm、高さレンジを1nmとして、日立建機ファインテック社製のAFMで測定し、測定した表面形状のデータを、イメージメトロロジ社製のソフトウェア「SPIP」によりフーリエ変換を用いて処理し、処理により出力されたデータに2πd/N(Nはデータ数、dはサンプリング間隔)を掛けることにより、パワースペクトルに変換した。なおデータ数は100個、サンプリング間隔は0.01μmとした。このようにして得たパワースペクトルAを図2に示す。このとき、空間波長1μmでのパワースペクトル密度は約2.0×10−3nmであり、空間波長0.1μmでのパワースペクトル密度は約2.0×10−4nmであった。
Examples of the present invention will be described in more detail below, but the present invention is not limited thereto.
(Experiment 1)
A silicon single crystal ingot grown by the CZ method was sliced and chamfered, lapped, etched, polished, and washed by a conventional method to produce a silicon wafer having a diameter of 300 mm. The polishing conditions at this time are based on conventional rough polishing and finish polishing, and the cleaning conditions are also based on conventional RCA cleaning. Next, the DNN value and DWO value of the silicon wafer surface were measured in the DNN mode and DWO mode of SP-1 manufactured by KLA-Tencor, which is a particle counter. At this time, the DNN value was about 50 ppb, and the DWO value was about 12 ppb. Next, the surface shape was measured with an AFM manufactured by Hitachi Construction Machinery Finetech Co., Ltd. with a measurement area of 1 μm × 1 μm and a height range of 1 nm. Processing was performed using Fourier transform by “SPIP”, and the data output by the processing was converted to a power spectrum by multiplying by 2πd / N (N is the number of data and d is a sampling interval). The number of data was 100, and the sampling interval was 0.01 μm. The power spectrum A thus obtained is shown in FIG. At this time, the power spectral density at a spatial wavelength of 1 μm was about 2.0 × 10 −3 nm 3 , and the power spectral density at a spatial wavelength of 0.1 μm was about 2.0 × 10 −4 nm 3 .

(実験2)
次に、仕上げ研磨において研磨布の表面粗さを小さくし、研磨剤のpHを低くするように調整した以外は実験1と同様にシリコンウエーハを作製し、ヘイズ値をパーティクルカウンターにより測定したところ、DNN値は約15ppbに改善され、DWO値は約10ppbに改善された。次に、その表面形状をAFMで測定し、この測定データをパワースペクトルに変換した。このようにして得たパワースペクトルBを図2に示す。このとき、空間波長1μmでのパワースペクトル密度は約1.5×10−3nmに大幅に改善され、空間波長0.1μmでのパワースペクトル密度は約1.5×10−4nmに改善された。
(Experiment 2)
Next, a silicon wafer was prepared in the same manner as in Experiment 1 except that the surface roughness of the polishing cloth was reduced in the final polishing and the pH of the abrasive was adjusted, and the haze value was measured with a particle counter. The DNN value was improved to about 15 ppb and the DWO value was improved to about 10 ppb. Next, the surface shape was measured by AFM, and this measurement data was converted into a power spectrum. The power spectrum B thus obtained is shown in FIG. At this time, the power spectral density at a spatial wavelength of 1 μm is greatly improved to about 1.5 × 10 −3 nm 3 , and the power spectral density at a spatial wavelength of 0.1 μm is about 1.5 × 10 −4 nm 3 . Improved.

(実験3)
次に、実験2と同様に仕上げ研磨において研磨布の表面粗さを小さくし、研磨剤のpHを低くするように調整するとともに、さらに洗浄工程をRCA洗浄から2流体洗浄に変更した以外は実験1と同様にシリコンウエーハを作製した。なお、このときの2流体洗浄は、二酸化炭素が添加された超純水と、窒素ガスを混合し、この混合流体をウエーハ表面に噴射するものとした。このシリコンウエーハのヘイズ値をパーティクルカウンターにより測定したところ、DNN値は約7ppbに改善され、DWO値は約2ppbに大幅に改善された。次に、その表面形状をAFMで測定し、この測定データをパワースペクトルに変換した。このようにして得たパワースペクトルCを図2に示す。このとき、空間波長1μmでのパワースペクトル密度は約1.3×10−3nmに改善され、空間波長0.1μmでのパワースペクトル密度は約4.0×10−5nmと大幅に改善された。
(Experiment 3)
Next, in the same manner as in Experiment 2, the surface roughness of the polishing cloth was reduced in final polishing, and the pH of the abrasive was adjusted to be low, and the experiment was performed except that the cleaning process was changed from RCA cleaning to two-fluid cleaning. A silicon wafer was produced in the same manner as in Example 1. In the two-fluid cleaning at this time, ultrapure water to which carbon dioxide was added and nitrogen gas were mixed, and this mixed fluid was jetted onto the wafer surface. When the haze value of this silicon wafer was measured with a particle counter, the DNN value was improved to about 7 ppb and the DWO value was greatly improved to about 2 ppb. Next, the surface shape was measured by AFM, and this measurement data was converted into a power spectrum. The power spectrum C thus obtained is shown in FIG. At this time, the power spectral density at a spatial wavelength of 1 μm is improved to about 1.3 × 10 −3 nm 3 , and the power spectral density at a spatial wavelength of 0.1 μm is significantly about 4.0 × 10 −5 nm 3. Improved.

(相関係数の算出)
実験1〜実験3の結果に基づいて、対応するヘイズ値とパワースペクトル密度とをプロットしたグラフを作成した。このグラフを図3に示す。図3(a)は空間波長1μmでのパワースペクトル密度とDNN値の相関を示すグラフであり、図3(b)は空間波長0.1μmでのパワースペクトル密度とDWO値の相関を示すグラフである。このように、各空間波長でのパワースペクトル密度とヘイズ値は相関関係を有していた。このデータを最小二乗法を用いて一次関数で近似することにより、空間波長1μmでのパワースペクトル密度をX(nm)、空間波長0.1μmでのパワースペクトル密度をX(nm)とする場合に、X=2×10−5DNN+1.2×10−3、X=2×10−5DWO+7×10−6となる相関関数が求められた。
(Calculation of correlation coefficient)
Based on the results of Experiment 1 to Experiment 3, a graph plotting the corresponding haze value and power spectral density was created. This graph is shown in FIG. 3A is a graph showing the correlation between the power spectral density at a spatial wavelength of 1 μm and the DNN value, and FIG. 3B is a graph showing the correlation between the power spectral density at a spatial wavelength of 0.1 μm and the DWO value. is there. Thus, the power spectral density and the haze value at each spatial wavelength have a correlation. By approximating this data with a linear function using the least square method, the power spectral density at a spatial wavelength of 1 μm is X 1 (nm 3 ), and the power spectral density at a spatial wavelength of 0.1 μm is X 2 (nm 3 ). In this case, correlation functions such as X 1 = 2 × 10 −5 DNN + 1.2 × 10 −3 and X 2 = 2 × 10 −5 DWO + 7 × 10 −6 were obtained.

すなわち、実験1〜実験3の結果に基づいて、ヘイズ値と所定の空間波長でのパワースペクトル密度との相関関数を求めたので、この後のシリコンウエーハの評価を行なう際には、上記相関関数を用いることにより、ヘイズ値を測定するだけで、空間波長1μmでのパワースペクトル密度及び空間波長0.1μmでのパワースペクトル密度を算出できる。   That is, since the correlation function between the haze value and the power spectral density at a predetermined spatial wavelength is obtained based on the results of Experiments 1 to 3, the correlation function is used when evaluating the silicon wafer thereafter. By using this, the power spectral density at a spatial wavelength of 1 μm and the power spectral density at a spatial wavelength of 0.1 μm can be calculated simply by measuring the haze value.

従って、DNN値の評価結果に応じて研磨条件を調整し、DWO値の評価結果に応じて洗浄条件を調整すれば、空間波長1μm、空間波長0.1μmにおけるパワースペクトル密度を効果的に減少させることができ、ウエーハ表面のマイクロラフネスを効果的に改善することが可能となる。特に、少なくともDNN値が10ppb以下、DWO値が2ppb以下になるように研磨条件、洗浄条件の調整を行なえば、ウエーハ表面のマイクロラフネスが十分に小さくなり、近年のデバイスの高集積化、高精度化により要求される電気特性を達成するのに十分なマイクロラフネスの表面を有する半導体ウエーハを製造することが可能となる。   Therefore, if the polishing conditions are adjusted according to the evaluation result of the DNN value and the cleaning conditions are adjusted according to the evaluation result of the DWO value, the power spectral density at a spatial wavelength of 1 μm and a spatial wavelength of 0.1 μm is effectively reduced. This can effectively improve the microroughness of the wafer surface. In particular, if the polishing and cleaning conditions are adjusted so that at least the DNN value is 10 ppb or less and the DWO value is 2 ppb or less, the microroughness of the wafer surface becomes sufficiently small, and the recent device integration and high accuracy are achieved. It becomes possible to manufacture a semiconductor wafer having a microroughness surface sufficient to achieve electrical characteristics required by the fabrication.

なお、本発明は、上記実施形態に限定されるものではない。上記実施形態は単なる例示であり、本発明の特許請求の範囲に記載された技術的思想と実質的に同一な構成を有し、同様な作用効果を奏するものは、いかなるものであっても本発明の技術的範囲に包含される。   The present invention is not limited to the above embodiment. The above embodiment is merely an example, and the present invention has the same configuration as that of the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.

本発明に係る半導体ウエーハの評価方法の一例を示す工程図である。It is process drawing which shows an example of the evaluation method of the semiconductor wafer which concerns on this invention. 実験1〜実験3において得られたシリコンウエーハの表面状態のパワースペクトルA、B、Cを示すグラフである。It is a graph which shows the power spectra A, B, and C of the surface state of the silicon wafer obtained in Experiment 1 to Experiment 3. (a)は空間波長1μmでのパワースペクトル密度とDNN値の相関を示すグラフであり、(b)は空間波長0.1μmでのパワースペクトル密度とDWO値の相関を示すグラフである。(A) is a graph showing the correlation between the power spectral density at a spatial wavelength of 1 μm and the DNN value, and (b) is a graph showing the correlation between the power spectral density at a spatial wavelength of 0.1 μm and the DWO value.

Claims (7)

半導体ウエーハの評価方法であって、少なくとも、予め半導体ウエーハ表面の垂直照射・高角度受光のヘイズ値及び/又は斜角照射・低角度受光のヘイズ値を測定すると共に、該ウエーハの表面形状を測定し、該測定したウエーハの表面形状のデータをパワースペクトルに変換し、該パワースペクトルにおいて、空間波長1μmでのパワースペクトル密度と前記垂直照射・高角度受光ヘイズ値との相関関係及び/又は空間波長0.1μmでのパワースペクトル密度と前記斜角照射・低角度受光ヘイズ値との相関関係を求めておくことを特徴とする半導体ウエーハの評価方法。   A method for evaluating a semiconductor wafer, at least measuring a haze value of vertical irradiation / high angle light reception and / or a haze value of oblique angle irradiation / low angle light reception on a semiconductor wafer surface in advance and measuring the surface shape of the wafer Then, the measured wafer surface shape data is converted into a power spectrum, and in the power spectrum, the correlation between the power spectrum density at a spatial wavelength of 1 μm and the vertical irradiation / high angle received haze value and / or the spatial wavelength A method for evaluating a semiconductor wafer, characterized in that a correlation between a power spectral density at 0.1 μm and the oblique angle irradiation / low angle light receiving haze value is obtained. 請求項1に記載の評価方法であって、半導体ウエーハ表面の垂直照射・高角度受光のヘイズ値及び/又は斜角照射・低角度受光のヘイズ値を測定し、該ヘイズ値と前記相関関係とを用いて前記空間波長におけるパワースペクトル密度を算出することにより、該半導体ウエーハの表面形状を評価することを特徴とする半導体ウエーハの評価方法。   The evaluation method according to claim 1, wherein a haze value of vertical irradiation / high angle light reception and / or a haze value of oblique irradiation / low angle light reception on a semiconductor wafer surface is measured, and the haze value and the correlation are measured. A method for evaluating a semiconductor wafer, wherein the surface shape of the semiconductor wafer is evaluated by calculating the power spectral density at the spatial wavelength using 請求項1又は請求項2に記載の評価方法であって、前記ヘイズ値をパーティクルカウンターで測定することを特徴とする評価方法。   The evaluation method according to claim 1, wherein the haze value is measured with a particle counter. 請求項1乃至請求項3のいずれか一項に記載の評価方法であって、前記半導体ウエーハの表面形状を、原子間力顕微鏡法、触針法、光干渉法、位相シフト干渉法、光散乱トポグラフィ法のいずれかで測定することを特徴とする評価方法。   The evaluation method according to any one of claims 1 to 3, wherein the surface shape of the semiconductor wafer is determined by atomic force microscopy, stylus method, optical interferometry, phase shift interferometry, light scattering. An evaluation method characterized by measuring by any of the topography methods. 少なくとも、半導体インゴットをスライスして得られたウエーハを研磨した後に洗浄する半導体ウエーハの製造方法であって、請求項1乃至請求項4のいずれか一項に記載の方法により前記ウエーハの表面形状を評価し、該評価結果に応じて、研磨条件及び/又は洗浄条件を調整することを特徴とする半導体ウエーハの製造方法。   5. A method for manufacturing a semiconductor wafer, comprising: polishing a wafer obtained by slicing a semiconductor ingot and then cleaning the wafer, wherein the surface shape of the wafer is changed by the method according to claim 1. A method for manufacturing a semiconductor wafer, characterized by evaluating and adjusting polishing conditions and / or cleaning conditions according to the evaluation results. 請求項5に記載の製造方法であって、垂直照射・高角度受光のヘイズの評価結果に応じて前記研磨条件を調整し及び/又は斜角照射・低角度受光のヘイズの評価結果に応じて前記洗浄条件を調整することを特徴とする製造方法。   6. The manufacturing method according to claim 5, wherein the polishing condition is adjusted according to a haze evaluation result of vertical irradiation / high angle light reception and / or a haze evaluation result of oblique angle irradiation / low angle light reception. A manufacturing method characterized by adjusting the cleaning conditions. 請求項5又は請求項6に記載の製造方法であって、少なくとも垂直照射・高角度受光のヘイズ値が10ppb以下及び斜角照射・低角度受光のヘイズ値が2ppb以下になるように研磨条件及び洗浄条件の調整を行なうことを特徴とする製造方法。   The manufacturing method according to claim 5 or 6, wherein at least the haze value of vertical irradiation / high angle light reception is 10 ppb or less and the haze value of oblique irradiation / low angle light reception is 2 ppb or less. A manufacturing method comprising adjusting cleaning conditions.
JP2005092557A 2005-03-28 2005-03-28 Semiconductor wafer evaluation method and manufacturing method Active JP4385978B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005092557A JP4385978B2 (en) 2005-03-28 2005-03-28 Semiconductor wafer evaluation method and manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005092557A JP4385978B2 (en) 2005-03-28 2005-03-28 Semiconductor wafer evaluation method and manufacturing method

Publications (2)

Publication Number Publication Date
JP2006278515A true JP2006278515A (en) 2006-10-12
JP4385978B2 JP4385978B2 (en) 2009-12-16

Family

ID=37212992

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005092557A Active JP4385978B2 (en) 2005-03-28 2005-03-28 Semiconductor wafer evaluation method and manufacturing method

Country Status (1)

Country Link
JP (1) JP4385978B2 (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010050365A1 (en) * 2008-10-31 2010-05-06 株式会社日立ハイテクノロジーズ Reference wafer for calibrating dark-field inspection device, method for fabricating reference wafer for calibrating dark-field inspection device, method for calibrating dark-field inspection device, dark-field inspection device, and wafer inspection method
JP2013038435A (en) * 2012-09-13 2013-02-21 Shin Etsu Handotai Co Ltd Silicon single crystal wafer manufacturing method and silicon single crystal wafer evaluation method
WO2013031445A1 (en) * 2011-08-31 2013-03-07 株式会社 日立ハイテクノロジーズ Surface shape measurement device
JP2013114730A (en) * 2011-11-30 2013-06-10 Showa Denko Kk Substrate for magnetic recording medium, magnetic recording medium, and manufacturing method and surface inspection method of substrate for magnetic recording medium
WO2013118543A1 (en) * 2012-02-09 2013-08-15 株式会社 日立ハイテクノロジーズ Surface measurement device
WO2013146990A1 (en) * 2012-03-28 2013-10-03 Hoya株式会社 Mask blank substrate, substrate with multilayer reflection film, transparent mask blank, reflecting mask, transparent mask, and reflecting mask and semiconductor fabrication method
WO2014104276A1 (en) * 2012-12-28 2014-07-03 Hoya株式会社 Substrate for mask blank, substrate with multilayer reflective film, reflective type mask blank, reflective type mask, manufacturing method of substrate for mask blank and manufacturing method of substrate with multilayer reflective film as well as manufacturing method of semiconductor device
JP2017092400A (en) * 2015-11-17 2017-05-25 信越半導体株式会社 Method for determining defective region
WO2021205950A1 (en) * 2020-04-08 2021-10-14 信越半導体株式会社 Method for measuring formation of dic defects in silicon wafer, and polishing method

Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8831899B2 (en) 2008-10-31 2014-09-09 Hitachi High-Technologies Corporation Inspecting apparatus and an inspecting method
JP2010109257A (en) * 2008-10-31 2010-05-13 Hitachi High-Technologies Corp Reference wafer for calibration of dark field inspection system, method of manufacturing the same, method of calibration of dark field inspection system, the dark field inspection system, and wafer inspection method
WO2010050365A1 (en) * 2008-10-31 2010-05-06 株式会社日立ハイテクノロジーズ Reference wafer for calibrating dark-field inspection device, method for fabricating reference wafer for calibrating dark-field inspection device, method for calibrating dark-field inspection device, dark-field inspection device, and wafer inspection method
WO2013031445A1 (en) * 2011-08-31 2013-03-07 株式会社 日立ハイテクノロジーズ Surface shape measurement device
JP2013050371A (en) * 2011-08-31 2013-03-14 Hitachi High-Technologies Corp Surface shape measuring device
US9310190B2 (en) 2011-08-31 2016-04-12 Hitachi High-Technologies Corporation Surface shape measuring apparatus
JP2013114730A (en) * 2011-11-30 2013-06-10 Showa Denko Kk Substrate for magnetic recording medium, magnetic recording medium, and manufacturing method and surface inspection method of substrate for magnetic recording medium
US9366625B2 (en) 2012-02-09 2016-06-14 Hitachi High-Technologies Corporation Surface measurement device
WO2013118543A1 (en) * 2012-02-09 2013-08-15 株式会社 日立ハイテクノロジーズ Surface measurement device
KR101477470B1 (en) 2012-03-28 2014-12-29 호야 가부시키가이샤 Mask blank substrate, substrate with multilayer reflection film, transparent mask blank, reflecting mask, transparent mask, and reflecting mask and semiconductor fabrication method
US9494851B2 (en) 2012-03-28 2016-11-15 Hoya Corporation Mask blank substrate, substrate with multilayer reflection film, transmissive mask blank, reflective mask, and semiconductor device fabrication method
JP2014186333A (en) * 2012-03-28 2014-10-02 Hoya Corp Substrate for mask blank, substrate with multilayer reflection membrane, transmission type mask blank, reflection type mask blank, transmission type mask, reflection type mask, and method of manufacturing semiconductor device
JP5538638B2 (en) * 2012-03-28 2014-07-02 Hoya株式会社 Mask blank substrate, substrate with multilayer reflective film, transmissive mask blank, reflective mask blank, transmissive mask, reflective mask, and method for manufacturing semiconductor device
JPWO2013146990A1 (en) * 2012-03-28 2015-12-14 Hoya株式会社 Mask blank substrate, substrate with multilayer reflective film, transmissive mask blank, reflective mask blank, transmissive mask, reflective mask, and method for manufacturing semiconductor device
WO2013146990A1 (en) * 2012-03-28 2013-10-03 Hoya株式会社 Mask blank substrate, substrate with multilayer reflection film, transparent mask blank, reflecting mask, transparent mask, and reflecting mask and semiconductor fabrication method
US10295900B2 (en) 2012-03-28 2019-05-21 Hoya Corporation Mask blank substrate, substrate with multilayer reflection film, transmissive mask blank, reflective mask, and semiconductor device fabrication method
US10001699B2 (en) 2012-03-28 2018-06-19 Hoya Corporation Mask blank substrate, substrate with multilayer reflection film, transmissive mask blank, reflective mask, and semiconductor device fabrication method
TWI607277B (en) * 2012-03-28 2017-12-01 Hoya Corp Photomask substrate substrate, substrate with multilayer reflection film, transmission type photomask substrate, reflection type photomask substrate, transmission type photomask, reflection type photomask, and method for manufacturing semiconductor device
JP2013038435A (en) * 2012-09-13 2013-02-21 Shin Etsu Handotai Co Ltd Silicon single crystal wafer manufacturing method and silicon single crystal wafer evaluation method
US9581895B2 (en) 2012-12-28 2017-02-28 Hoya Corporation Mask blank substrate, substrate with multilayer reflective film, reflective mask blank, reflective mask, method of manufacturing mask blank substrate, method of manufacturing substrate with reflective film and method of manufacturing semiconductor device
JPWO2014104276A1 (en) * 2012-12-28 2017-01-19 Hoya株式会社 Mask blank substrate, substrate with multilayer reflective film, reflective mask blank, reflective mask, method for manufacturing mask blank substrate, method for manufacturing substrate with multilayer reflective film, and method for manufacturing semiconductor device
WO2014104276A1 (en) * 2012-12-28 2014-07-03 Hoya株式会社 Substrate for mask blank, substrate with multilayer reflective film, reflective type mask blank, reflective type mask, manufacturing method of substrate for mask blank and manufacturing method of substrate with multilayer reflective film as well as manufacturing method of semiconductor device
US10025176B2 (en) 2012-12-28 2018-07-17 Hoya Corporation Mask blank substrate, substrate with multilayer reflective film, reflective mask blank, reflective mask, method of manufacturing mask blank substrate, method of manufacturing substrate with reflective film and method of manufacturing semiconductor device
JP2017092400A (en) * 2015-11-17 2017-05-25 信越半導体株式会社 Method for determining defective region
WO2021205950A1 (en) * 2020-04-08 2021-10-14 信越半導体株式会社 Method for measuring formation of dic defects in silicon wafer, and polishing method

Also Published As

Publication number Publication date
JP4385978B2 (en) 2009-12-16

Similar Documents

Publication Publication Date Title
JP4385978B2 (en) Semiconductor wafer evaluation method and manufacturing method
JP4464033B2 (en) Semiconductor wafer shape evaluation method and shape evaluation apparatus
US6200908B1 (en) Process for reducing waviness in semiconductor wafers
CN108140593B (en) Method for determining defective area
JP5029234B2 (en) Epitaxial wafer manufacturing method
CN104969328B (en) Method for producing a gallium arsenide substrate, gallium arsenide substrate and use thereof
EP1900858B1 (en) Epitaxial wafer and method of producing same
JP2006278513A (en) Method for evaluating semiconductor wafer and process for producing semiconductor wafer
EP1868235A1 (en) Method and apparatus for evaluating semiconductor wafer and semiconductor wafer manufacturing method
JP4400331B2 (en) Wafer shape evaluation method and management method
US7810383B2 (en) Method for evaluating semiconductor wafer, apparatus for evaluating semiconductor wafer, and method for manufacturing semiconductor wafer
JPH05226203A (en) Mirror-surface wafer, its manufacture and its inspection method
JP6536502B2 (en) Method of manufacturing wafer for particle counter calibration
JP2020202289A (en) Manufacturing method of SiC epitaxial wafer
JP2000208578A (en) Evaluation method for silicon wafer and silicon wafer
KR20000011562A (en) Semiconductor wafer, method for producing the same, and wafer chuck
JP4003943B2 (en) Evaluation method of octahedral voids in silicon wafer
JP7251517B2 (en) Method for evaluating pretreatment conditions for epitaxial growth
JP7279753B2 (en) Silicon wafer cleaning method and manufacturing method
JPH1174493A (en) Inspecting method for defect of soi wafer
JP2003142544A (en) Method for evaluating minute defect in silicon wafer
US20160168020A1 (en) Method of finishing pre-polished glass substrate surface
KR101000252B1 (en) An Estimating Method Of Surface Damage For Wafer
Sorooshian et al. Dependence of oxide pattern density variation on motor current endpoint detection during shallow trench isolation chemical mechanical planarization
JPH08167640A (en) Semiconductor substrate for foreign matter control

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070226

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090417

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090428

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090616

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20090908

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20090921

R150 Certificate of patent or registration of utility model

Ref document number: 4385978

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121009

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131009

Year of fee payment: 4

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250