JP2006278438A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2006278438A
JP2006278438A JP2005091583A JP2005091583A JP2006278438A JP 2006278438 A JP2006278438 A JP 2006278438A JP 2005091583 A JP2005091583 A JP 2005091583A JP 2005091583 A JP2005091583 A JP 2005091583A JP 2006278438 A JP2006278438 A JP 2006278438A
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semiconductor chip
signal line
power supply
electrically connected
wiring board
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Megumi Kusumi
恵 楠美
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Toshiba Corp
Kioxia Advanced Package Corp
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Toshiba Corp
Toshiba LSI Package Solutions Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can be improved in the electrical characteristics, without causing the manufacturing cost and the number of manufacturing processes to increase. <P>SOLUTION: The semiconductor device comprises a package substrate 2, semiconductor chip 5 mounted on the package substrate 2, semiconductor chip 7 mounted on the semiconductor chip 5, signal line group 9 consisting of a plurality of signal lines with one end electrically connected to the semiconductor chip 5 and the other end electrically connected to the package substrate 2, signal line group 10 consisting of a plurality of signal lines with one end electrically connected to the semiconductor chip 7 and the other end electrically connected to the package substrate 2, a plurality of power supply lines 11a with one end electrically connected to the semiconductor chip 5 and the other end electrically connected to the package substrate 2, and a plurality of power supply lines 11b with one end electrically connected to the semiconductor chip 7 and the other end electrically connected to the package substrate 2. The semiconductor device also includes a power supply line group 11, at least a part of which is located between the signal line group 9 and the signal line group 10. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体装置に関する。   The present invention relates to a semiconductor device.

近年、電子機器の小型・薄型化への要求が高まっているのを受け、半導体装置の実装面積縮小の要求が高まっている。しかしながら、従来の１つのパッケージ内に１つの半導体チップを搭載する技術においては、実装面積の縮小には限界がある。そこで、１つのパッケージ内に２つ以上の半導体チップを搭載するＳｉＰ（System in Package）技術が特に注目されている。この技術によれば、実装面積の縮小が可能になる。   In recent years, demands for reducing the mounting area of semiconductor devices are increasing in response to increasing demands for smaller and thinner electronic devices. However, in the conventional technique of mounting one semiconductor chip in one package, there is a limit to reducing the mounting area. Therefore, SiP (System in Package) technology in which two or more semiconductor chips are mounted in one package has attracted particular attention. According to this technique, the mounting area can be reduced.

しかしながら、搭載されている半導体チップ同士が電気的に干渉し合い、１つのパッケージ内に１つの半導体チップを搭載する場合に比べて、クロストークの発生、インピーダンスの不整合など電気的特性が劣化し易い。   However, the mounted semiconductor chips interfere with each other electrically, and the electrical characteristics such as the occurrence of crosstalk and impedance mismatching deteriorate compared to the case where one semiconductor chip is mounted in one package. easy.

一方、パッケージに搭載される半導体チップの高速化に伴い、出力される信号等の電気的特性を劣化させずに伝達することが重要視されている。そこで、電気的特性の劣化を抑制する目的からパッケージ基板にリングと呼ばれるエリアが設けられる場合がある。リングを設けることにより、半導体チップからボンディングワイヤ、リング、スルーホールを介してパッケージ基板内に設けた電源層に接続することができ、これにより、クロストークの発生、又はインピーダンスの不整合など、電気的特性の劣化を招く要因を軽減させることができる。しかしながら、ＳｉＰ構造のものにおいては、従来の２つ或いは３つのパッケージとなるものを１つのパッケージに収めている構造上、リングや電源層を形成するスペースを確保することができない。   On the other hand, with an increase in the speed of a semiconductor chip mounted on a package, it has been regarded as important to transmit without deteriorating electrical characteristics such as an output signal. Therefore, an area called a ring may be provided on the package substrate for the purpose of suppressing deterioration of electrical characteristics. By providing a ring, it is possible to connect the semiconductor chip to a power supply layer provided in the package substrate via a bonding wire, a ring, or a through hole. It is possible to reduce the factors that cause deterioration of the physical characteristics. However, in the case of the SiP structure, the space for forming the ring and the power supply layer cannot be secured due to the conventional structure in which two or three packages are housed in one package.

また、ＳｉＰ構造のものにおいては、上段の半導体チップ及び下段の半導体チップのそれぞれからワイヤボンディングを行っているため、従来のような上段の半導体チップ或いは下段の半導体チップに接続されたボンディングワイヤ間（横方向）の影響に加え、上段の半導体チップに接続されたボンディングワイヤと下段の半導体チップに接続されたボンディングワイヤとの間（上下方向）の影響を受けることとなり、電気的特性が劣化し易い。   In the SiP structure, wire bonding is performed from each of the upper semiconductor chip and the lower semiconductor chip, so that the conventional bonding between the bonding wires connected to the upper semiconductor chip or the lower semiconductor chip ( In addition to the influence of the lateral direction), the electrical characteristics are likely to deteriorate due to the influence of the bonding wire connected to the upper semiconductor chip and the bonding wire connected to the lower semiconductor chip (vertical direction). .

このようなことから、ＳｉＰ構造のものにおいては、電気的特性の劣化を抑制する技術が必要となる。特許文献１には、半導体チップと半導体チップとの間に、ボンディングワイヤによりグランド電位に保持された伝熱導電板を介在させ、電気的特性を向上させる技術が開示されている。また、特許文献２には、半導体チップと半導体チップとの間に、ボンディングワイヤにより電源電位或いはグランド電位に保持された銅箔を介在させ、上段の半導体チップの裏面を電源電位或いはグランド電位に保持する技術が開示されている。
特開２００４−１１１６５６号公報 特開２００４−３１６４９号公報 For this reason, in the SiP structure, a technique for suppressing deterioration of electrical characteristics is required. Patent Document 1 discloses a technique for improving electrical characteristics by interposing a heat transfer conductive plate held at a ground potential by a bonding wire between a semiconductor chip and a semiconductor chip. Further, in Patent Document 2, a copper foil held at a power supply potential or a ground potential by a bonding wire is interposed between the semiconductor chips, and the back surface of the upper semiconductor chip is held at the power supply potential or the ground potential. Techniques to do this are disclosed.
JP 2004-111656 A JP 2004-31649 A

しかしながら、特許文献１においては、半導体チップと半導体チップとの間に伝熱導電板を介在させ、特許文献２においては、半導体チップと半導体チップとの間に銅箔を介在させているので、伝熱導電板或いは銅箔を新たに用意する必要がある。またパッケージ基板と伝熱導電板或いは銅箔とをボンディングワイヤで接続しているので、ボンディングワイヤ全体の本数が増大してしまう。この結果、製造コスト及び製造工程数等が増大してしまう。   However, in Patent Document 1, a heat transfer conductive plate is interposed between the semiconductor chips, and in Patent Document 2, a copper foil is interposed between the semiconductor chip and the semiconductor chip. It is necessary to newly prepare a heat conductive plate or copper foil. Further, since the package substrate and the heat transfer conductive plate or the copper foil are connected by the bonding wire, the total number of bonding wires is increased. As a result, the manufacturing cost and the number of manufacturing steps increase.

また、半導体チップと半導体チップとの間に、伝熱導電板或いは銅箔を介在させることにより、上段の半導体チップの上面の位置が高くなるので、上段の半導体チップに接続されているボンディングワイヤの長さが長くなってしまい、電気的特性を劣化させるおそれがある。   Further, by interposing a heat transfer conductive plate or copper foil between the semiconductor chips, the position of the upper surface of the upper semiconductor chip is increased, so that the bonding wire connected to the upper semiconductor chip There is a possibility that the length becomes long and the electrical characteristics are deteriorated.

本発明は、上記課題を解決するためになされたものである。即ち、本発明は、製造コスト及び製造工程数を増大させずに電気的特性を向上させることができる半導体装置を提供することを目的とする。   The present invention has been made to solve the above problems. That is, an object of the present invention is to provide a semiconductor device that can improve electrical characteristics without increasing the manufacturing cost and the number of manufacturing steps.

本発明の一の態様によれば、配線基板と、前記配線基板上に搭載された第１の半導体チップと、前記第１の半導体チップ上に搭載された第２の半導体チップと、一端が前記第１の半導体チップに電気的に接続され且つ他端が前記配線基板に電気的に接続された複数の第１の信号線から成る第１の信号線群と、一端が前記第２の半導体チップに電気的に接続され且つ他端が前記配線基板に電気的に接続され、前記第１の信号線と電気的に分離された複数の第２の信号線から成る第２の信号線群と、一端が前記第１の半導体チップに電気的に接続され且つ他端が前記配線基板に電気的に接続され、前記第１及び第２の信号線と電気的に分離された複数の第１の電源線と、一端が前記第２の半導体チップに電気的に接続され且つ他端が前記配線基板に電気的に接続され、前記第１及び第２の信号線と電気的に分離された複数の第２の電源線とから成り、少なくとも一部が前記第１の信号線群と前記第２の信号線群との間に位置した電源線群とを具備することを特徴とする半導体装置が提供される。   According to one aspect of the present invention, a wiring board, a first semiconductor chip mounted on the wiring board, a second semiconductor chip mounted on the first semiconductor chip, and one end of the first semiconductor chip A first signal line group composed of a plurality of first signal lines electrically connected to the first semiconductor chip and having the other end electrically connected to the wiring board, and one end thereof being the second semiconductor chip A second signal line group comprising a plurality of second signal lines electrically connected to the other end and electrically connected to the wiring board and electrically separated from the first signal line; A plurality of first power supplies having one end electrically connected to the first semiconductor chip and the other end electrically connected to the wiring board and electrically separated from the first and second signal lines. One end of the wire is electrically connected to the second semiconductor chip, and the other end is the wiring board. A plurality of second power supply lines electrically connected and electrically separated from the first and second signal lines, and at least a part of the first signal line group and the second signal There is provided a semiconductor device comprising a power supply line group positioned between the line group.

本発明の一の態様によれば、製造コスト及び製造工程数を増大させずに電気的特性を向上させることができる。   According to one embodiment of the present invention, electrical characteristics can be improved without increasing the manufacturing cost and the number of manufacturing steps.

以下、図面を参照しながら実施の形態について説明する。図１は本実施の形態に係る半導体装置の模式的な垂直断面図であり、図２は図１のＡ−Ａ線で切断した半導体装置の模式的な垂直断面図である。   Hereinafter, embodiments will be described with reference to the drawings. FIG. 1 is a schematic vertical sectional view of the semiconductor device according to the present embodiment, and FIG. 2 is a schematic vertical sectional view of the semiconductor device cut along the line AA in FIG.

図１及び図２に示されるように、半導体装置１は、ＳｉＰ構造のものである。半導体装置１は、配線基板としての例えば多層配線構造を有するパッケージ基板２を備えている。パッケージ基板２の下面には、複数のはんだボール３が形成されている。パッケージ基板２の上面には接着剤４を介して半導体チップ５が搭載されており、半導体チップ５上には接着剤６を介して半導体チップ７が搭載されている。半導体チップ５，７は高周波領域で動作するものであり、半導体チップ５，７はモールド樹脂８により覆われている。   As shown in FIGS. 1 and 2, the semiconductor device 1 has a SiP structure. The semiconductor device 1 includes a package substrate 2 having, for example, a multilayer wiring structure as a wiring substrate. A plurality of solder balls 3 are formed on the lower surface of the package substrate 2. A semiconductor chip 5 is mounted on the upper surface of the package substrate 2 via an adhesive 4, and a semiconductor chip 7 is mounted on the semiconductor chip 5 via an adhesive 6. The semiconductor chips 5 and 7 operate in a high frequency region, and the semiconductor chips 5 and 7 are covered with a mold resin 8.

パッケージ基板２は、パッケージ基板２の上面であって半導体チップ５の外側の領域に形成された複数の信号線用パッド２ａ，２ｂ及び複数の電源線用パッド２ｃ，２ｄを備えている。信号線用パッド２ｂ（第２の信号線用パッド）は、信号線用パッド２ａ（第１の信号線用パッド）よりパッケージ基板２の外周側に形成されている。電源線用パッド２ｃは、信号線用パッド２ａよりパッケージ基板２の外周側に形成されている。本実施の形態では、電源線用パッド２ｃは信号線用パッド２ｂとほぼ同列に形成されており、電源線用パッド２ｄは信号線用パッド２ａとほぼ同列に形成されている。電源線用パッド２ｃは、接地電位（グランド電位）或いは電源電位に保持されている。半導体チップ５，７は、それぞれ半導体チップ５，７の上面であって半導体チップ５，７の外周縁部に形成された複数の信号線用パッド５ａ，７ａ及び複数の電源線用パッド５ｂ，７ｂを備えている。   The package substrate 2 includes a plurality of signal line pads 2a and 2b and a plurality of power supply line pads 2c and 2d formed on the upper surface of the package substrate 2 and outside the semiconductor chip 5. The signal line pad 2b (second signal line pad) is formed on the outer peripheral side of the package substrate 2 from the signal line pad 2a (first signal line pad). The power supply line pad 2c is formed on the outer peripheral side of the package substrate 2 from the signal line pad 2a. In the present embodiment, the power line pad 2c is formed in substantially the same row as the signal line pad 2b, and the power line pad 2d is formed in the substantially same row as the signal line pad 2a. The power supply line pad 2c is held at a ground potential (ground potential) or a power supply potential. The semiconductor chips 5 and 7 are a plurality of signal line pads 5a and 7a and a plurality of power supply line pads 5b and 7b formed on the outer peripheral edges of the semiconductor chips 5 and 7, respectively, on the upper surface of the semiconductor chips 5 and 7. It has.

パッケージ基板２と半導体チップ５，７とは信号線群９，１０及び電源線群１１を介して電気的に接続されている。信号線群９（第１の信号線群）は複数の信号線９ａから構成されており、信号線群１０（第２の信号線群）は複数の信号線１０ａから構成されている。信号線９ａは一端が信号線用パッド２ａに接続され、かつ他端が信号線用パッド５ａに接続されており、信号線１０ａは一端が信号線用パッド２ｂに接続され、かつ他端が信号線用パッド７ａに接続されている。信号線９ａと信号線１０ａとは、電気的に分離されている。なお、信号線９ａはワイヤボンディングにより信号線用パッド２ａと信号線用パッド５ａに接続されており、信号線１０ａはワイヤボンディングにより信号線用パッド２ｂと信号線用パッド７ａに接続されている。   The package substrate 2 and the semiconductor chips 5 and 7 are electrically connected via signal line groups 9 and 10 and a power supply line group 11. The signal line group 9 (first signal line group) is composed of a plurality of signal lines 9a, and the signal line group 10 (second signal line group) is composed of a plurality of signal lines 10a. The signal line 9a has one end connected to the signal line pad 2a and the other end connected to the signal line pad 5a. The signal line 10a has one end connected to the signal line pad 2b and the other end connected to the signal line. It is connected to the line pad 7a. The signal line 9a and the signal line 10a are electrically separated. The signal line 9a is connected to the signal line pad 2a and the signal line pad 5a by wire bonding, and the signal line 10a is connected to the signal line pad 2b and the signal line pad 7a by wire bonding.

電源線群１１は、複数の電源線１１ａ（第１の電源線）及び複数の電源線１１ｂ（第２の電源線）から構成されている。電源線１１ａは一端が電源線用パッド２ｃに接続され、かつ他端が電源線用パッド５ｂに接続されており、電源線１１ｂは一端が電源線用パッド２ｃに接続され、かつ他端が電源線用パッド７ｂに接続されている。ここで、本実施の形態では、電源線用パッド２ｄは使用されていないが、搭載する半導体チップに応じて使用する電源線用パッド２ｃ，２ｄを使い分けることが可能である。電源線１１ａ，１１ｂは、信号線９ａ，１０ａと電気的に分離されている。電源線１１ｂは、電源線１１ａが接続されている電源線用パッド２ｃとは異なる電源線用パッド２ｃに接続されている。電源線群１１の少なくとも一部は、信号線群９と信号線群１０との間に位置している。なお、電源線１１ａはワイヤボンディングにより電源線用パッド２ｃと電源線用パッド５ｂに接続されており、電源線１１ｂはワイヤボンディングにより電源線用パッド２ｃと電源線用パッド７ｂに接続されている。   The power supply line group 11 includes a plurality of power supply lines 11a (first power supply lines) and a plurality of power supply lines 11b (second power supply lines). The power line 11a has one end connected to the power line pad 2c and the other end connected to the power line pad 5b. The power line 11b has one end connected to the power line pad 2c and the other end connected to the power source. It is connected to the line pad 7b. Here, in this embodiment, the power supply line pad 2d is not used, but the power supply line pads 2c and 2d to be used can be used properly according to the semiconductor chip to be mounted. The power supply lines 11a and 11b are electrically separated from the signal lines 9a and 10a. The power supply line 11b is connected to a power supply line pad 2c different from the power supply line pad 2c to which the power supply line 11a is connected. At least a part of the power supply line group 11 is located between the signal line group 9 and the signal line group 10. The power supply line 11a is connected to the power supply line pad 2c and the power supply line pad 5b by wire bonding, and the power supply line 11b is connected to the power supply line pad 2c and the power supply line pad 7b by wire bonding.

本実施の形態では、電源線群１１の少なくとも一部が信号線群９と信号線群１０との間に位置しているので、電源線群１１のこの部分によるシールド効果により信号線群９と信号線群１０とを電気的に遮蔽することができる。これにより、信号線群９と信号線群１０との間における電気的干渉を抑制することができ、クロストークを低減させることができるともにインピーダンス整合を実現することができる。それ故、半導体装置１の電気的特性を向上させることができる。   In this embodiment, since at least a part of the power line group 11 is located between the signal line group 9 and the signal line group 10, the signal line group 9 and The signal line group 10 can be electrically shielded. As a result, electrical interference between the signal line group 9 and the signal line group 10 can be suppressed, crosstalk can be reduced, and impedance matching can be realized. Therefore, the electrical characteristics of the semiconductor device 1 can be improved.

本実施の形態では、電源線１１の少なくとも一部を信号線群９と信号線群１０との間に位置させるだけで、電気的特性を向上させることができるので、ボンディングワイヤの本数の増大させることなく、また伝熱導電板等の新たな部品を用いることなく、電気的特性を向上させることができる。これにより、製造コスト及び製造工程数を増大させることなく、半導体装置１の電気的特性を向上させることができる。   In the present embodiment, it is possible to improve the electrical characteristics only by positioning at least a part of the power supply line 11 between the signal line group 9 and the signal line group 10, and thus the number of bonding wires is increased. The electrical characteristics can be improved without using new components such as a heat transfer conductive plate. Thereby, the electrical characteristics of the semiconductor device 1 can be improved without increasing the manufacturing cost and the number of manufacturing steps.

本実施の形態では、半導体チップ５と半導体チップ７との間に伝熱導電板等を介在させていないので、半導体チップ７の上面の位置が高くならない。これにより、半導体チップ７に接続されている信号線１０ａの長さが長くならず、半導体装置１の電気的特性をより向上させることができる。   In this embodiment, since the heat transfer conductive plate or the like is not interposed between the semiconductor chip 5 and the semiconductor chip 7, the position of the upper surface of the semiconductor chip 7 does not increase. Thereby, the length of the signal line 10a connected to the semiconductor chip 7 is not increased, and the electrical characteristics of the semiconductor device 1 can be further improved.

上段の半導体チップを下段の半導体チップに搭載する際、下段の半導体チップのボンディングエリアを確保するため、通常下段の半導体チップの外周端から片側３００〜５００μｍ程度距離を取る必要がある。一方、上段の半導体チップと下段の半導体チップとの間に伝熱導電板等を介在させ、かつ電気的特性を向上させるために上段の半導体チップの裏面を電源電位或いはグランド電位に保持する場合、伝熱導電板等にもにはボンディングワイヤを接続する必要がある。これらのことを考慮すると、上段の半導体チップと下段の半導体チップの間に伝熱導電板等を介在させる場合、下段の半導体チップの外周端からボンディングエリアとして片側３００〜５００μｍ程度の距離を取る他、伝熱導電板等の外周端からもボンディングエリアとして片側３００〜５００μｍ程度距離を取る必要がある。従って、半導体チップと半導体チップの間に伝熱導電板等を介在させる場合、上段の半導体チップは下段の半導体チップよりも片側６００〜１０００μｍ程度、チップサイズで換算すると１２００〜２０００μｍ小さいサイズでなければ搭載できないという製造上の制約が発生する。これに対し、本実施の形態では、半導体チップ５と半導体チップ７との間に伝熱導電板等を介在させないので、伝熱導電板等を介在させた場合より、大きなサイズの半導体チップ７を搭載することができる。   When the upper semiconductor chip is mounted on the lower semiconductor chip, it is usually necessary to take a distance of about 300 to 500 μm on one side from the outer peripheral edge of the lower semiconductor chip in order to secure a bonding area of the lower semiconductor chip. On the other hand, when a heat transfer conductive plate or the like is interposed between the upper semiconductor chip and the lower semiconductor chip, and the back surface of the upper semiconductor chip is held at the power supply potential or the ground potential in order to improve electrical characteristics, It is necessary to connect a bonding wire to the heat transfer conductive plate or the like. In consideration of these points, when a heat transfer conductive plate or the like is interposed between the upper semiconductor chip and the lower semiconductor chip, a distance of about 300 to 500 μm on one side is taken as a bonding area from the outer peripheral edge of the lower semiconductor chip. Further, it is necessary to take a distance of about 300 to 500 μm on one side as a bonding area from the outer peripheral end of the heat transfer conductive plate or the like. Therefore, when a heat transfer conductive plate or the like is interposed between the semiconductor chips, the upper semiconductor chip must be about 600 to 1000 μm on one side than the lower semiconductor chip, and not smaller than 1200 to 2000 μm in terms of chip size. There is a manufacturing restriction that it cannot be mounted. On the other hand, in this embodiment, since the heat transfer conductive plate or the like is not interposed between the semiconductor chip 5 and the semiconductor chip 7, the semiconductor chip 7 having a larger size than the case where the heat transfer conductive plate or the like is interposed. Can be installed.

本実施の形態では、電源線１１の少なくとも一部を信号線群９と信号線群１０との間に位置させているので、伝熱導電板等を介在させた場合に比べて、信号線群９と電源線群１１との距離、信号線群１０と電源線１１の距離が短くなり、より高いシールド効果を期待できる。   In this embodiment, since at least a part of the power supply line 11 is positioned between the signal line group 9 and the signal line group 10, the signal line group is compared with a case where a heat transfer conductive plate or the like is interposed. 9 and the power line group 11 and the distance between the signal line group 10 and the power line 11 are shortened, and a higher shielding effect can be expected.

なお、本発明は上記実施の形態の記載内容に限定されるものではなく、構造や材質、各部材の配置等は、本発明の要旨を逸脱しない範囲で適宜変更可能である。例えば、上記実施の形態では、上下２段の半導体チップ５，７を用いて説明しているが、３段以上であってもよい。   Note that the present invention is not limited to the description of the above embodiment, and the structure, material, arrangement of each member, and the like can be appropriately changed without departing from the gist of the present invention. For example, although the above embodiment has been described using the upper and lower two-stage semiconductor chips 5 and 7, it may be three or more stages.

実施の形態に係る半導体装置の模式的な垂直断面図である。1 is a schematic vertical sectional view of a semiconductor device according to an embodiment. 図１のＡ−Ａ線で切断した半導体装置の模式的な垂直断面図である。FIG. 2 is a schematic vertical sectional view of the semiconductor device cut along line AA in FIG. 1.

符号の説明Explanation of symbols

１…半導体装置、２…パッケージ基板、２ａ，２ｂ…信号線用パッド、２ｃ，２ｄ…電源線用パッド、３…はんだボール、５，７…半導体チップ、８…モールド樹脂、５ａ，７ａ…信号線用パッド、５ｂ，７ｂ…電源線用パッド、９，１０…信号線群、９ａ，１０ａ…信号線、１１…電源線群、１１ａ，１１ｂ…電源線。   DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... Package substrate, 2a, 2b ... Signal line pad, 2c, 2d ... Power supply line pad, 3 ... Solder ball, 5, 7 ... Semiconductor chip, 8 ... Mold resin, 5a, 7a ... Signal Line pads, 5b, 7b ... Power supply line pads, 9, 10 ... Signal line group, 9a, 10a ... Signal line, 11 ... Power supply line group, 11a, 11b ... Power supply line.

Claims (4)

配線基板と、
前記配線基板上に搭載された第１の半導体チップと、
前記第１の半導体チップ上に搭載された第２の半導体チップと、
一端が前記第１の半導体チップに電気的に接続され且つ他端が前記配線基板に電気的に接続された複数の第１の信号線から成る第１の信号線群と、
一端が前記第２の半導体チップに電気的に接続され且つ他端が前記配線基板に電気的に接続され、前記第１の信号線と電気的に分離された複数の第２の信号線から成る第２の信号線群と、
一端が前記第１の半導体チップに電気的に接続され且つ他端が前記配線基板に電気的に接続され、前記第１及び第２の信号線と電気的に分離された複数の第１の電源線と、一端が前記第２の半導体チップに電気的に接続され且つ他端が前記配線基板に電気的に接続され、前記第１及び第２の信号線と電気的に分離された複数の第２の電源線とから成り、少なくとも一部が前記第１の信号線群と前記第２の信号線群との間に位置した電源線群と、
を具備することを特徴とする半導体装置。 A wiring board;
A first semiconductor chip mounted on the wiring board;
A second semiconductor chip mounted on the first semiconductor chip;
A first signal line group comprising a plurality of first signal lines, one end of which is electrically connected to the first semiconductor chip and the other end of which is electrically connected to the wiring board;
One end is electrically connected to the second semiconductor chip and the other end is electrically connected to the wiring board, and includes a plurality of second signal lines electrically separated from the first signal line. A second signal line group;
A plurality of first power supplies having one end electrically connected to the first semiconductor chip and the other end electrically connected to the wiring board and electrically separated from the first and second signal lines. A plurality of first lines electrically connected to the first and second signal lines and having one end electrically connected to the second semiconductor chip and the other end electrically connected to the wiring board. Two power supply lines, and at least a part of the power supply line group located between the first signal line group and the second signal line group;
A semiconductor device comprising: 前記配線基板は複数の第１の信号線用パッド、前記第１の信号線用パッドより前記配線基板の外周側に位置した複数の第２の信号線用パッド、及び前記第１の信号線用パッドより前記配線基板の外周側に位置した複数の電源線用パッドを備えており、前記第１及び第２の半導体チップはそれぞれ複数の信号線用パッド及び複数の電源線用パッドを備えており、
前記第１の信号線の前記一端は前記第１の半導体チップの前記信号線用パッドに接続され且つ前記他端は前記配線基板の前記第１の信号線用パッドに接続されており、前記第２の信号線の前記一端は前記第２の半導体チップの前記信号線用パッドに接続され且つ前記他端は前記配線基板の前記第２の信号線用パッドに接続されており、
前記第１の電源線の前記一端は前記第１の半導体チップの前記電源線用パッドに接続され且つ前記他端は前記配線基板の前記電源線用パッドに接続されており、前記第２の電源線の前記一端は前記第２の半導体チップの前記電源線用パッドに接続され且つ前記他端は前記配線基板の前記電源線用パッドに接続されていることを特徴とする請求項１記載の半導体装置。 The wiring board includes a plurality of first signal line pads, a plurality of second signal line pads located on an outer peripheral side of the wiring board from the first signal line pads, and the first signal line pads. A plurality of power line pads are provided on the outer peripheral side of the wiring board from the pads, and the first and second semiconductor chips each include a plurality of signal line pads and a plurality of power line pads. ,
The one end of the first signal line is connected to the signal line pad of the first semiconductor chip, and the other end is connected to the first signal line pad of the wiring board. The one end of the second signal line is connected to the signal line pad of the second semiconductor chip and the other end is connected to the second signal line pad of the wiring board;
The one end of the first power supply line is connected to the power supply line pad of the first semiconductor chip, and the other end is connected to the power supply line pad of the wiring board, and the second power supply 2. The semiconductor according to claim 1, wherein the one end of the line is connected to the power line pad of the second semiconductor chip, and the other end is connected to the power line pad of the wiring board. apparatus. 前記第１の電源線の一端は、前記配線基板おける前記第２の電源線が接続された前記電源線用パッドとは異なる前記電源線用パッドに接続されていることを特徴とする請求項２記載の半導体装置。   The one end of the first power supply line is connected to the power supply line pad different from the power supply line pad to which the second power supply line is connected in the wiring board. The semiconductor device described. 前記第１の電源線及び前記第２の電源線は、それぞれ接地電位に保持されていることを特徴とする請求項１乃至３のいずれか１項に記載の半導体装置。   4. The semiconductor device according to claim 1, wherein the first power supply line and the second power supply line are each held at a ground potential. 5.
JP2005091583A 2005-03-28 2005-03-28 Semiconductor device Withdrawn JP2006278438A (en)

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