JP2006278061A - Lighting system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inexpensive lighting system capable of controlling an illumination load by a normal control signal by accurately distinguishing noise from a zero cross detection signal regardless of the magnitude of noise. <P>SOLUTION: A zero cross detecting part 3 is equipped with a plurality of zero cross detecting means 31-3N to detect the zero cross of the output of an ac power source AC, and the zero cross detecting means 31-3N output zero cross detection signals A1-AN to a control part 4. The control part produces a control signal B from the difference in the waveform of each of the zero cross signals A1-AN, and outputs it to a light control circuit 1. The light control circuit 1 controls the phase of power supplied to the illumination load 2 from the ac power source AC by switching on and off the power source voltage from the ac power source AC in the timing of the control signal B, and controls brightness of the illumination load 2. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a lighting device.

  Conventionally, a phase control method has been mainly used for an illumination device that dimmes an incandescent lamp, a lighting fixture using an LED, or the like. As shown in FIGS. 20A to 20C, the phase control method is performed by turning on and off the power supply voltage Vac at a phase corresponding to a control signal E that alternately repeats the off period Toff and the on period Ton. The voltage VL supplied to the load is controlled to control the brightness of the lighting load.

  As a means for synchronizing the control signal E with the waveform of the power supply voltage Vac, a zero cross detector 20 as shown in FIG. 21 is used. The zero-cross detector 20 detects the zero-cross ta of the full-wave rectified voltage Vr (FIG. 22A) obtained by rectifying the power supply voltage Vac output from the AC power supply AC by the rectifier DB. A series circuit of connected resistors R21 and R22, an NPN transistor Q20 having a base connected to the connection point of the resistors R21 and R22, and a resistor R23 connected between the control voltage and the collector of the transistor Q20; The emitter of the transistor Q20 and the low-voltage side rectified output of the rectifier DB are connected to the ground level, and the collector potential of the transistor Q20 is output to the control unit 21 (see FIG. 24) as the zero cross detection signal D (FIG. 22B). When the zero cross is detected, the zero cross detection signal D is inverted to the H level.

  Next, using the rising edge of the zero-cross detection signal D as a trigger for counter start, the elapsed time from the rising timing t100 of the zero-cross detection signal D is counted by the counter, and the control signal E is set to the H level after the time T101 has elapsed (time t101). The control signal E is inverted to L level after time T102 has elapsed (time t102).

Then, using the control signal E generated in this way, the voltage supplied to the illumination load is phase-controlled to perform dimming. (For example, see Patent Document 1)
JP-A-9-311729

  The control signal E may be disturbed by noise that has entered the signal line of the power source or the zero cross detection signal. For example, as shown in FIGS. 23A to 23C, the control signal E is inverted to H level after the time T101 has elapsed since the rising of the zero-cross detection signal D at the time t110, and the control signal E is changed after the time T102 has elapsed. The control signal E0 generated by inverting it to the L level is a normal control signal.

  However, when noise Vra whose power source waveform is missing enters the full-wave rectified voltage Vr, pulse noise Da occurs in the zero-cross detection signal D at time t111. The control signal Ea generated by inverting the control signal E to the H level after the time T101 elapses from the rising edge of the pulse noise Da and inverting to the L level after the time T102 elapses becomes an erroneous control signal.

  Further, when the noise Db enters near the rising edge of the zero-cross detection signal D, the control signal E is generated by inverting the control signal E to the H level after the time T101 has elapsed from the rising edge of the noise Db and inverting to the L level after the time T102 has elapsed. The signal Eb is also an erroneous control signal.

  Conventionally, in order to remove such noise of the zero-cross detection signal D, a capacitor C20 is connected in parallel between the output terminals of the zero-cross detection unit 20 (FIG. 24), a capacitor is connected in parallel to the power source, There is a method of identifying noise by software of the control unit 21.

  However, in the method of connecting the capacitors C20 in parallel, when the capacitance of the capacitor C20 is small, the waveform of the zero-cross detection signal D rises and falls sharply as shown in FIG. Only pulse noise can be removed. When the capacitance of the capacitor C20 is large, the waveform of the zero-cross detection signal D becomes a waveform in which the rising and falling response times are delayed and the edges are rounded as shown in FIG. 25B, and any of the times t121, t122, and t123 is obtained. It is unclear whether should be the rising timing.

  Further, when trying to identify noise with the software of the control unit 21, a high-performance CPU and a high-speed oscillator are required, which causes problems such as an increase in cost and an increase in substrate area.

  The present invention has been made in view of the above-described reasons, and the object of the present invention is to accurately identify the noise and the zero-cross detection signal regardless of the magnitude of the noise, and to control the illumination load with a normal control signal. The object is to provide a cost lighting device.

  According to the first aspect of the present invention, there is provided an illumination load, a zero-cross detection unit provided with a plurality of zero-cross detection means for detecting a zero-cross of a power supply voltage of an AC power supply and outputting a zero-cross detection signal, and each output waveform of the plurality of zero-cross detection means A control unit that discriminates a zero-cross detection signal and noise from the difference and generates a control signal based on the zero-cross detection signal, and a dimming circuit that dims an illumination load based on the control signal .

  According to the present invention, it is possible to accurately identify the noise and the zero-crossing detection signal regardless of the magnitude of the noise, and to control the illumination load with a normal control signal, and to be configured at low cost.

  According to a second aspect of the present invention, in the first aspect, the plurality of zero-cross detection means are such that the signal levels at the time of zero-cross detection are inverted to the same polarity, and the width at the time of inversion is different from any other zero-cross detection means Each of the zero cross detection signals is output.

  According to the present invention, the normal control signal can be generated by removing the influence of the pulse noise generated in the zero cross detection signal due to the noise entering the power supply. In addition, the circuit can be configured to save space and cost, and the processing in the control unit can be executed with a simple algorithm.

  According to a third aspect of the present invention, in the first aspect, the plurality of zero-cross detection means invert the signal level at the time of zero-cross detection to a polarity different from that of any other zero-cross detection means, and have the same width at the time of inversion. Each of the zero-cross detection signals is output.

  According to the present invention, the normal control signal can be generated by removing the influence of the pulse noise generated in the zero-cross detection signal due to the positive / negative noise that has entered the signal line of the zero-cross detection signal. In addition, the circuit can be configured to save space and cost, and the processing in the control unit can be executed with a simple algorithm.

  According to a fourth aspect of the present invention, in the first aspect, the plurality of zero cross detection means invert the signal level at the time of zero cross detection to a polarity different from any of the other zero cross detection means, and the width at the time of inversion is other than A zero cross detection signal different from any zero cross detection means is output.

  According to the present invention, the normal control signal is generated by removing the influence of the pulse noise generated in the zero-cross detection signal due to the noise entering the power supply and the positive / negative noise entering the signal line of the zero-cross detection signal. be able to. In addition, the circuit can be configured to save space and cost, and the processing in the control unit can be executed with a simple algorithm.

  As described above, according to the present invention, it is possible to accurately identify the noise and the zero-crossing detection signal regardless of the magnitude of the noise, and to control the illumination load with a normal control signal and to be configured at low cost. is there.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 shows a configuration of an illumination device X according to the present embodiment, and the illumination device X includes a dimming circuit 1, an illumination load 2, a zero-cross detection unit 3, and a control unit 4.

  The zero-cross detection unit 3 includes a plurality of zero-cross detection units 31 to 3N that detect a zero-cross of the power supply voltage output from the AC power supply AC, and each of the zero-cross detection units 31 to 3N outputs the zero-cross detection signals A1 to AN to the control unit 4. To do. The control unit 4 generates a control signal B according to the zero cross detection signals A1 to AN and outputs the control signal B to the dimming circuit 1. The dimming circuit 1 controls the phase of power supplied from the AC power supply AC to the lighting load 2 by turning on and off the power supply voltage from the AC power supply AC at the timing of the control signal B, and the brightness of the lighting load 2 To control.

  FIG. 2 shows a configuration of the zero-cross detection unit 3 of the present embodiment, and includes a rectifier DB that rectifies the output of the AC power supply AC, and a series circuit of resistors R1, R2, and R3 connected between the rectification output terminals of the rectifier DB. NPN transistor Q1 having a base connected to the connection point of resistors R1 and R2, NPN transistor Q2 having a base connected to the connection point of resistors R2 and R3, and between the control voltage and the collector of transistor Q1 A resistor R4 connected, and a resistor R5 connected between the control voltage and the collector of the transistor Q2, the emitters of the transistors Q1 and Q2, and the low-voltage side rectified output of the rectifier DB are connected to the ground level; , Q2 are output as zero-cross detection signals A1, A2.

  The operation waveforms of each part of the zero cross detection unit 3 are shown in FIGS. 3A to 3C, and the full-wave rectified voltage Vr (FIG. 3A) obtained by full-wave rectifying the AC voltage is applied to the resistors R1, R2, and R3. The voltage is divided by a series circuit, and the voltage at the connection point between the resistors R1 and R2 becomes a full-wave rectified waveform having a larger amplitude than the voltage at the connection point between the resistors R2 and R3 due to the difference in voltage division ratio.

  The transistors Q1 and Q2 are turned on when a current flows between the bases and emitters, and the zero cross detection signals A1 and A2 become L level. When no current flows between the bases and emitters, the transistors Q1 and Q2 are turned off. The signals A1 and A2 are at the H level, and when the zero cross is detected, the zero cross detection signals A1 and A2 are inverted to the H level. In this embodiment, zero-cross detection signals A1 and A2 having the same polarity with different rising timings and falling timings and different change widths due to the difference in amplitude of voltages applied to the bases of the transistors Q1 and Q2 (FIG. 3). (B) (c)) can be obtained.

  Here, as shown in FIGS. 4 (a) to 4 (c), when noise Vra such that noise enters the power supply and the waveform of the full-wave rectified voltage Vr is lost occurs at time t1, each zero-cross detection signal A1, Pulse noises A1a and A2a having the same polarity are generated at the same timing (time t1) in both A2. On the other hand, when normal, the zero-cross detection signal A2 rises at time t3 after the zero-cross detection signal A1 rises at time t2. That is, since the normal zero cross detection signals A1 and A2 have different rising timings, the control unit 4 can determine that all pulse waveforms generated simultaneously in the zero cross detection signals A1 and A2 are noise.

  Next, the zero cross detection operation in the control unit 4 will be described using the flowchart of FIG. When the execution of the zero cross detection is started (step S1), first, the rising edge of the zero cross detection signal A1 is monitored (step S2). When the rising edge of the zero cross detection signal A1 is detected, it is determined whether the zero cross detection signals A1 and A2 have risen simultaneously. Judgment is made (step S3).

  If the zero-cross detection signals A1 and A2 rise simultaneously, it is determined that the noise is present, and the process returns to step S2. If the zero-cross detection signals A1 and A2 do not rise at the same time, the rising edge of the zero-cross detection signal A2 is monitored (step S4), and the rising edge of the zero-cross detection signal A2 is used as a counter start trigger (step S5).

  Then, as shown in FIG. 4 (d), the elapsed time from the rising timing t3 of the zero cross detection signal A2 is counted by a counter, the control signal B is inverted to L level after the time T1 has passed, and the control signal B is passed after the time T2 has passed. Is inverted to H level. The dimming circuit 1 supplies the lighting power from the AC power supply AC to the lighting load 2 while the control signal B is at the L level, and performs dimming.

  In this way, in the case of noise that lacks the power supply waveform, pulse noise is generated in the detection signal, but the effect of this pulse noise is completely eliminated regardless of the magnitude of the noise, and the counter starts and normal control signal is generated. Can be generated. Also, in terms of circuit, only two resistors and one transistor are added to the conventional zero-cross detection unit shown in FIG. 21, and it can be configured in a very space-saving and low-cost manner. Processing can also be performed with a simple algorithm.

(Embodiment 2)
The configuration of the illumination device X of the present embodiment is shown in FIG.

  FIG. 6 shows the configuration of the zero-cross detection unit 3 of the present embodiment, and includes a rectifier DB that rectifies the output of the AC power supply AC, a series circuit of resistors R1 and R3 connected between rectified output terminals of the rectifier DB, and a resistor An NPN transistor Q1 having a base connected to a connection point between R1 and R3, a PNP transistor Q3 having a base connected to a connection point between resistors R1 and R3, and a control voltage and a collector of the transistor Q1 A resistor R4, and a resistor R5 connected between the control voltage and the emitter of the transistor Q3. The emitter of the transistor Q1, the collector of the transistor Q3, and the low-voltage side rectified output of the rectifier DB are connected to the ground level. The collector potential and the emitter potential of the transistor Q3 are output as zero cross detection signals A1 and A2.

  7A to 7C show operation waveforms of the respective parts of the zero-cross detection unit 3, and a full-wave rectified voltage Vr (FIG. 7A) obtained by full-wave rectifying an AC voltage is a series circuit of resistors R1 and R3. Divide pressure with.

  The transistor Q1 is turned on when a current flows between the base and the emitter, and the zero cross detection signal A1 becomes L level. If no current flows between the base and the emitter, the transistor Q1 is turned off and the zero cross detection signal A1 becomes the H level. At the time of zero cross detection, the zero cross detection signal A1 is inverted to H level. The transistor Q3 is turned on when the current flows between the emitter and the base, and the zero cross detection signal A2 becomes L level. When the current does not flow between the emitter and the base, the transistor Q3 is turned off and the zero cross detection signal A2 becomes the H level. Sometimes the zero cross detection signal A2 is inverted to L level. In the present embodiment, the voltages applied to the bases of the transistors Q1 and Q2 are the same voltage. The rising timing of the zero-cross detection signal A1, the falling timing of the zero-cross detection signal A2, and the falling timing of the zero-cross detection signal A1 The rising timings of the zero-cross detection signals A2 are the same, and the zero-cross detection signals A1 and A2 (FIGS. 7B and 7C) having the same change width and different polarities can be obtained.

  Here, when positive and negative noise N enters the signal line of the zero cross detection signal regardless of the power waveform, if positive noise enters when the zero cross detection signal is at L level, it appears as pulse noise, but the zero cross detection signal In the case of negative noise, pulse noise is generated if the zero cross detection signal is H level, but if the zero cross detection signal is L level, it is not affected. There is no.

  For example, as shown in FIGS. 8A to 8C, when positive noise Na enters at time t11, pulse noise A1a occurs only at zero-cross detection signal A1, and negative noise Nb enters at time t13. When pulse noise A1b occurs only in the zero-cross detection signal A1 and negative noise Nc enters at time t14, pulse noise A2c occurs only in the zero-cross detection signal A2, and positive noise Nd enters at time t15 Causes the pulse noise A2d only in the zero-cross detection signal A2. On the other hand, when normal, the rise of the zero-cross detection signal A1 and the fall of the zero-cross detection signal A2 occur simultaneously at time t12. That is, since the rising timings of the normal zero-cross detection signals A1 and A2 coincide with each other, the control unit 4 can determine that all the pulse waveforms generated in only one of the zero-cross detection signals A1 and A2 are noise. .

  Next, the zero cross detection operation in the control unit 4 will be described using the flowchart of FIG. When the execution of zero cross detection is started (step S11), first, the rise of the zero cross detection signal A1 is monitored (step S12). When the rise of the zero cross detection signal A1 is detected, the zero cross detection signal A2 falls simultaneously with the zero cross detection signal A1. It is determined whether or not (step S13).

  If the zero-cross detection signal A2 does not fall simultaneously with the zero-cross detection signal A1, it is determined that the noise is detected, and the process returns to step S12. When the zero-cross detection signal A2 falls simultaneously with the zero-cross detection signal A1, the rising edge of the zero-cross detection signal A1 is set as a counter start trigger (step S14).

  Then, as shown in FIG. 8D, the elapsed time from the rising timing t12 of the zero cross detection signal A1 is counted by a counter, the control signal B is inverted to the L level after the time T11 has passed, and the control signal B has been passed after the time T12 has passed. Is inverted to H level. The dimming circuit 1 supplies the lighting power from the AC power supply AC to the lighting load 2 while the control signal B is at the L level, and performs dimming.

  In this way, when positive or negative noise enters the signal line of the zero cross detection signal, pulse noise is generated in the detection signal. The influence of this pulse noise is completely eliminated regardless of the noise level, and the counter Start and generate a normal control signal. Further, in terms of circuit, only one resistor and one transistor are added to the conventional zero-cross detection unit shown in FIG. Processing can also be performed with a simple algorithm.

(Embodiment 3)
The configuration of the illumination device X of the present embodiment is shown in FIG.

  FIG. 10 shows a configuration of the zero-cross detection unit 3 of the present embodiment, and includes a rectifier DB that rectifies the output of the AC power supply AC, and a series circuit of resistors R1, R2, and R3 connected between rectification output terminals of the rectifier DB. NPN transistor Q1 having a base connected to the connection point of resistors R1 and R2, PNP transistor Q3 having a base connected to the connection point of resistors R2 and R3, and between the control voltage and the collector of transistor Q1 A resistor R4 connected, and a resistor R5 connected between the control voltage and the emitter of the transistor Q3. The emitter of the transistor Q1, the collector of the transistor Q3, and the low-voltage side rectified output of the rectifier DB are connected to the ground level. The collector potential of Q1 and the emitter potential of transistor Q3 are output as zero cross detection signals A1 and A2.

  The operation waveforms of the respective parts of the zero-cross detection unit 3 are shown in FIGS. 11A to 11C, and the full-wave rectified voltage Vr (FIG. 11A) obtained by full-wave rectifying the AC voltage is applied to the resistors R1, R2, and R3. The voltage is divided by a series circuit, and the voltage at the connection point between the resistors R1 and R2 becomes a full-wave rectified waveform having a larger amplitude than the voltage at the connection point between the resistors R2 and R3 due to the difference in voltage division ratio.

  The transistor Q1 is turned on when a current flows between the base and the emitter, and the zero cross detection signal A1 becomes L level. If no current flows between the base and the emitter, the transistor Q1 is turned off and the zero cross detection signal A1 becomes the H level. At the time of zero cross detection, the zero cross detection signal A1 is inverted to H level. The transistor Q2 is turned on when the current flows between the emitter and the base, and the zero cross detection signal A2 becomes L level. When the current does not flow between the emitter and the base, the transistor Q2 is turned off and the zero cross detection signal A2 becomes the H level. Sometimes the zero cross detection signal A2 is inverted to L level. In the present embodiment, zero-cross detection signals A1 and A2 having different rising timings and falling timings and different change widths and polarities due to differences in amplitudes of voltages applied to the bases of the transistors Q1 and Q2 (FIG. 11 ( b) (c)) can be obtained.

  Here, when positive and negative noise N enters the signal line of the zero cross detection signal regardless of the power waveform, if positive noise enters when the zero cross detection signal is at L level, it appears as pulse noise, but the zero cross detection signal In the case of negative noise, pulse noise is generated if the zero cross detection signal is H level, but if the zero cross detection signal is L level, it is not affected. There is no.

  For example, as shown in FIGS. 12A to 12D, when negative noise Na enters at time t21, pulse noise A2a occurs only at zero cross detection signal A2, and positive noise Nb enters at time t22. Causes pulse noise A1b only in the zero-cross detection signal A1.

  Further, when noise Vrc protruding into the waveform of the full-wave rectified voltage Vr is generated at time t24 due to noise entering the power supply, pulse noise A1c is generated only in the zero-cross detection signal A1, and the waveform of the full-wave rectified voltage Vr is generated. Is generated at time t25, pulse noise A2d is generated only at zero cross detection signal A2, and when noise Vre is generated at time t27, pulse noise A1e, A2e is generated at both zero cross detection signals A1, A2. Will occur.

  That is, in the case of normal zero-cross detection signals A1 and A2, the zero-cross detection signal A2 rises after the zero-cross detection signal A1 rises, but when noise enters the power supply or the signal line of the zero-cross detection signal The rise of the zero-cross detection signal A1 and the fall of the zero-cross detection signal A2 occur at the same time, or after the zero-cross detection signal A1 rises, the fall of the zero-cross detection signal A1 or the rise of the zero-cross detection signal A2 occurs. Yes.

  Therefore, in the present embodiment, in the case of the normal zero-cross detection signals A1 and A2, the zero-cross detection signals A1 and A2 and noise are utilized by utilizing the fact that the zero-cross detection signal A2 falls after the zero-cross detection signal A1 rises. Is identified. Hereinafter, the zero cross detection operation in the control unit 4 will be described with reference to the flowchart of FIG. When the execution of zero cross detection is started (step S21), first, the rise of the zero cross detection signal A1 is monitored (step S22). When the rise of the zero cross detection signal A1 is detected, the zero cross detection signal A2 is simultaneously detected with the rise of the zero cross detection signal A1. It is determined whether or not it has fallen (step S23).

  If the zero-cross detection signal A2 falls simultaneously with the rise of the zero-cross detection signal A1, it is determined as noise and the process returns to step S22.

  If the rising edge of the zero cross detection signal A1 and the falling edge of the zero cross detection signal A2 are not simultaneous, the falling edge of the zero cross detection signal A1 is monitored (step S24). If the falling edge of the zero cross detection signal A1 is detected, noise is detected. It judges that there is, and returns to step S22. If the falling edge of the zero-cross detection signal A1 is not detected, the rising edge of the zero-crossing detection signal A2 is monitored (step S25). If the rising edge of the zero-cross detection signal A2 is detected, it is determined as noise and the process returns to step S22. If the rising edge of the zero-cross detection signal A2 is not detected, the falling edge of the zero-cross detection signal A2 is monitored (step S26), and the falling edge of the zero-cross detection signal A2 is used as a counter start trigger (step S27).

  Then, as shown in FIG. 12 (e), after the zero cross detection signal A1 rises at time t23, the elapsed time from the falling timing t26 of the zero cross detection signal A2 is counted by a counter, and the control signal B is sent after the time T21 has passed. The control signal B is inverted to the H level after the time T22 has elapsed. The dimming circuit 1 supplies the lighting power from the AC power supply AC to the lighting load 2 while the control signal B is at the L level, and performs dimming.

  In this way, if noise enters the power line or the signal line of the zero-cross detection signal, pulse noise will be generated in the detection signal. The effect of this pulse noise is completely eliminated regardless of the noise level, and the counter starts. A normal control signal can be generated. Also, in terms of circuit, only two resistors and one transistor are added to the conventional zero-cross detection unit shown in FIG. Processing can also be performed with a simple algorithm.

(Embodiment 4)
In the first to third embodiments, when the control unit 4 is configured by a microcomputer or the like and the zero cross detection signal is read by the microcomputer or the like, not only noise detection based on the waveform of the detection signal but also a timer is used. The identification accuracy can be improved.

  For example, in the first embodiment, when the time difference Tm (see FIG. 3) of each rising edge between the normal zero-crossing detection signal A1 and the zero-crossing detection signal A2 is set to 1 ms, the rising edge of the zero-crossing detection signal A1 is detected. If the time until the rising edge of the zero-cross detection signal A2 is detected is less than 1 ms, it can be said that the detected signal is noise.

  Hereinafter, the zero cross detection operation in the control unit 4 will be described with reference to the flowchart of FIG. When the execution of the zero cross detection is started (step S31), first, the rising edge of the zero cross detection signal A1 is monitored (step S32), and when the rising edge of the zero cross detection signal A1 is detected, it is determined whether the zero cross detection signals A1 and A2 are simultaneously raised. Judgment is made (step S33).

  If the zero-cross detection signals A1 and A2 rise simultaneously, it is determined that the noise is present, and the process returns to step S32. If the zero cross detection signals A1 and A2 do not rise at the same time, the timer starts counting (step S34), monitors the rise of the zero cross detection signal A2 (step S35), and detects the rise of the zero cross detection signal A2. When the time measured by the timer is less than 1 ms, it is determined that the noise is present, and the process returns to step S35. If the timer timing is not less than 1 ms, the timer timing operation is stopped (step S37), and the rising edge of the zero-cross detection signal A2 is used as a counter start trigger (step S38).

  Then, similarly to the first to third embodiments, the control signal B is generated and the dimming control is performed.

(Embodiment 5)
In the fourth embodiment, the time measured by the timer from the rise of the zero cross detection signal A1 to the rise of the zero cross detection signal A2 may exceed 1 ms. Even in such a case, the rising edge of the zero cross detection signal A2 is used as a trigger for counter start in the fourth embodiment. However, in this embodiment, the rising edge of the zero cross detection signal A2 is started as a counter when the time measured by the timer is 1 ms. If the measured time exceeds 1 ms, the falling edge of the zero cross detection signal A2 is set as a counter start trigger.

  Hereinafter, the zero cross detection operation in the control unit 4 will be described with reference to the flowchart of FIG. Steps S41 to S45 are the same as steps S31 to S35 of FIG. When the rising edge of the zero-cross detection signal A2 is detected in step S45, the timer time is determined (step S46). If the timer time is less than 1 ms, it is determined that the noise is detected, and the process returns to step S45. .

  If the timer time is 1 ms, the timer operation is stopped (step S47), and the rising edge of the zero-cross detection signal A2 is used as a counter start trigger (step S48). Then, as shown in FIGS. 16A and 16B, the elapsed time from the rising timing t32 of the zero cross detection signal A2 is counted by a counter, the control signal B is inverted to the L level after the time T31 has elapsed, and after the time T32 has elapsed. The control signal B is inverted to H level.

  If the timer time exceeds 1 ms, the timer operation is stopped (step S49), and the falling edge of the zero-cross detection signal A2 is used as a counter start trigger (step S50). Then, as shown in FIGS. 16 (a) and 16 (b), the elapsed time from the falling timing t31 of the zero cross detection signal A2 is counted by the counter, and the control signal B is inverted to the L level after the time T33 has elapsed, and the time T34 has elapsed. Later, the control signal B is inverted to H level.

  In order to obtain the time T33, a time T35 from the fall (time t31) to the rise (time t32) of the zero cross detection signal A2 may be added to the time T31. In order to obtain the time T34, The time T35 may be added to the time T32.

(Embodiment 6)
The configuration of the illumination device X of the present embodiment is shown in FIG.

  FIG. 17 shows the configuration of the zero-cross detection unit 3 of the present embodiment, and includes a rectifier DB that rectifies the output of the AC power supply AC, and a series circuit of resistors R11, R12, and R13 connected between the rectification output terminals of the rectifier DB. The base is connected to the connection point of the PNP transistor Q11 having the base connected to the connection point of the resistors R11 and R12, the NPN transistor Q12 having the base connected to the connection point of the resistors R11 and R12, and the connection point of the resistors R12 and R13. NPN transistor Q13, a resistor R14 connected between the control voltage and the emitter of transistor Q11, a resistor R15 connected between the control voltage and the collector of transistor Q12, a control voltage and the collector of transistor Q13 And a resistor R16 connected between the collector of the transistor Q11, transistors Q12, Q13 Low-voltage side rectification output of the emitter and the rectifier DB is connected to the ground level and outputs the emitter potential of transistors Q11, the collector potential of the transistor Q12, Q13 as the zero-cross detection signal A1, A2, A3.

  Then, the full-wave rectified voltage Vr obtained by full-wave rectifying the AC voltage is divided by a series circuit of resistors R11, R12, and R13, and the voltage at the connection point between the resistors R11 and R12 is determined by the difference in voltage division ratio. The full-wave rectified waveform has a larger amplitude than the voltage.

  18A to 18C show the operation waveforms of the respective parts of the zero cross detector 3, and the transistor Q11 is turned on when a current flows between the emitter and the base, and the zero cross detection signal A1 becomes L level. If no current flows between the emitter and the base, it is turned off and the zero-cross detection signal A1 becomes H level. At the time of zero-cross detection, the zero-cross detection signal A1 is inverted to L level. The transistors Q12 and Q13 are turned on when a current flows between the base and the emitter, and the zero cross detection signals A2 and A3 become L level. When no current flows between the base and the emitter, the transistors Q12 and Q13 are turned off and the zero cross detection signals A2 and A3 are turned on. When the zero cross is detected, the zero cross detection signals A2 and A3 are inverted to the H level. In the present embodiment, the voltages applied to the bases of the transistors Q11 and Q12 are the same voltage. The rising timing of the zero-cross detection signal A1, the falling timing of the zero-cross detection signal A2, and the falling timing of the zero-cross detection signal A1 The rising timings of the zero-cross detection signals A2 are the same, and the zero-cross detection signals A1 and A2 (FIGS. 18A and 18B) having the same change width and different polarities can be obtained. Further, the zero-cross detection signals A1, A3 having different rising timings and falling timings and different change widths and polarities in the transistors Q11 and Q13 due to the difference in amplitude of the voltages applied to the bases of the transistors Q11 and Q13. (FIGS. 18A and 18C) can be obtained.

  Hereinafter, the zero cross detection operation in the control unit 4 will be described with reference to the flowchart of FIG. When the execution of zero cross detection is started (step S61), first, the rise of the zero cross detection signal A2 is monitored (step S62). When the rise of the zero cross detection signal A1 is detected, the zero cross detection signal A1 is simultaneously detected with the rise of the zero cross detection signal A2. It is determined whether or not it has fallen (step S63).

  If the zero-cross detection signal A1 does not fall simultaneously with the rise of the zero-cross detection signal A2, it is determined as noise and the process returns to step S62. If the rise of the zero cross detection signal A2 and the fall of the zero cross detection signal A1 are simultaneous, it is determined whether or not the zero cross detection signal A3 has changed simultaneously with the rise of the zero cross detection signal A2 (step S64). If the zero-cross detection signal A3 changes simultaneously with the rise of the zero-cross detection signal A2, it is determined as noise and the process returns to step S62.

  If the zero cross detection signal A3 does not change simultaneously with the rise of the zero cross detection signal A2, the rise of the zero cross detection signal A3 is monitored (step S65). If the rise of the zero cross detection signal A3 is detected, the rise of the zero cross detection signal A3 is detected. At the same time, it is determined whether or not the zero cross detection signal A1 has changed (step S66).

  If the zero-cross detection signal A1 changes simultaneously with the rise of the zero-cross detection signal A3, it is determined as noise and the process returns to step S62. If the zero cross detection signal A1 does not change simultaneously with the rise of the zero cross detection signal A3, it is determined whether or not the zero cross detection signal A2 has changed simultaneously with the rise of the zero cross detection signal A3 (step S67). If the zero-cross detection signal A2 changes simultaneously with the rise of the zero-cross detection signal A3, it is determined as noise and the process returns to step S62.

  If the zero-cross detection signal A2 does not change simultaneously with the rise of the zero-cross detection signal A3, the rising edge of the zero-cross detection signal A3 is set as a counter start trigger (step S68).

  Then, the elapsed time from the rising timing of the zero-cross detection signal A3 is counted by a counter, the control signal B is inverted to L level after a predetermined time has elapsed, and the control signal B is inverted to H level after the predetermined time has elapsed. The dimming circuit 1 supplies the lighting power from the AC power supply AC to the lighting load 2 while the control signal B is at the L level, and performs dimming.

  In this way, noise elimination accuracy can be further increased by providing three systems of zero-cross detection means.

It is a block diagram which shows the illuminating device of Embodiment 1 of this invention. It is a block diagram which shows a zero cross detection part same as the above. (A)-(c) It is a wave form diagram which shows operation | movement of each part of a zero cross detection part same as the above. (A)-(d) It is a wave form diagram which shows operation | movement of each part at the time of noise generation same as the above. It is a flowchart figure which shows zero cross detection operation same as the above. It is a block diagram which shows the zero crossing detection part of Embodiment 2 of this invention. (A)-(c) It is a wave form diagram which shows operation | movement of each part of a zero cross detection part same as the above. (A)-(d) It is a wave form diagram which shows operation | movement of each part at the time of noise generation same as the above. It is a flowchart figure which shows zero cross detection operation same as the above. It is a block diagram which shows the zero cross detection part of Embodiment 3 of this invention. (A)-(c) It is a wave form diagram which shows operation | movement of each part of a zero cross detection part same as the above. (A)-(e) It is a wave form diagram which shows operation | movement of each part at the time of noise generation same as the above. It is a flowchart figure which shows zero cross detection operation same as the above. It is a flowchart figure which shows the zero cross detection operation | movement of Embodiment 4 of this invention. It is a flowchart figure which shows the zero cross detection operation | movement of Embodiment 5 of this invention. (A) (b) It is a wave form diagram which shows timer start operation | movement same as the above. It is a block diagram which shows the zero cross detection part of Embodiment 6 of this invention. (A)-(c) It is a wave form diagram which shows operation | movement of each part of a zero cross detection part same as the above. It is a flowchart figure which shows zero cross detection operation same as the above. (A)-(c) It is a wave form diagram which shows the operation | movement at the time of the conventional phase control. It is a block diagram which shows the conventional zero cross detection part. (A)-(c) It is a wave form diagram which shows the conventional zero cross detection operation | movement. (A)-(c) It is a wave form diagram which shows the zero cross detection operation | movement at the time of the noise generation in the past. It is a figure which shows the conventional noise removal method. (A) (b) It is a figure which shows the waveform of the zero cross detection signal at the time of the conventional noise removal.

Explanation of symbols

X lighting device 1 dimming circuit 2 lighting load 3 zero cross detection unit 4 control unit 31 to 3N zero cross detection means AC AC power supply

Claims (4)

Zero cross detection unit provided with multiple zero cross detection means to detect the zero cross of the power supply voltage of the AC power supply and the lighting load, and the zero cross detection signal and noise due to the difference in each output waveform of the multiple zero cross detection means And a dimming circuit for dimming the illumination load based on the control signal. The plurality of zero-cross detection means each output a zero-cross detection signal whose signal levels at the time of zero-cross detection are inverted to the same polarity and whose width at the time of inversion is different from any of the other zero-cross detection means. The lighting device according to claim 1. The plurality of zero-cross detection means each outputs a zero-cross detection signal whose signal level at the time of zero-cross detection is inverted to a polarity different from that of any other zero-cross detection means and whose width at the time of inversion is the same as each other. The lighting device according to claim 1. The plurality of zero-cross detection means have a zero-cross detection signal in which the signal level at the time of zero-cross detection is inverted to a polarity different from that of any other zero-cross detection means, and the width at the time of inversion is different from that of any other zero-cross detection means The illuminating device according to claim 1, wherein each of the lighting devices is output.

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