JP2016070831A - Power failure detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power failure detection circuit capable of detecting a power failure of an AC power source in a short period of time.SOLUTION: A power failure detection circuit comprises: a first timer circuit (12-1) that outputs a power source abnormality signal indicating that an AC power source is in an abnormal state, when a first time where a first state is maintained has passed a predetermined period since a point in time when entering the first state where an electric potential of a first terminal (2-1) of the AC power source (2) is higher than an electric potential of a second terminal (2-2) of the AC power source; a first phase inversion detection circuit (13-1) that resets the first time to 0 when the electric potential of the second terminal becomes higher than the electric potential of the first terminal; a second timer circuit (12-2) that outputs a power source abnormality signal when a second time where a second state is maintained has passed a predetermined period since a point in time when entering the second state where the electric potential of the second terminal is higher than the electric potential of the first terminal; and a second phase inversion detection circuit (13-2) that resets the second time to 0 when the electric potential of the first terminal becomes higher than the electric potential of the second terminal.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a power failure detection circuit that detects a power failure of an AC power supply.

  Conventionally, techniques for detecting a power failure of an AC power supply have been proposed (see, for example, Patent Documents 1 to 3).

  For example, Patent Document 1 discloses a circuit that detects a power failure according to a DC voltage obtained by converting a voltage supplied from an AC power source into a DC by a rectifier and smoothing the voltage with a smoothing capacitor.

The power supply abnormality detection device disclosed in Patent Document 2 converts the voltage of the commercial power supply into a pulse width, and determines that the power supply is abnormal when the pulse width exceeds a specified value range.
Furthermore, in the current regulator disclosed in Patent Document 3, a power failure detection circuit in which a reference terminal is connected between a current transformer connected to a commercial power source and a load circuit is based on a voltage applied to the reference terminal. Determine whether a power failure occurred.

Japanese Patent Laid-Open No. 10-134279 JP 2000-339233 A JP 2002-112462 A

  However, a capacitor may be connected to a circuit that supplies power from the AC power supply to the load circuit in order to smooth the voltage or reduce noise. In such a case, when the AC power supply fails, the capacitor is discharged, and the change in the voltage applied to the circuit that detects the power failure becomes gradual, and it may take time from the occurrence of the power failure to the detection of the power failure. was there.

  Then, an object of this invention is to provide the power failure detection circuit which can shorten the time which detection of the power failure of AC power supply is required.

  As one aspect of the present invention, a power failure detection circuit is provided. This power failure detection circuit is connected to a first terminal of an AC power supply having a first terminal and a second terminal, and from the time when the potential of the first terminal is in a first state higher than the reference potential. A first timer circuit that outputs a power supply abnormality signal indicating that an abnormality has occurred in the AC power supply when the first time during which the first state is maintained exceeds a first predetermined period; Connected to the second terminal, connected to the first phase inversion detection circuit that resets the first time to 0 when the potential of the second terminal becomes higher than the reference potential, and the second terminal of the AC power supply; From the time when the potential of the second terminal becomes the second state higher than the reference potential, a power failure signal is output when the second time during which the second state is maintained exceeds the second predetermined period. Connected to the first timer terminal and the first terminal of the AC power supply. There and having a second phase inversion detecting circuit becomes higher than the reference potential the second time is reset to zero.

  In this power failure detection circuit, it is preferable that the first predetermined period and the second predetermined period are periods from 1/2 of the cycle of the AC voltage to 3 times the cycle of the AC voltage.

In the power failure detection circuit, the first timer circuit includes a first switching element whose control terminal is connected to the first terminal, and a capacitor whose one end is connected to the constant voltage source via the first switching element. And a second switching element having a control terminal connected to one end of the capacitor, one terminal connected to the output terminal of the power failure detection circuit, and the other terminal grounded. In this case, the first phase inversion detection circuit includes a third switching element having a control terminal connected to the second terminal, one terminal connected to one end of the capacitor, and the other terminal grounded. It is preferable to have.
In this case, during the first time, the first switching element is turned on to charge the capacitor, and when the first time has passed the first predetermined period, the second switching element is turned on to output. When the power supply abnormality signal is output from the terminal and the potential of the second terminal becomes higher than the reference potential before the first time reaches the first predetermined period, the third switching element is turned on. Preferably, the capacitor is discharged and the first time is reset to zero.

  Further, the power failure detection circuit is connected to the first terminal and the second terminal, and both the voltage of the first terminal and the voltage of the second terminal are 1 of the cycle of the AC voltage supplied from the AC power source. It is preferable to further include a voltage drop detection circuit that outputs a power supply abnormality signal when the predetermined voltage is not reached over a third predetermined period longer than / 2.

  The power failure detection circuit according to the present invention has an effect that the time required for detecting a power failure of the AC power supply can be shortened.

It is a circuit diagram of a power failure detection circuit according to one embodiment of the present invention. It is a figure which shows the time change of the voltage of each part of a power failure detection circuit in case an alternating current power supply is operating normally. It is a figure which shows the time change of the voltage of each part of a power failure detection circuit at the time of AC power failure.

  Hereinafter, a power failure detection circuit according to an embodiment of the present invention will be described with reference to the drawings. This power failure detection circuit checks whether or not the phase inversion of the voltage supplied from the AC power supply is in accordance with the AC cycle, and if the phase does not invert even after the period assumed in accordance with the AC cycle, the AC By detecting a power failure, the time required to detect a power failure is reduced.

  FIG. 1 is a circuit diagram of a power failure detection circuit according to one embodiment of the present invention. As shown in FIG. 1, the power failure detection circuit 1 includes a voltage drop detection circuit 11, a first timer circuit 12-1, a second timer circuit 12-2, and a first phase inversion detection circuit 13-1. And a second phase inversion detection circuit 13-2. The power failure detection circuit 1 converts the AC voltage supplied from the AC power source 2 into a DC voltage to the first terminal 2-1 and the second terminal 2-2 of the AC power source 2 and converts the DC voltage to the DC voltage. It is connected in parallel with a rectifier circuit 3 that supplies a load circuit (not shown). The power failure detection circuit 1 detects a power failure of the AC power source 2 or outputs a signal indicating a power source abnormality from the trigger terminal 14 when the amplitude of the AC voltage supplied from the AC power source 2 becomes a predetermined value or less. The trigger terminal 14 is connected to, for example, a control circuit (not shown) of a device having a load circuit driven by power supplied from the AC power supply 2 via the rectifier circuit 3, and the trigger terminal 14 receives a signal from the trigger terminal 14. The device is notified that a power supply abnormality has occurred in the AC power supply 2.

  In the present embodiment, when the signal output from the trigger terminal 14 indicates a power supply abnormality, the output voltage of the trigger terminal 14 is relatively low, while the signal output from the trigger terminal 14 indicates that the AC power supply 2 is operating normally. In this case, the output voltage of the trigger terminal 14 is relatively high.

  In the following, for the sake of convenience, the potential of the first terminal 2-1 is equal to the potential of the second terminal 2-2, and the potential of the first terminal 2-1 is thereafter set to the second terminal 2-2. The phase of the AC voltage supplied from the AC power source 2 at the time when the potential becomes higher than the potential is set to 0 °. That is, if the potential of the first terminal 2-1 is higher than the potential of the second terminal 2-2, the phase of the AC voltage supplied from the AC power supply 2 is included in the range of 0 ° to 180 °. When the potential difference is maximum, the phase is 90 °. Conversely, if the potential of the second terminal 2-2 is higher than the potential of the first terminal 2-1, the phase of the AC voltage supplied from the AC power supply 2 is included in the range of 180 ° to 360 °. When the potential difference is maximum, the phase is 270 °. For convenience, when the phase of the AC voltage is included in 0 ° to 180 °, the voltage and its phase are positive. When the phase of the AC voltage is included in 180 ° to 360 °, the voltage and its phase are negative. Suppose that

  The voltage drop detection circuit 11 outputs a signal indicating a power supply abnormality to the trigger terminal 14 when the AC voltage supplied from the AC power supply 2 becomes equal to or lower than a predetermined threshold voltage over a predetermined period (third predetermined period). Let For this purpose, the voltage drop detection circuit 11 includes two diodes D1 and D2, a Zener diode ZD1, two NPN bipolar transistors (hereinafter simply referred to as transistors) TR1 and TR2, and a capacitor C1.

  The anode terminal of the diode D1 is connected to the first terminal 2-1 of the AC power supply 2, and the anode terminal of the diode D2 is connected to the second terminal 2-2 of the AC power supply 2. The cathode terminals of the two diodes D1 and D2 are connected to the cathode terminal of the Zener diode ZD1. The anode terminal of the Zener diode ZD1 is connected to the base terminal of the transistor TR1 that is a switching element via the resistor R1. The base terminal is an example of a control terminal to which a signal for switching on / off of the switching element is input. The collector terminal of the transistor TR1 is connected to the constant voltage source Vcc via the resistor R2. On the other hand, the emitter terminal of the transistor TR1 is grounded.

  Furthermore, one end on the positive side of the capacitor C1 is also connected to the constant voltage source Vcc via the resistor R2, and one end on the positive side is connected to the base terminal of the transistor TR2 as a switching element via the resistor R3. The On the other hand, the other end on the negative electrode side of the capacitor C1 is grounded.

  The collector terminal of the transistor TR2 is connected to the constant voltage source Vcc via the resistor R4 and to the trigger terminal 14. On the other hand, the emitter terminal of the transistor TR2 is grounded.

Hereinafter, the operation of the voltage drop detection circuit 11 will be described.
When the voltage of either the first terminal 2-1 or the second terminal 2-2 of the AC power supply 2 is higher than the Zener voltage of the Zener diode ZD1, a current flows through the base terminal of the transistor TR1, and the transistor TR1 is turned on. It becomes. Therefore, no current flows through the base terminal of the transistor TR2, and the transistor TR2 is turned off. Therefore, the voltage of the trigger terminal 14 becomes a relatively high value corresponding to the voltage supplied from the constant voltage source Vcc. That is, the trigger terminal 14 outputs a signal indicating that the AC power supply 2 is operating normally. This Zener voltage is an example of the above threshold voltage, and for example, the minimum value of the amplitude of the AC voltage that can obtain a voltage at which the load circuit can operate normally, for example, 1 / of the rated voltage of the AC power supply 2. Set to 5 to 1/2.

  On the other hand, when the voltage at both the first terminal 2-1 and the second terminal 2-2 of the AC power supply 2 is lower than the Zener voltage of the Zener diode ZD1, no current flows through the base terminal of the transistor TR1, and the transistor TR1. Is turned off, the capacitor C1 is charged by the voltage from the constant voltage source Vcc. Until the delay period in which the amount of charge of the capacitor C1 reaches a certain value elapses, no current flows through the base terminal of the transistor TR2, and the transistor TR2 remains off. This delay time corresponds to the third predetermined period. Accordingly, the voltage of either the first terminal 2-1 or the second terminal 2-2 is higher than the zener voltage of the zener diode ZD1 before the AC power supply 2 is operating normally and the delay period elapses. The trigger terminal 14 does not output a signal indicating a power supply abnormality.

  However, the amplitude of the AC voltage output from the AC power supply 2 decreases, and the voltage output from either the first terminal 2-1 or the second terminal 2-2 is higher than the Zener voltage of the Zener diode ZD1. If not, the transistor TR1 is not turned on within the delay period, so that a current flows through the base terminal of the transistor TR2 and the transistor TR2 is turned on. As a result, the voltage at the trigger terminal 14 decreases, and a signal indicating power supply abnormality is output from the trigger terminal 14. It should be noted that when the AC power supply 2 is operating normally, the capacitance of the capacitor C1 and the delay time are longer than 1/2 of the AC voltage cycle so that a signal indicating power supply abnormality is not output. The resistance value of the resistor R3 is preferably set. On the other hand, in order to reduce the time required for detecting the AC voltage supplied from the AC power source 2 after the AC voltage has decreased, the capacitance of the capacitor C1 and the capacitor C1 are set so that the delay time is shorter than the cycle of the AC voltage. The resistance value of the resistor R3 is preferably set.

  The first timer circuit 12-1 is in a state in which the voltage is positive from the time when the AC voltage supplied from the AC power supply 2 changes from negative to positive (that is, when the phase of the AC voltage becomes 0 °) ( When the elapsed time maintained in the first state passes a predetermined period (hereinafter referred to as a first predetermined period), a signal indicating a power supply abnormality is output to the trigger terminal 14. In the present embodiment, the time when the AC voltage supplied from the AC power supply 2 changes from negative to positive is the time when the potential of the first terminal 2-1 of the AC power supply 2 becomes higher than the reference potential. Correspond. The reference potential is the ground potential of the power failure detection circuit 1.

  Similarly, the second timer circuit 12-2 has a negative voltage when the AC voltage supplied from the AC power supply 2 changes from positive to negative (that is, when the phase of the AC voltage becomes 180 °). When the elapsed time maintained in this state (second state) passes a predetermined period (hereinafter referred to as a second predetermined period), a signal indicating a power supply abnormality is output to the trigger terminal 14. In the present embodiment, the time when the AC voltage supplied from the AC power supply 2 changes from positive to negative is the time when the potential of the second terminal 2-2 of the AC power supply 2 becomes higher than the reference potential. Correspond.

  When the AC voltage supplied from the AC power supply 2 is inverted from positive to negative (that is, when the phase of the AC voltage becomes 180 °), the first phase inversion detection circuit 13-1 is configured to operate as the first timer circuit 12-1. To reset the elapsed time of the first state. Similarly, when the AC voltage supplied from the AC power supply 2 is inverted from negative to positive (that is, when the phase of the AC voltage becomes 0 °), the second phase inversion detection circuit 13-2 performs the second timer circuit. Reset the elapsed time of the second state according to 12-2.

In the first timer circuit 12-1 and the second timer circuit 12-2, the input terminal of the first timer circuit 12-1 is connected to the first terminal 2-1 of the AC power source 2, respectively. The two timer circuits 12-2 can have the same configuration except that the input terminal of the timer circuit 12-2 is connected to the second terminal 2-2 of the AC power supply 2. Similarly, the first phase inversion detection circuit 13-1 and the second phase inversion detection circuit 13-2 are configured such that the input terminal of the first phase inversion detection circuit 13-1 is the second of the AC power supply 2. The same configuration can be adopted except that it is connected to the terminal 2-2 and the input terminal of the second phase inversion detection circuit 13-2 is connected to the first terminal 2-1 of the AC power supply 2. .
Therefore, hereinafter, the first timer circuit 12-1 and the first phase inversion detection circuit 13-1 will be described.

  The first timer circuit 12-1 includes a diode D3, three bipolar transistors (hereinafter simply referred to as transistors) TR3 to TR5, and a capacitor C2.

  The anode terminal of the diode D3, which is the input terminal of the first timer circuit 12-1, is connected to the first terminal 2-1 of the AC power supply 2, while the cathode terminal is an NPN transistor TR3 via the resistor R5. Connected to the base terminal.

The collector terminal of the transistor TR3 is connected to the constant voltage source Vcc via the resistors R6 and R7, and is further connected to the base terminal of the PNP transistor TR4 via the resistor R7. On the other hand, the emitter terminal of the transistor TR3 is grounded. The emitter terminal of the transistor TR4 is connected to the constant voltage source Vcc, while the collector terminal of the transistor TR4 is connected to one end of the capacitor C2 via the resistor R8. Further, the collector terminal of the transistor TR4 is connected to the base terminal of the NPN transistor TR5 via resistors R8 and R9.
The transistors TR3 and TR4 are an example of a first switching element included in the first timer circuit 12-1.

  As described above, one end of the positive side of the capacitor C2 is connected to the collector terminal of the transistor TR4 and the base terminal of the transistor TR5 via the resistors R8 and R9, and the output of the first phase inversion detection circuit 13-1. Connected to terminal. The other end of the capacitor C2 on the negative electrode side is grounded.

  Furthermore, the collector terminal of the transistor TR5, which is the output terminal of the first timer circuit 12-1, is connected to the trigger terminal 14, while the emitter terminal of the transistor TR5 is grounded. The transistor TR5 is an example of a second switching element included in the first timer circuit 12-1.

  The first phase inversion detection circuit 13-1 includes a diode D4 and an NPN bipolar transistor (hereinafter simply referred to as a transistor) TR6, which is a switching element.

  The anode terminal of the diode D4, which is the input terminal of the first phase inversion detection circuit 13-1, is connected to the second terminal 2-2 of the AC power supply 2, while the cathode terminal of the transistor TR6 is connected via the resistor R10. Connected to the base terminal. The collector terminal of the transistor TR6, which is the output terminal of the first phase inversion detection circuit 13-1, is connected to the positive terminal of the capacitor C2 of the first timer circuit 12-1. On the other hand, the emitter terminal of the transistor TR6 is grounded.

  Hereinafter, operations of the first timer circuit 12-1 and the first phase inversion detection circuit 13-1 will be described.

  When the AC voltage output from the AC power supply 2 changes from negative to positive, the potential of the first terminal 2-1 becomes higher than the ground potential of the power failure detection circuit 1, which is the reference potential, and the first terminal 2-1 Current flows through the diode D3 to the base terminal of the transistor TR3, so that the transistor TR3 is turned on. Therefore, a current also flows through the base terminal of the transistor TR4, and the transistor TR4 is also turned on. As a result, charging of the capacitor C2 is started. The capacitor C2 continues to be charged while the AC voltage is positive. If the elapsed time that the AC voltage has been kept positive after changing from negative to positive exceeds the first predetermined period and the capacitor C2 continues to be charged, current will flow to the base terminal of the transistor TR5. The transistor TR5 is turned on. When the transistor TR5 is turned on, a current flows from the constant voltage source Vcc through the transistor TR5 via the trigger terminal 14, so that the voltage at the trigger terminal 14 decreases and a signal indicating a power supply abnormality is output from the trigger terminal. become.

  On the other hand, as will be described in detail later, if the first timer circuit 12-1 is reset by the first phase inversion detection circuit 13-1 before the elapsed time reaches the first predetermined period, the capacitor C2 Is discharged, the transistor TR5 remains off. When the transistor TR5 is off, the output voltage of the trigger terminal 14 is not relatively lowered by the first timer circuit 12-1.

  Further, since the current does not flow to the base terminal of the transistor TR3 while the AC voltage is negative, the transistor TR3 is turned off. Therefore, no current flows through the base terminal of the transistor TR4, and the transistor TR4 is also turned off. As a result, charging of the capacitor C2 is stopped. For this reason, the transistor TR5 is not turned on unless the transistor TR5 is already turned on.

  Next, for the first phase inversion detection circuit 13-1, while the AC voltage output from the AC power supply 2 is positive, no current flows through the base terminal of the transistor TR6, so the transistor TR6 is turned off. Therefore, the capacitor C2 of the first timer circuit 12-1 is not discharged through the transistor TR6.

  On the other hand, when the AC voltage changes from positive to negative, the potential of the second terminal 2-2 becomes higher than the ground potential of the power failure detection circuit 1, which is the reference potential, and the second terminal 2-2 passes through the diode D4. As a result, current flows through the base terminal of the transistor TR6, and the transistor TR6 is turned off. For this reason, the capacitor C2 of the first timer circuit 12-1 is discharged through the transistor TR6, so that the first timer circuit 12-1 is reset.

  As described above, if the AC power supply 2 is not powered off, the first timer circuit 12-1 is connected to the first timer circuit 12-1 before the first timer circuit 12-1 outputs a signal indicating power supply abnormality to the trigger terminal 14. 1 is reset by the phase inversion detection circuit 13-1, the signal indicating the power supply abnormality is not output from the trigger terminal 14. However, if the AC power supply 2 fails while the AC voltage is positive, the AC voltage does not switch from positive to negative even after the first predetermined period has elapsed, so the first timer circuit 12-1 The first phase inversion detection circuit 13-1 is not reset, and a signal indicating a power supply abnormality is output from the trigger terminal 14 after the first predetermined period has elapsed since the AC voltage was switched from negative to positive.

  Similarly, if the AC power supply 2 fails while the phase of the AC voltage is negative, the AC voltage does not switch from negative to positive even after the second predetermined period has elapsed, so the second timer circuit 12- 2 is not reset by the second phase inversion detection circuit 13-2, and a signal indicating a power supply abnormality is output from the trigger terminal 14.

  Therefore, the power failure detection circuit 1 can detect a power failure when the longer one of the first predetermined period and the second predetermined period has elapsed at the latest after the occurrence of a power failure of the AC power supply 2, and a power failure occurs. This can be notified to the device connected to the trigger terminal 14. Therefore, the device represents a power failure countermeasure (for example, the operating status of the device driven by the power from the AC power source 2) after the AC power source 2 has a power failure until the device itself stops operating. It is possible to increase the time available for storing data in a non-volatile memory.

  In addition, when the AC power supply 2 is operating normally, the first and second predetermined periods are set to be 1/2 or more of the AC voltage cycle so that a signal indicating power supply abnormality is not output. The capacitance of the capacitor C2 and the resistance value of the resistor R9 of the first timer circuit 12-1 and the second timer circuit 12-2 are preferably set. On the other hand, in order to shorten the time required for detecting the AC power supply 2 after a power failure, the capacitance of the capacitor C2 and the capacitor C2 are set so that the first and second predetermined periods are shorter than the AC voltage cycle. The resistance value of the resistor R9 is preferably set. Therefore, for example, the capacitance of the capacitor C2 and the resistance value of the resistor R9 are set so that the first and second predetermined periods are from 1/2 of the period of the AC voltage to 3 times the period of the AC voltage. It is preferable. When the first and second predetermined periods are not more than three times the AC voltage cycle, the power failure detection circuit 1 can detect a power failure in a shorter period than the conventional power failure detection circuit. In particular, the capacitance of the capacitor C2 and the resistance value of the resistor R9 are set such that the first and second predetermined periods are periods obtained by adding a predetermined offset (for example, 0.1 to 1 msec) to 1/2 of the period of the AC voltage. It is preferably set. For example, when the capacitance of the capacitor C2 and the resistance value of the resistor R9 are set so that the first and second predetermined periods are ½ of the cycle of the AC voltage, the power failure detection circuit 1 may be the AC power source 2 at the latest. When a half of the AC voltage cycle has elapsed since the power failure occurred (for example, if the AC voltage cycle is 50 Hz, 10 msec has passed; if the AC voltage cycle is 60 Hz, 8.3 msec. It is possible to detect a power outage when

  FIG. 2 is a diagram illustrating a temporal change in voltage of each part of the power failure detection circuit when the AC power supply is operating normally. In FIG. 2, the horizontal axis represents time, and the vertical axis represents voltage. A waveform 200 represents a time change of the output voltage from the trigger terminal 14. A waveform 201 represents a time change of the voltage at the positive terminal of the capacitor C2 of the first timer circuit 12-1. A waveform 202 represents a time change of the voltage at the positive terminal of the capacitor C2 of the second timer circuit 12-2. Further, a waveform 203 represents a time change of the voltage at the positive terminal of the capacitor C1 of the voltage drop detection circuit 11. A waveform 204 is a waveform of the AC voltage output from the AC power supply 2.

  As the AC voltage changes from negative to positive at time t1, charging of the capacitor C2 of the first timer circuit 12-1 is started, so that as shown in the waveform 201, the first timer circuit 12- The voltage at the positive terminal of the capacitor C2 increases. However, since the AC voltage changes from positive to negative at time t4, the capacitor C2 of the first timer circuit 12-1 is discharged, and the voltage at the positive terminal of the capacitor C2 of the first timer circuit 12-1 is: Before the transistor TR5 of the first timer circuit 12-1 reaches a voltage to turn on, the voltage drops to almost zero. Conversely, as indicated by the waveform 202, the voltage at the positive terminal of the capacitor C2 of the second timer circuit 12-2 starts to rise. However, since the AC voltage changes from negative to positive at time t7, the capacitor C2 of the second timer circuit 12-2 is discharged, and the voltage at the positive terminal of the capacitor C2 of the second timer circuit 12-2 is: The voltage drops to almost zero before reaching the voltage at which the transistor TR5 of the second timer circuit 12-2 is turned on. Such voltage change is repeated at the positive terminal of the capacitor C2 of each timer circuit every cycle of the AC voltage.

  Further, as shown in the waveform 203, since the voltage at both the first terminal 2-1 and the second terminal 2-2 is equal to or lower than the Zener voltage of the Zener diode ZD1 between the time t0 and the time t2, the voltage The voltage at the positive terminal of the capacitor C1 of the drop detection circuit 11 rises. However, since the voltage at the first terminal 2-1 becomes higher than the Zener voltage at the Zener diode ZD1 at time t2, the voltage at the positive terminal of the capacitor C1 does not reach the voltage at which the transistor TR2 is turned on. Decreases until zero. Thereafter, until time t3, the voltage at the first terminal 2-1 is higher than the Zener voltage of the Zener diode ZD1, and therefore the voltage at the positive terminal of the capacitor C1 remains substantially zero.

  After time t3, the voltage at both the first terminal 2-1 and the second terminal 2-2 becomes equal to or lower than the Zener voltage of the Zener diode ZD1, so that the voltage at the positive terminal of the capacitor C1 starts to rise again. However, since the voltage at the second terminal 2-2 becomes higher than the Zener voltage at the Zener diode ZD1 at time t5, the voltage at the positive terminal of the capacitor C1 does not reach the voltage at which the transistor TR2 is turned on. Decreases until zero. Thereafter, until time t6, the voltage at the second terminal 2-2 is higher than the Zener voltage of the Zener diode ZD1, so the voltage at the positive terminal of the capacitor C1 remains substantially zero.

  Thereafter, such a voltage change is repeated at the positive terminal of the capacitor C1 every cycle of the AC voltage. Therefore, as shown in the waveform 200, the output voltage from the trigger terminal 14 is not a voltage indicating a power supply abnormality but is maintained as a voltage indicating that the AC power supply 2 is operating normally.

  FIG. 3 is a diagram illustrating a temporal change in voltage of each part of the power failure detection circuit when the AC power supply fails. In FIG. 3, the horizontal axis represents time, and the vertical axis represents voltage. A waveform 300 represents a time change of the output voltage from the trigger terminal 14. A waveform 301 represents a change over time in the voltage at the positive terminal of the capacitor C2 of the first timer circuit 12-1. A waveform 302 represents a change over time in the voltage at the positive terminal of the capacitor C2 of the second timer circuit 12-2. Further, a waveform 303 represents a time change of the voltage at the positive terminal of the capacitor C1 of the voltage drop detection circuit 11. A waveform 304 is a waveform of an AC voltage output from the AC power supply 2.

  In this example, as shown in the waveform 304, a power failure occurs at time t1, and then the voltage from the AC power supply is positive, that is, the potential of the first terminal 2-1 is the second terminal 2-2. It is constant at a state higher than the potential. Therefore, since charging of the capacitor C2 of the first timer circuit 12-1 is continued, as shown in the waveform 301, the voltage at the positive terminal of the capacitor C2 of the first timer circuit 12-1 continues to rise. At time t2, the voltage reaches the voltage at which the transistor TR5 of the first timer circuit 12-1 is turned on. Therefore, as shown in the waveform 300, it can be seen that the output voltage from the trigger terminal 14 has dropped after time t2, and a power failure has been detected. As shown in the waveform 302, after the time t1, since the potential of the first terminal 2-1 is higher than the potential of the second terminal 2-2, the second timer The voltage at the positive terminal of the capacitor C2 of the circuit 12-2 remains constant at almost zero. Furthermore, since the voltage at the first terminal 2-1 remains higher than the Zener voltage of the Zener diode ZD1 after time t1, the voltage at the positive terminal of the capacitor C1 of the voltage drop detection circuit 11 is almost zero. Will remain.

  As explained above, this power failure detection circuit detects a power failure of the AC power source when the phase of the AC voltage supplied from the AC power source exceeds a predetermined period and does not reverse from positive to negative or negative to positive. To do. For this reason, the power failure detection circuit can quickly detect the occurrence of a power failure even if the voltage change after the power failure occurs moderately due to the influence of a capacitor or the like connected to the AC power supply. This power failure detection circuit can detect a power failure of the AC power supply with a simple circuit configuration. Furthermore, since this power failure detection circuit has a separate circuit for detecting a drop in the AC voltage supplied from the AC power supply, the AC power supply does not stop completely, and it can also be detected that the supplied AC voltage has dropped.

  According to the modification, MOSFETs or other switching elements may be used in each circuit instead of bipolar transistors.

  According to another modification, the first timer circuit may include a comparator, a sampling circuit, and a counter instead of the transistors TR3 and TR4 and the capacitor C2. For example, one input of the comparator is connected to the first terminal 2-1 of the AC power supply 2, and the other input of the comparator is grounded. The comparator outputs a relatively high voltage when the potential of the first terminal 2-1 is higher than the potential of the second terminal 2-2 (that is, the phase of the AC voltage is positive), When the potential of the first terminal 2-1 is lower than the potential of the second terminal 2-2 (that is, the phase of the AC voltage is negative), a relatively low voltage is output. The sampling circuit samples the voltage output from the comparator at a predetermined cycle (for example, 0.1msec to 1msec) shorter than the cycle of the AC voltage, and generates a pulse signal when the output voltage from the comparator is relatively high To do. The output terminal of the sampling circuit is connected to the input terminal of the counter. The counter increments the count value by 1 each time a pulse signal is input from the sampling circuit. The counter turns on the transistor TR5 when the count value exceeds a threshold value corresponding to the number of pulse signals input in a half period of the AC voltage cycle, thereby causing a power supply abnormality from the trigger terminal 14. A representative signal is output.

In this case, the first phase inversion detection circuit 13-1 may also have a comparator instead of the transistor TR6. One input of the comparator is connected to the second terminal 2-2 of the AC power supply 2, and the other input of the comparator is grounded. The comparator outputs a relatively high voltage when the potential of the second terminal 2-2 is higher than the potential of the first terminal 2-1 (that is, the phase of the AC voltage is negative), When the potential of the second terminal 2-2 is lower than the potential of the first terminal 2-1 (that is, the phase of the AC voltage is positive), a relatively low voltage is output. The output from the comparator is input to the reset terminal of the counter. When the comparator outputs a relatively high voltage, the counter is reset. As a result, when the AC power supply 2 is operating normally, it is reset before the count value of the counter reaches the threshold value, thereby preventing the trigger terminal 14 from outputting a signal indicating power supply abnormality. .
The second timer circuit 12-2 and the second phase inversion detection circuit 13-2 may also be configured as in the above modification.

  The power failure detection circuit according to the above-described embodiment or modification may be mounted on a gaming machine such as a ball game machine or a spinning game machine.

  As described above, those skilled in the art can make various modifications in accordance with the embodiment to be implemented within the scope of the present invention.

DESCRIPTION OF SYMBOLS 1 Power failure detection circuit 2 AC power supply 2-1 1st terminal 2-2 2nd terminal 3 Rectifier circuit 11 Voltage drop detection circuit 12-1 1st timer circuit 12-2 2nd timer circuit 13-1 1st Phase inversion detection circuit 13-2 Second phase inversion detection circuit 14 Trigger terminal

Claims (4)

The first terminal is connected to the first terminal of the AC power source having the first terminal and the second terminal, and the first terminal is in a first state in which the potential of the first terminal is higher than the reference potential. A first timer circuit that outputs a power supply abnormality signal indicating that an abnormality has occurred in the AC power supply when a first time during which the state is maintained exceeds a first predetermined period;
A first phase inversion detection circuit that is connected to the second terminal of the AC power supply and resets the first time to 0 when the potential of the second terminal becomes higher than the reference potential;
The second state in which the second state is maintained from the time when the second state is connected to the second terminal of the AC power source and the potential of the second terminal is higher than the reference potential. A second timer circuit for outputting the power abnormality signal when time passes a second predetermined period;
A second phase inversion detection circuit that is connected to the first terminal of the AC power supply and resets the second time to 0 when the potential of the first terminal becomes higher than the reference potential;
A power failure detection circuit characterized by comprising:   The said 1st predetermined period and the said 2nd predetermined period are periods from 1/2 of the period of the alternating voltage supplied from the said alternating current power supply to 3 times the period of the said alternating voltage. Power failure detection circuit. The first timer circuit includes a first switching element having a control terminal connected to the first terminal, a capacitor having one end connected to a constant voltage source via the first switching element, and the capacitor A control terminal is connected to the one end of the second switching element, and one terminal is connected to the output terminal of the power failure detection circuit, and the other terminal is grounded.
The first phase inversion detection circuit includes a third switching element having a control terminal connected to the second terminal, one terminal connected to one end of the capacitor, and the other terminal grounded.
During the first time, the first switching element is turned on to charge the capacitor, and when the first time has passed the first predetermined period, the second switching element is turned on. The power abnormality signal is output from the output terminal,
On the other hand, if the potential of the second terminal becomes higher than the reference potential before the first time reaches the first predetermined period, the capacitor is discharged by turning on the third switching element. The first time is reset to zero,
The power failure detection circuit according to claim 1 or 2.   Connected to the first terminal and the second terminal, both of the voltage of the first terminal and the voltage of the second terminal are from a half of the cycle of the AC voltage supplied from the AC power supply. The power failure detection circuit according to any one of claims 1 to 3, further comprising a voltage drop detection circuit that outputs the power supply abnormality signal when the predetermined voltage is not reached over a long third predetermined period.

Images