JP2006269965A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP2006269965A
JP2006269965A JP2005089311A JP2005089311A JP2006269965A JP 2006269965 A JP2006269965 A JP 2006269965A JP 2005089311 A JP2005089311 A JP 2005089311A JP 2005089311 A JP2005089311 A JP 2005089311A JP 2006269965 A JP2006269965 A JP 2006269965A
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resin
bare chip
semiconductor device
substrate
manufacturing
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JP4470780B2 (en
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Jun Ono
小野　　純
Tomohiko Ishida
智彦 石田
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TDK Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To manufacture a semiconductor device, low in cost and capable of insuring reliability. <P>SOLUTION: A plurality of semiconductor devices are formed on a substrate 17 through a mounting process for mounting a bare chip 11 having semiconductor elements on a substrate 17 having electrode terminals 14; a connecting process for electrically connecting electrode pads 13 formed on the bare chip 11, to the electrode terminals 14 through wires 15; and a coating process for coating a resin 16 by dispense method, so that at least the electrode pads 13 and the wires 15 are covered by the resin 16. Then the semiconductor devices are divided by cutting through a dicing process. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体装置の製造方法に関し、特に、複数のベアチップが搭載された基板上に樹脂を塗布する半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a resin is applied to a substrate on which a plurality of bare chips are mounted.

半導体装置において、水分による腐食や塵・埃等から電極パッドやワイヤ等の金属部材を保護するため、これらの金属部材と外気との接触を防ぐ必要があり、そのためにこれらの金属部材を樹脂で封止する方法が採られている。   In semiconductor devices, in order to protect metal members such as electrode pads and wires from corrosion due to moisture, dust, etc., it is necessary to prevent contact between these metal members and the outside air. The method of sealing is taken.

従来の樹脂封止型の半導体装置の製造は、一般的に以下のような工程で行われていた。
すなわち、所定の回路と電極端子とを有する基板上に、半導体素子を形成したベアチップを搭載する工程と、電極端子とベアチップ上の電極パッドとをワイヤ等で配線して電気的に接続する工程と、その後に、ワイヤ及びベアチップ全体を樹脂で封止する工程と、封止が完了した基板を所定の形状に切断する工程とで、半導体装置を製造していた。半導体素子がフォトダイオード、フォトトランジスタ、ＣＣＤ（Charge Coupled Devices）、レーザーダイオード等の受光素子または発光素子等の光学素子である場合、封止には透明樹脂が使用される（特許文献１参照）。
特開２００５−５３６３号公報 Conventional resin-encapsulated semiconductor devices are generally manufactured in the following steps.
That is, a step of mounting a bare chip on which a semiconductor element is formed on a substrate having a predetermined circuit and an electrode terminal, and a step of electrically connecting the electrode terminal and the electrode pad on the bare chip by wiring. Thereafter, the semiconductor device is manufactured by a step of sealing the entire wire and the bare chip with a resin and a step of cutting the substrate that has been sealed into a predetermined shape. When the semiconductor element is a light receiving element such as a photodiode, a phototransistor, a CCD (Charge Coupled Devices), a laser diode, or an optical element such as a light emitting element, a transparent resin is used for sealing (see Patent Document 1).
JP 2005-5363 A

上記樹脂封止型の半導体装置の製造方法に関しては、以下のような問題点があった。
（１）ワイヤ及びベアチップ全体を樹脂で封止するためには、金型が必要であり、大きな設備投資が要求された。また、金型およびその他、樹脂モールドのための機器や設備のメンテナンスの負担が大きいという問題もあった。
（２）はんだリフロー時等の加熱過程において、封止樹脂とベアチップとの熱膨張率の差による熱応力が生じ、ベアチップに割れや欠けが発生する。あるいは、ワイヤの接続が切れるという懸念もあった。
（３）半導体素子が光学素子である場合に用いられる透明樹脂は、一般に不透明な黒色樹脂等に比べて高価であった。 The method for manufacturing the resin-encapsulated semiconductor device has the following problems.
(1) In order to seal the entire wire and bare chip with resin, a mold is required, and a large capital investment is required. In addition, there is a problem that the burden of maintenance of the mold and other equipment and equipment for resin molding is large.
(2) In a heating process such as during solder reflow, thermal stress is generated due to a difference in thermal expansion coefficient between the sealing resin and the bare chip, and the bare chip is cracked or chipped. There was also a concern that the wire could be disconnected.
(3) The transparent resin used when the semiconductor element is an optical element is generally more expensive than an opaque black resin or the like.

本発明は、このような実情に鑑みてなされた発明であり、低コストで半導体装置を製造できると共に、その半導体装置の信頼性を確保できる半導体装置の製造方法を提供することを目的とする。   The present invention has been made in view of such circumstances, and an object of the present invention is to provide a method of manufacturing a semiconductor device that can manufacture a semiconductor device at low cost and can ensure the reliability of the semiconductor device.

上記目的を達成するため、本発明の第１の観点にかかる半導体装置の製造方法は、
半導体素子が形成された複数のベアチップを、基板上にマトリクス状に搭載する搭載工程と、
前記ベアチップ上に形成された電極パッドと前記基板上に形成された電極端子とを導電部材で電気的に接続する工程と、
少なくとも前記電極パッド及び前記導電部材が樹脂で覆われるように樹脂を塗布する塗布工程と、を有し、
前記搭載工程では、前記基板上に搭載された第１のベアチップの対向する２辺の延長線上に、該第１のベアチップと隣接する第２のベアチップの対向する２辺が重なるように配列され、
前記塗布工程では、前記複数のベアチップの同一直線上の辺について連続的に、樹脂を塗布することを特徴とする。 In order to achieve the above object, a method of manufacturing a semiconductor device according to the first aspect of the present invention includes:
A mounting step of mounting a plurality of bare chips formed with semiconductor elements on a substrate in a matrix;
Electrically connecting the electrode pad formed on the bare chip and the electrode terminal formed on the substrate with a conductive member;
An application step of applying a resin so that at least the electrode pad and the conductive member are covered with the resin,
In the mounting step, the two opposing sides of the second bare chip adjacent to the first bare chip are arranged so as to overlap the extension line of the two opposing sides of the first bare chip mounted on the substrate,
In the coating step, the resin is continuously coated on the same straight side of the plurality of bare chips.

前記ベアチップはほぼ矩形であり、前記電極パッドは前記ベアチップの４辺それぞれに沿った外周部に形成されてもよい。   The bare chip may be substantially rectangular, and the electrode pad may be formed on an outer peripheral portion along each of the four sides of the bare chip.

前記塗布工程では、隣接するベアチップ間に樹脂の切れ目を形成することなく、樹脂を塗布してもよい。   In the application step, the resin may be applied without forming a resin cut between adjacent bare chips.

前記半導体素子は受光部または発光部を有する光学素子を含み、
前記塗布工程では、前記受光部または発光部が樹脂で覆われないように、樹脂を塗布してもよい。 The semiconductor element includes an optical element having a light receiving part or a light emitting part,
In the application step, a resin may be applied so that the light receiving portion or the light emitting portion is not covered with the resin.

少なくとも電極パッドとワイヤを含むように樹脂で被覆することにより、金型を使わずにディスペンス法等により樹脂を塗布することができるため、簡易かつ安価に、半導体装置を製造する方法を提供することができる。また、熱応力差の影響が緩和され、半導体装置の信頼性を確保できる。また、特に半導体素子が光学素子を含む場合であっても不透明な樹脂を使用可能な半導体装置の製造方法を提供することができる。   To provide a method for manufacturing a semiconductor device easily and inexpensively because a resin can be applied by a dispensing method or the like without using a mold by covering with at least an electrode pad and a wire. Can do. Further, the influence of the thermal stress difference is mitigated, and the reliability of the semiconductor device can be ensured. In particular, a method for manufacturing a semiconductor device that can use an opaque resin even when the semiconductor element includes an optical element can be provided.

以下、本発明の実施の形態について図面を用いて詳細に説明する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

（第１の実施の形態）
図１は、本発明の第１の実施の形態に係る半導体装置１０の構成を示す平面図である。この半導体装置１０は、半導体素子が形成されたベアチップ１１を基板１７に搭載した装置である。 (First embodiment)
FIG. 1 is a plan view showing a configuration of a semiconductor device 10 according to the first embodiment of the present invention. The semiconductor device 10 is a device in which a bare chip 11 on which a semiconductor element is formed is mounted on a substrate 17.

基板１７は、例えば矩形であり、基板１７上の中央には、ダイパッド１２が形成されると共に、基板１７の外縁近傍には、外部との接続を可能にする複数の電極端子１４が、基板１７の各辺に沿って形成されている。   The substrate 17 is, for example, rectangular, and the die pad 12 is formed at the center on the substrate 17, and a plurality of electrode terminals 14 that allow connection to the outside are provided near the outer edge of the substrate 17. It is formed along each side.

ベアチップ１１は、基板１７のダイパッド１２の上に取付けられている。ベアチップ１１の外形も矩形である。ベアチップ１１上には、複数の電極パッド１３がベアチップ１１の各辺に沿った外周部に形成されている。ベアチップ１１の電極パッド１３と基板１７の電極端子１４とは、ワイヤ１５により電気的に接続されている。   The bare chip 11 is attached on the die pad 12 of the substrate 17. The external shape of the bare chip 11 is also rectangular. On the bare chip 11, a plurality of electrode pads 13 are formed on the outer peripheral portion along each side of the bare chip 11. The electrode pad 13 of the bare chip 11 and the electrode terminal 14 of the substrate 17 are electrically connected by a wire 15.

また、ベアチップ１１の４辺に並んだ電極パッド１３と、ワイヤ１５とはすべて樹脂１６で被覆されている。   Further, the electrode pads 13 arranged on the four sides of the bare chip 11 and the wires 15 are all covered with the resin 16.

次に、この半導体装置１０の製造方法を説明する。
図２及び図３は、図１の半導体装置１０の製造工程の説明図である。 Next, a method for manufacturing the semiconductor device 10 will be described.
2 and 3 are explanatory diagrams of the manufacturing process of the semiconductor device 10 of FIG.

複数の半導体装置を製造するために、当初の基板１７には、１つの半導体装置を構成するためのダイパッド１２及び複数の電極端子１４のパターンが、マトリクス状に複数組形成されている。   In order to manufacture a plurality of semiconductor devices, a plurality of patterns of the die pad 12 and the plurality of electrode terminals 14 for forming one semiconductor device are formed in a matrix on the initial substrate 17.

このような基板１７に対して、図２（ａ）のベアチップ搭載工程と、図２（ｂ）の接続工程と、図２（ｃ）及び図３（ｄ）の塗布工程と、ダイシング工程とを行うことにより、図３（ｅ）に示すように半導体装置１０が製造される。   The bare chip mounting process in FIG. 2A, the connection process in FIG. 2B, the coating process in FIGS. 2C and 3D, and the dicing process are performed on such a substrate 17. As a result, the semiconductor device 10 is manufactured as shown in FIG.

図２（ａ）のベアチップ搭載工程では、電極端子１４が設けられた基板１７に、半導体素子が形成されたベアチップ１１を搭載する。ベアチップ１１が搭載されるダイパット１２部分には、予め接着用ペースト材が塗布されている。この接着用ペースト材上にベアチップ１１を搭載し、基板１７ごと加熱炉内に入れ、接着用ペースト材を熱硬化させてベアチップ１１を基板１７に固定する。   In the bare chip mounting process of FIG. 2A, the bare chip 11 on which the semiconductor element is formed is mounted on the substrate 17 on which the electrode terminals 14 are provided. An adhesive paste material is applied in advance to the die pad 12 where the bare chip 11 is mounted. The bare chip 11 is mounted on the adhesive paste material, and the substrate 17 is placed in a heating furnace, and the adhesive paste material is thermally cured to fix the bare chip 11 to the substrate 17.

図２（ｂ）の接続工程では、ワイヤボンダを用いてベアチップ１１の表面の外周部に形成された電極パッド１３と基板１７上の電極端子１４とをワイヤ１５で電気的に接続する。   2B, the electrode pad 13 formed on the outer peripheral portion of the surface of the bare chip 11 and the electrode terminal 14 on the substrate 17 are electrically connected by the wire 15 using a wire bonder.

図２（ｃ）の塗布工程では、ベアチップ１１の対向する２辺に沿って電極パッド１３と、ワイヤ１５と、ワイヤ１５の周辺部分に樹脂１６を塗布して覆う。樹脂１６として、熱硬化性のエポキシ樹脂等を用いることができる。   In the coating process of FIG. 2C, the resin 16 is coated and covered on the electrode pad 13, the wire 15, and the peripheral portion of the wire 15 along the two opposing sides of the bare chip 11. As the resin 16, a thermosetting epoxy resin or the like can be used.

この塗布工程では、基板１７をＸ，Ｙの２方向に移動可能なＸＹステージ（図示略）に乗せ、ディスペンサに装着されたシリンダから充填された樹脂１６を押し出すと同時に、シリンダ先端とＸＹステージが相対的に所定距離だけＸ方向に移動するように、シリンダおよび/またはＸＹステージを動かし、ベアチップ１１の一辺について電極パッド１３とワイヤ１５とワイヤ１５の周辺部分とを樹脂１６で覆う。ベアチップ１１の一辺について樹脂１６が塗布された後は、隣接するベアチップ１１に対しても、一つ前に樹脂１６を塗布した辺と同一直線上の辺について同様に樹脂１６を塗布する。以上のように順次隣接するベアチップに樹脂１６を塗布していく。   In this coating process, the substrate 17 is placed on an XY stage (not shown) that can move in two directions of X and Y, and the resin 16 filled from the cylinder mounted on the dispenser is pushed out. The cylinder and / or the XY stage is moved so as to move relatively in the X direction by a predetermined distance, and the electrode pad 13, the wire 15, and the peripheral portion of the wire 15 are covered with the resin 16 on one side of the bare chip 11. After the resin 16 is applied to one side of the bare chip 11, the resin 16 is applied to the adjacent bare chip 11 in the same manner on the side that is on the same straight line as the side to which the resin 16 was applied one time before. As described above, the resin 16 is sequentially applied to adjacent bare chips.

次いで、樹脂１６が塗布された辺に対向する側についても同様に樹脂１６を塗布して電極パッド１３とワイヤ１５およびワイヤ１５の周辺部分に樹脂１６を塗布して覆う。   Next, the resin 16 is similarly applied to the side facing the side to which the resin 16 is applied, and the resin pad 16 is applied to the electrode pad 13, the wire 15, and the peripheral portion of the wire 15.

その後、図３（ｄ）に示すように、ベアチップ１１上の残された辺についても以上の手順に従って順次に樹脂１６を塗布していく。
なお、シリンダは１本ではなく、複数本を使用して塗布するように塗布工程を構成することもできる。 Thereafter, as shown in FIG. 3D, the resin 16 is sequentially applied to the remaining sides on the bare chip 11 according to the above procedure.
Note that the coating process may be configured so that coating is performed using a plurality of cylinders instead of one.

各ベアチップ１１の全ての辺について樹脂１６の塗布が終了した基板１７は加熱炉内に入れられ、塗布した樹脂１６を熱硬化させる。   The substrate 17 on which application of the resin 16 has been completed for all sides of each bare chip 11 is placed in a heating furnace, and the applied resin 16 is thermally cured.

次に、ダイシング工程では、ダイシングカッターを用いて図３（ｄ）に示すダイシングラインｄに沿ってベアチップ１１を搭載した基板１７を所定の位置で切断し、図３（ｅ）に示すようにベアチップ１１単位で半導体装置を分離する。   Next, in the dicing process, the substrate 17 on which the bare chip 11 is mounted is cut at a predetermined position along the dicing line d shown in FIG. 3 (d) using a dicing cutter, and the bare chip as shown in FIG. 3 (e). The semiconductor device is separated by 11 units.

以上により、図１の半導体装置１０が形成される。
本実施形態の半導体装置１０は、ベアチップ１１全体ではなく、少なくとも電極パッド１３とワイヤ１５が覆われるようにベアチップ１１の各辺に沿って樹脂１６を塗布すればよい。したがって、金型を使った樹脂封止によらずに、ディスペンス法等により樹脂１６を塗布すればよく、多数のベアチップ１１が基板に搭載された状態で連続的に樹脂１６を塗布する塗布工程が可能となる。これによって、簡易かつ安価に、半導体装置を製造できる。また、熱応力差の影響が緩和され、半導体装置の信頼性を確保できる。 Thus, the semiconductor device 10 of FIG. 1 is formed.
In the semiconductor device 10 of this embodiment, the resin 16 may be applied along each side of the bare chip 11 so that at least the electrode pad 13 and the wire 15 are covered, not the entire bare chip 11. Therefore, the resin 16 may be applied by a dispensing method or the like without using resin sealing using a mold, and the application process of continuously applying the resin 16 in a state where a large number of bare chips 11 are mounted on the substrate. It becomes possible. Thereby, a semiconductor device can be manufactured easily and inexpensively. Further, the influence of the thermal stress difference is mitigated, and the reliability of the semiconductor device can be ensured.

なお、樹脂１６を塗布する順序は、ベアチップ１１上に形成された電極パッド１３の配置によって適宜調節することも可能である。例えば、図４（ａ）に、樹脂１６を横方向から縦方向に塗布した半導体装置の平面図を示す。図４（ｂ）は、図４（ａ）に示す半導体装置のＡ−Ａ’線断面図である。また、図５（ａ）に、樹脂１６を縦方向から横方向に塗布した半導体装置の平面図を示す。図５（ｂ）は、図５（ａ）に示す半導体装置のＢ−Ｂ’線断面図である。   The order in which the resin 16 is applied can be adjusted as appropriate depending on the arrangement of the electrode pads 13 formed on the bare chip 11. For example, FIG. 4A shows a plan view of a semiconductor device in which the resin 16 is applied from the horizontal direction to the vertical direction. FIG. 4B is a cross-sectional view taken along line A-A ′ of the semiconductor device shown in FIG. FIG. 5A is a plan view of a semiconductor device in which the resin 16 is applied from the vertical direction to the horizontal direction. FIG. 5B is a cross-sectional view of the semiconductor device shown in FIG.

例えば、図４（ａ）に示すように電極パッド１３及び電極端子１４が形成された半導体装置で、横方向から樹脂１６を塗布すると、横方向に塗布された樹脂１６と縦方向に塗布された樹脂１６との接触界面は、図示するように電極パッド１３及び電極端子１４付近に横方向に形成される。本実施の形態で樹脂１６は、供給と中断を交互に繰り返し、連続的に塗布されるため、樹脂１６を供給した際及び中断した際、樹脂１６中に空気が内包される場合がある。結果として、先に塗布された樹脂１６と、その上から塗布された樹脂１６との接触界面近傍には図４（ｂ）に示すように空気が内包される恐れがある。樹脂中に空気が内包されると、空気及びこの空気に含まれる水分が、はんだリフロー時の加熱によって膨張することで樹脂にクラックが生じたり、あるいは半導体装置の性能を劣化させたりするおそれがある。従って、空気が内包される恐れがある接触界面が図４（ｂ）に示すように電極パッド１３付近に形成されると、半導体装置の信頼性を低下させる恐れがあり、図４（ａ）に示す半導体装置では横方向から縦方向に樹脂１６を塗布するのは好ましくない。   For example, as shown in FIG. 4A, in the semiconductor device in which the electrode pad 13 and the electrode terminal 14 are formed, when the resin 16 is applied from the horizontal direction, the resin 16 applied in the horizontal direction is applied in the vertical direction. The contact interface with the resin 16 is formed in the lateral direction in the vicinity of the electrode pad 13 and the electrode terminal 14 as shown in the figure. In the present embodiment, since the resin 16 is continuously applied by alternately repeating supply and interruption, air may be included in the resin 16 when the resin 16 is supplied or interrupted. As a result, air may be contained in the vicinity of the contact interface between the previously applied resin 16 and the resin 16 applied from above, as shown in FIG. If air is encapsulated in the resin, the air and moisture contained in the air may expand due to heating during solder reflow, causing cracks in the resin or degrading the performance of the semiconductor device. . Therefore, if a contact interface that may contain air is formed in the vicinity of the electrode pad 13 as shown in FIG. 4B, the reliability of the semiconductor device may be lowered. In the semiconductor device shown, it is not preferable to apply the resin 16 from the horizontal direction to the vertical direction.

図５（ａ）に示すように、縦方向から横方向へ樹脂を塗布すると樹脂１６の接触界面は縦方向に形成される。この場合、接触界面は電極パッド１３及び電極端子１４から離れて形成され、図５（ｂ）に示すように接触界面近傍に空気が内包された場合であっても、電極パッド１３から離れた位置に形成されるため、電極パッド１３等に影響を及ぼす可能性が小さくなる。このように電極パッド１３及び電極端子１４の配置によって適宜樹脂１６を塗布する順を調節することによって、更に高い信頼性の半導体装置を製造することができる。   As shown in FIG. 5A, when the resin is applied from the vertical direction to the horizontal direction, the contact interface of the resin 16 is formed in the vertical direction. In this case, the contact interface is formed away from the electrode pad 13 and the electrode terminal 14, and even if air is included in the vicinity of the contact interface as shown in FIG. Therefore, the possibility of affecting the electrode pad 13 and the like is reduced. Thus, by adjusting the order in which the resin 16 is applied according to the arrangement of the electrode pads 13 and the electrode terminals 14, a semiconductor device with higher reliability can be manufactured.

（第２の実施の形態）
図６は、本発明の第２の実施形態に係る半導体装置２０の平面図である。
この半導体装置は、半導体素子が形成されたベアチップ１１を基板１７に搭載した装置である。 (Second Embodiment)
FIG. 6 is a plan view of a semiconductor device 20 according to the second embodiment of the present invention.
This semiconductor device is a device in which a bare chip 11 on which a semiconductor element is formed is mounted on a substrate 17.

基板１７は、例えば矩形であり、基板１７上の中央には、ダイパッド１２が形成されると共に、基板１７の外縁近傍には、外部との接続を可能にする複数の電極端子１４が、各辺に沿って形成されている。   The substrate 17 is, for example, rectangular, and the die pad 12 is formed in the center on the substrate 17, and a plurality of electrode terminals 14 that allow connection to the outside are provided in the vicinity of the outer edge of each substrate 17. It is formed along.

ベアチップ１１は、基板１７のダイパッド１２の上に取付けられている。ベアチップ１１の外形も矩形である。ベアチップ１１上には、複数の電極パッド１３が各辺に沿って形成されている。ベアチップ１１の電極パッド１３と基板１７の電極端子１４とがワイヤ１５により、電気的に接続されている。   The bare chip 11 is attached on the die pad 12 of the substrate 17. The external shape of the bare chip 11 is also rectangular. On the bare chip 11, a plurality of electrode pads 13 are formed along each side. The electrode pad 13 of the bare chip 11 and the electrode terminal 14 of the substrate 17 are electrically connected by a wire 15.

ベアチップ１１の４辺に並んだ電極パッド１３と、ワイヤ１５とは、すべて樹脂２６で被覆されている。   The electrode pads 13 arranged on the four sides of the bare chip 11 and the wires 15 are all covered with a resin 26.

本実施の形態の半導体装置２０は、半導体装置１０と異なりベアチップ１１の４辺に並んだ電極パッド１３およびワイヤ１５が全て樹脂２６で被覆されているが、樹脂２６の一部は基板の端部まで到達している。   In the semiconductor device 20 of the present embodiment, unlike the semiconductor device 10, the electrode pads 13 and the wires 15 arranged on the four sides of the bare chip 11 are all covered with the resin 26, but a part of the resin 26 is an end portion of the substrate. Has reached.

次に、この半導体装置２０の製造方法を説明する。
図７及び図８は、図６に示す半導体装置２０の製造方法の説明図である。
複数の半導体装置を製造するために、当初の基板１７には、１つの半導体装置を構成するためのダイパッド１２及び複数の電極端子１４のパターンが、マトリクス状に複数組形成されている。 Next, a method for manufacturing the semiconductor device 20 will be described.
7 and 8 are explanatory views of a method for manufacturing the semiconductor device 20 shown in FIG.
In order to manufacture a plurality of semiconductor devices, a plurality of patterns of the die pad 12 and the plurality of electrode terminals 14 for forming one semiconductor device are formed in a matrix on the initial substrate 17.

このような基板１７に対して、図７（ａ）のベアチップ搭載工程と、図７（ｂ）の接続工程と、図７（ｃ）及び図８（ｄ）の塗布工程と、ダイシング工程とを行うことにより、半導体装置が製造される。   With respect to such a substrate 17, the bare chip mounting process of FIG. 7A, the connection process of FIG. 7B, the coating process of FIGS. 7C and 8D, and the dicing process are performed. By doing so, a semiconductor device is manufactured.

図７（ａ）のベアチップ搭載工程は、第１の実施形態のベアチップ搭載工程と同様であり、電極端子１４が設けられた基板１７に、半導体素子が形成されたベアチップ１１を搭載する。基板１７上のベアチップ１１が搭載されるためのダイパット１２部分には、予め接着用ペースト材が塗布されており、基板１７ごと加熱炉内に入れ、接着用ペースト材を熱硬化させてベアチップ１１を基板１７に固定する。   The bare chip mounting process of FIG. 7A is the same as the bare chip mounting process of the first embodiment, and the bare chip 11 on which the semiconductor element is formed is mounted on the substrate 17 on which the electrode terminals 14 are provided. The portion of the die pad 12 on which the bare chip 11 on the substrate 17 is mounted is preliminarily coated with an adhesive paste material. The entire substrate 17 is placed in a heating furnace, and the adhesive paste material is thermally cured to form the bare chip 11. Fix to the substrate 17.

図７（ｂ）の接続工程も、第１の実施形態の接続工程と同様であり、ワイヤボンダを用いてベアチップ１１の表面の外周部に形成された電極パッド１３と基板１７上の電極端子１４とをワイヤ１５で電気的に接続する。   The connection process of FIG. 7B is the same as the connection process of the first embodiment, and the electrode pads 13 formed on the outer peripheral portion of the surface of the bare chip 11 using the wire bonder and the electrode terminals 14 on the substrate 17 Are electrically connected by a wire 15.

図７（ｃ）の塗布工程では、ベアチップ１１の各辺に沿って電極パッド１３とワイヤ１５およびワイヤ１５の周辺部分に樹脂２６を塗布して覆う。樹脂２６には、熱硬化性のエポキシ樹脂等が使用できる。   In the coating process of FIG. 7C, the resin 26 is applied and covered along the sides of the bare chip 11 to the electrode pad 13, the wire 15, and the peripheral portion of the wire 15. As the resin 26, a thermosetting epoxy resin or the like can be used.

即ち、基板１７をＸＹステージ（図示略）に乗せ、ディスペンサに装着されたシリンダから充填された樹脂２６を押し出すと同時に、シリンダ先端とＸＹステージが相対的に所定距離だけＸ方向に移動するように、シリンダおよび/またはＸＹステージを動かし、ベアチップ１１の一辺について電極パッド１３とワイヤ１５およびワイヤ１５の周辺部分を樹脂２６で覆う。   That is, the substrate 17 is placed on an XY stage (not shown), and the resin 26 filled from the cylinder mounted on the dispenser is pushed out, and at the same time, the tip of the cylinder and the XY stage move relatively in the X direction by a predetermined distance. Then, the cylinder and / or the XY stage is moved, and the electrode pad 13, the wire 15, and the peripheral portion of the wire 15 are covered with the resin 26 on one side of the bare chip 11.

ベアチップ１１の一辺について樹脂２６が塗布された後は、そのままシリンダからの樹脂２６の供給を止めることなくシリンダおよび/またはＸＹステージを移動させ、一つ前に樹脂２６を塗布した辺と同一直線上の辺について同様に樹脂２６を塗布するようにして、順次に樹脂２６を塗布していく。   After the resin 26 is applied to one side of the bare chip 11, the cylinder and / or the XY stage are moved without stopping the supply of the resin 26 from the cylinder, and the same side as the side where the resin 26 is applied one before is moved. Similarly, the resin 26 is applied to the sides, and the resin 26 is sequentially applied.

次いで、樹脂２６が塗布された辺に対向する側についても同様に樹脂２６を塗布する。   Next, the resin 26 is similarly applied to the side facing the side where the resin 26 is applied.

その後、図８（ｄ）に示すようにベアチップ１１上の残された辺についても同様に樹脂２６を塗布する。
なお、シリンダは１本ではなく、複数本を使用して塗布するように塗布工程を構成することもできる。
各ベアチップ１１の全ての辺について樹脂２６の塗布が終了した基板１７は加熱炉内に入れられ、塗布した樹脂２６を熱硬化させる。 Thereafter, as shown in FIG. 8D, the resin 26 is similarly applied to the remaining side on the bare chip 11.
Note that the coating process may be configured so that coating is performed using a plurality of cylinders instead of one.
The substrate 17 on which the application of the resin 26 has been completed for all sides of each bare chip 11 is placed in a heating furnace, and the applied resin 26 is thermally cured.

図８（ｄ）のダイシング工程では、ダイシングカッターを用いてベアチップ１１を搭載した基板１７をダイシングラインｄに沿って切断し、図８（ｅ）に示すようにベアチップ１１単位で半導体装置を分離する。   In the dicing process of FIG. 8D, the substrate 17 on which the bare chip 11 is mounted is cut along the dicing line d using a dicing cutter, and the semiconductor device is separated in units of the bare chip 11 as shown in FIG. .

以上により、図６に示す半導体装置２０が形成される。
本実施形態の半導体装置の製造方法によれば、第１の実施形態による製造方法に比べ、樹脂供給やシリンダまたはＸＹステージ移動の中断と再開を繰り返す必要がないため、更に塗布工程の効率を上げることができる。 Thus, the semiconductor device 20 shown in FIG. 6 is formed.
According to the manufacturing method of the semiconductor device of this embodiment, compared with the manufacturing method of the first embodiment, it is not necessary to repeat and stop and restart the resin supply and the cylinder or XY stage movement, so that the efficiency of the coating process is further increased. be able to.

また、本実施の形態の製造方法では、樹脂の供給を中断することなく連続して行う。樹脂によって空気を押し出しながら塗布工程が行われるため、樹脂中に空気が内包される恐れが軽減する。従って、樹脂中に空気が内包されることで生じるクラックや、半導体装置の性能の劣化を生じさせる恐れが軽減し、高い信頼性を備える半導体装置を製造することができる。例えば、図９（ａ）に、樹脂２６を縦方向から横方向に塗布した半導体装置の平面図を示す。図９（ｂ）は、図９（ａ）に示す半導体装置のＣ−Ｃ’線断面図である。図９（ａ）に示すように縦方向から横方向に樹脂２６を塗布した場合、接触界面は縦方向に形成される。上述したように本実施の形態では樹脂２６は中断なく連続的に供給されるため、樹脂２６中に空気が内包される恐れが軽減され、図９（ｂ）に示すように接触界面近傍に空気が内包されることなく半導体装置を製造することができる。   Further, in the manufacturing method of the present embodiment, the resin supply is continuously performed without interruption. Since the coating process is performed while extruding air with the resin, the risk of air being included in the resin is reduced. Therefore, the possibility of causing cracks caused by the inclusion of air in the resin and the deterioration of the performance of the semiconductor device is reduced, and a semiconductor device having high reliability can be manufactured. For example, FIG. 9A shows a plan view of a semiconductor device in which the resin 26 is applied from the vertical direction to the horizontal direction. FIG. 9B is a cross-sectional view taken along line C-C ′ of the semiconductor device illustrated in FIG. As shown in FIG. 9A, when the resin 26 is applied from the vertical direction to the horizontal direction, the contact interface is formed in the vertical direction. As described above, in the present embodiment, the resin 26 is continuously supplied without interruption, so that the possibility of air being contained in the resin 26 is reduced, and as shown in FIG. The semiconductor device can be manufactured without inclusion.

なお、本実施の形態の製造方法は、第１の実施の形態による製造方法と比べ、次のような利点も有する。図５（ａ）及び図５（ｂ）に示すように、第１の実施の形態による製造方法では、電極パッド１３及び電極端子１４の配置に応じて樹脂１６を塗布する順序を調節することで、空気が内包される恐れのある接触界面を電極パッド１３等から離すことができ、半導体装置１０の信頼性を確保することができる。しかし、例えば縦方向と横方向に同じように電極パッド等が配置されている等、電極パッド等の配置によっては塗布する順序を調節することで接触界面を電極パッド等から離すことが難しい場合もある。このような場合であっても、本実施の形態の製造方法では、樹脂の供給を途中で中断することなく、樹脂を塗布していくため、樹脂中に空気が混入されにくく、先に塗布された樹脂とその上から塗布された樹脂との接触界面近傍に空気が内包される恐れが軽減する。従って、高い信頼性を備える半導体装置を製造することができる。   Note that the manufacturing method of the present embodiment also has the following advantages compared to the manufacturing method according to the first embodiment. As shown in FIGS. 5A and 5B, in the manufacturing method according to the first embodiment, the order in which the resin 16 is applied is adjusted according to the arrangement of the electrode pads 13 and the electrode terminals 14. The contact interface that may contain air can be separated from the electrode pad 13 and the like, and the reliability of the semiconductor device 10 can be ensured. However, there are cases where it is difficult to separate the contact interface from the electrode pad etc. by adjusting the application sequence depending on the arrangement of the electrode pad etc. is there. Even in such a case, in the manufacturing method of the present embodiment, since the resin is applied without interrupting the supply of the resin in the middle, it is difficult for air to be mixed into the resin and the resin is applied first. The risk of air being contained in the vicinity of the contact interface between the coated resin and the resin applied thereon is reduced. Therefore, a semiconductor device having high reliability can be manufactured.

（第３の実施の形態）
図１０は本発明の第３の実施形態に係る半導体装置３０の平面図である。
この半導体装置３０はフォトダイオードやレーザーダイオード等の光学素子１８が形成されたベアチップ１１を基板１７に搭載した装置である。
本実施の形態に係る半導体装置３０は、ベアチップ１１に光学素子１８が形成されている以外は第１の実施の形態と同様の構成を採る。第１の実施の形態と共通する部分は、同一の引用番号を付し詳細な説明は、省略する。 (Third embodiment)
FIG. 10 is a plan view of a semiconductor device 30 according to the third embodiment of the present invention.
The semiconductor device 30 is a device in which a bare chip 11 on which an optical element 18 such as a photodiode or a laser diode is formed is mounted on a substrate 17.
The semiconductor device 30 according to the present embodiment has the same configuration as that of the first embodiment except that the optical element 18 is formed on the bare chip 11. Portions common to the first embodiment are given the same reference numerals, and detailed descriptions thereof are omitted.

基板１７は、例えば矩形であり、基板１７上の中央には、ダイパッド１２が形成されると共に、基板１７の外縁近傍には、外部との接続を可能にする複数の電極端子１４が、各辺に沿って形成されている。   The substrate 17 is, for example, rectangular, and the die pad 12 is formed in the center on the substrate 17, and a plurality of electrode terminals 14 that allow connection to the outside are provided in the vicinity of the outer edge of each substrate 17. It is formed along.

ベアチップ１１は、基板１７のダイパッド１２の上に取付けられている。ベアチップ１１の外形も矩形である。ベアチップ１１上には、複数の電極パッド１３が各辺に沿って形成されている。ベアチップ１１の電極パッド１３と基板１７の電極端子１４とがワイヤ１５により、電気的に接続されている。   The bare chip 11 is attached on the die pad 12 of the substrate 17. The external shape of the bare chip 11 is also rectangular. On the bare chip 11, a plurality of electrode pads 13 are formed along each side. The electrode pad 13 of the bare chip 11 and the electrode terminal 14 of the substrate 17 are electrically connected by a wire 15.

ベアチップ１１の４辺に並んだ電極パッド１３及びワイヤ１５が、すべて樹脂１６で被覆されている。   The electrode pads 13 and the wires 15 arranged on the four sides of the bare chip 11 are all covered with the resin 16.

光学素子１８は、フォトダイオードやレーザーダイオード等から構成され光学素子１８の発光部または受光部は樹脂１６で覆われず、開口している。   The optical element 18 is composed of a photodiode, a laser diode, or the like, and the light emitting portion or the light receiving portion of the optical element 18 is not covered with the resin 16 and is opened.

この半導体装置の製造方法は、図２及び３に示す製造工程で、光学素子の発光部または受光部が樹脂で覆われることなく開口するようにする必要がある以外は、第１の実施形態と同様の製造方法である。   The manufacturing method of this semiconductor device is the same as that of the first embodiment except that it is necessary to open the light emitting part or the light receiving part of the optical element without being covered with resin in the manufacturing process shown in FIGS. It is the same manufacturing method.

本実施の形態の半導体装置の製造方法は、樹脂１６を電極端子１４、電極パッド１３等のみを覆うように形成するため、ベアチップ１１上に形成された光学素子１８は、受光面又は発光面が露出する。従って、封止に透明樹脂を使う必要がなく、コストを下げることができる。   In the semiconductor device manufacturing method of the present embodiment, the resin 16 is formed so as to cover only the electrode terminals 14, the electrode pads 13, etc., so that the optical element 18 formed on the bare chip 11 has a light receiving surface or a light emitting surface. Exposed. Therefore, it is not necessary to use a transparent resin for sealing, and the cost can be reduced.

本発明は上述した実施の形態に限られず、様々な修正及び応用が可能である。
例えば、上述した第３の実施の形態のようにベアチップに光学素子が形成される場合、第２の実施の形態と同様に連続的に樹脂を塗布する構成を採用することも可能である。この場合、発光部又は受光部が樹脂で覆われることなく開口するように樹脂を形成する。 The present invention is not limited to the above-described embodiments, and various modifications and applications are possible.
For example, when an optical element is formed on a bare chip as in the third embodiment described above, it is possible to employ a configuration in which a resin is continuously applied as in the second embodiment. In this case, the resin is formed so that the light emitting part or the light receiving part is opened without being covered with the resin.

本発明の第１の実施の形態に係る半導体装置の平面図である。1 is a plan view of a semiconductor device according to a first embodiment of the present invention. 本発明の第１の実施の形態に係る半導体装置の製造工程を説明する図である。It is a figure explaining the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. 本発明の第１の実施の形態に係る半導体装置の製造工程を説明する図である。It is a figure explaining the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. 本発明の第１の実施の形態に係る半導体装置の製造工程において樹脂を塗布する順序について説明する図である。It is a figure explaining the order which applies resin in the manufacturing process of the semiconductor device concerning a 1st embodiment of the present invention. 本発明の第１の実施の形態に係る半導体装置の製造工程において樹脂を塗布する順序について説明する図である。It is a figure explaining the order which applies resin in the manufacturing process of the semiconductor device concerning a 1st embodiment of the present invention. 本発明の第２の実施の形態に係る半導体装置の平面図である。FIG. 6 is a plan view of a semiconductor device according to a second embodiment of the present invention. 本発明の第２の実施の形態に係る半導体装置の製造工程を説明する図である。It is a figure explaining the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. 本発明の第２の実施の形態に係る半導体装置の製造工程を説明する図である。It is a figure explaining the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. 本発明の第２の実施の形態に係る半導体装置の製造工程において樹脂を塗布する順序について説明する図である。It is a figure explaining the order which apply | coats resin in the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. 本発明の第３の実施の形態に係る半導体装置の平面図である。It is a top view of the semiconductor device concerning a 3rd embodiment of the present invention.

符号の説明Explanation of symbols

１０，２０，３０ 半導体装置
１１ ベアチップ
１２ ダイパッド
１３ 電極パッド
１４ 電極端子
１５ ワイヤ
１６，２６ 樹脂
１７ 基板
１８ 光学素子 DESCRIPTION OF SYMBOLS 10, 20, 30 Semiconductor device 11 Bare chip 12 Die pad 13 Electrode pad 14 Electrode terminal 15 Wire 16, 26 Resin 17 Substrate 18 Optical element

Claims (4)

半導体素子が形成された複数のベアチップを、基板上にマトリクス状に搭載する搭載工程と、
前記ベアチップ上に形成された電極パッドと前記基板上に形成された電極端子とを導電部材で電気的に接続する工程と、
少なくとも前記電極パッド及び前記導電部材が樹脂で覆われるように樹脂を塗布する塗布工程と、を有し、
前記搭載工程では、前記基板上に搭載された第１のベアチップの対向する２辺の延長線上に、該第１のベアチップと隣接する第２のベアチップの対向する２辺が重なるように配列され、
前記塗布工程では、前記複数のベアチップの同一直線上の辺について連続的に、樹脂を塗布することを特徴とする半導体装置の製造方法。 A mounting step of mounting a plurality of bare chips formed with semiconductor elements on a substrate in a matrix;
Electrically connecting the electrode pad formed on the bare chip and the electrode terminal formed on the substrate with a conductive member;
An application step of applying a resin so that at least the electrode pad and the conductive member are covered with the resin,
In the mounting step, the two opposing sides of the second bare chip adjacent to the first bare chip are arranged so as to overlap the extension line of the two opposing sides of the first bare chip mounted on the substrate,
In the coating process, a resin is continuously coated on the same straight side of the plurality of bare chips. 前記ベアチップはほぼ矩形であり、前記電極パッドは前記ベアチップの４辺それぞれに沿った外周部に形成されることを特徴とする請求項１に記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the bare chip is substantially rectangular, and the electrode pad is formed on an outer peripheral portion along each of four sides of the bare chip. 前記塗布工程では、隣接するベアチップ間に樹脂の切れ目を形成することなく、樹脂を塗布することを特徴とする請求項１又は２に記載の半導体装置の製造方法。   3. The method of manufacturing a semiconductor device according to claim 1, wherein in the applying step, the resin is applied without forming a resin cut between adjacent bare chips. 4. 前記半導体素子は受光部または発光部を有する光学素子を含み、
前記塗布工程では、前記受光部または発光部が樹脂で覆われないように、樹脂を塗布することを特徴とする請求項１乃至３のいずれか１項に記載の半導体装置の製造方法。 The semiconductor element includes an optical element having a light receiving part or a light emitting part,
4. The method of manufacturing a semiconductor device according to claim 1, wherein, in the application step, a resin is applied so that the light receiving portion or the light emitting portion is not covered with the resin. 5.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2271086A1 (en) 2006-09-29 2011-01-05 Sanyo Electric Co., Ltd. Projection-type image display device and projection-type image display system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2271086A1 (en) 2006-09-29 2011-01-05 Sanyo Electric Co., Ltd. Projection-type image display device and projection-type image display system

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