JP2006269899A - Method of manufacturing semiconductor apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor apparatus capable of restraining an insulating film that contains an overhydrogenated silazane polymer from deteriorating in characteristics. <P>SOLUTION: The method comprises a first process of applying a solution containing the overhydrogenated silazane polymer on a substrate 110, a second process of forming a film 108 containing the overhydrogenated silazane polymer by heating the solution, and a third process of turning the film 108 into an insulating film containing silicon and oxygen by subjecting the film 108 to an oxidation treatment in a reduced-pressure atmosphere 110 of water vapor. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device including forming an insulating film containing silicon and oxygen using a solution containing a perhydrogenated silazane polymer.

  The miniaturization of LSI is aimed at improving device performance (for example, improving operation speed and reducing power consumption) by high integration and suppressing manufacturing cost. In recent years, minimum feature sizes have been advanced to near 0.1 microns at the mass production level. Although the miniaturization technology is becoming more difficult, it is predicted that further miniaturization will progress to 0.1 microns or less in the future.

In the development stage, in the case of a logic device, a device with a gate length reduced to about 30 nm is prototyped.

  For high integration, it is important to miniaturize the element isolation region that occupies the majority of the element area. In recent years, STI (Shallow Trench Isolation) technology has been adopted as a method for forming a fine element isolation region. The STI technique is a technique of forming an element isolation region by embedding an insulating film (element isolation insulating film) in a groove (element isolation groove) formed by anisotropic etching.

  By the STI technique, an element isolation region having a groove width of about 90 nm to 70 nm and reaching 0.1 μm or less is realized. Similarly, even in a memory where high integration is important, the active area width and element isolation region width of transistors and the like are also about to reach an area of 0.1 micron or less of about 90 nm to 70 nm. Therefore, miniaturization of the element isolation region of the memory has become important.

  With the miniaturization, the difficulty of forming an element isolation region is increasing. The reason is as follows. The separation performance (insulating property) between elements is determined by the effective distance between adjacent elements. This effective distance is determined by the shortest distance of the peripheral length of the element isolation groove along the side wall from one side wall to the bottom surface and the other side wall of the element isolation groove. In order not to reduce the isolation performance even if the device is miniaturized, it is required to keep the effective distance as before, that is, to keep the depth of the element isolation groove substantially constant. Since the width of the element isolation trench becomes thinner as the miniaturization progresses, the aspect ratio of the element isolation trench becomes higher for each generation of miniaturization. As a result, the difficulty of forming an element isolation region increases with miniaturization.

  Currently, there is a high density plasma (HDP) CVD process as one of the standard element isolation insulating film forming techniques. When the silicon oxide film (HDP silicon oxide film) is formed in the element isolation trench of the 0.1 micron generation or less using the HDP-CVD process, the aforementioned aspect ratio reaches 3 or more. For this reason, it is very difficult to form an HDP silicon oxide film having no voids (unfilled) in the element isolation trench. Voids in the HDP silicon oxide film in the element isolation trench cause a decrease in insulation.

At present, as the technology for embedding element isolation trenches that have been miniaturized, the element isolation trenches are formed with a spin-on glass (SOG) film formed by a spin coating method or a fluid insulating film such as an O ₃ / TEOS film. It is considered that a method of embedding or a method of embedding an element isolation trench with a proven HDP silicon oxide film and the above-described fluid insulating film is considered promising.

  As one of the embedding techniques using an insulating film having fluidity, a solution containing a perhydrogenated silazane polymer (polysilazane) is applied on a silicon substrate on which element isolation grooves are formed, and the inside of the element isolation grooves is polysilazane. A method is known in which a polysilazane film is changed to a silicon oxide film by filling the film with a film and then heating the polysilazane film in a water vapor atmosphere using a diffusion furnace (Patent Documents 1 and 2).

In the silicon oxide film formed by the above method, impurities such as carbon (C) contained in an organic solvent such as nitrogen (N) and dibutyl ether contained in the raw material remain. Impurities remaining in the silicon oxide film act as positive fixed charges. The fixed charge causes deterioration of the insulating characteristics of the silicon oxide film.
JP 2004-179614 A JP 2002-367980 A

  The objective of this invention is providing the manufacturing method of the semiconductor device which can suppress the characteristic deterioration of the insulating film containing a perhydrogenated silazane polymer.

  A method of manufacturing a semiconductor device according to the present invention includes a step of applying a solution containing a perhydrogenated silazane polymer on a substrate, a step of heating the solution to form a film containing a perhydrogenated silazane polymer, And oxidizing the film in a water vapor atmosphere under reduced pressure to convert the film into an insulating film containing silicon and oxygen.

  The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the semiconductor device which can suppress the characteristic deterioration of the insulating film containing a perhydrogenated silazane polymer can be implement | achieved.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
1 to 9 are cross-sectional views for explaining a method for manufacturing a semiconductor device according to the first embodiment. 1 to 9 are cross-sectional views of the transistor in the channel width direction.

  In the present embodiment, a process of forming an element isolation trench before forming a gate (gate oxide film, floating gate electrode) of a transistor will be described.

[Figure 1]
A gate oxide film 102, a silicon nitride film 103, a CVD silicon oxide film 104, and a resist pattern 105 are sequentially formed on the silicon substrate 101. The gate oxide film 102 is a thermal oxide film. The film thickness of the gate oxide film 102 is 5 nm, for example. The film thickness of the silicon nitride film 103 is, for example, 150 nm. The silicon nitride film 103 is used as a polishing stopper during a CMP (Chemical Mechanical Polishing) process.

[Figure 2]
Using the resist pattern 105 as a mask, the CVD silicon oxide film 104 is etched by an RIE (Reactive Ion Etching) process. The etched CVD silicon oxide film 104 is used as a hard mask.

[Fig. 3]
The resist pattern 105 is removed by an asher process and a wet process using a mixed solution of sulfuric acid and hydrogen peroxide. Using the CVD silicon oxide film 104 as a mask, the silicon nitride film 103, the gate oxide film 102, and the silicon substrate 101 are sequentially etched by the RIE process, and a groove 106 is formed on the surface of the silicon substrate 101. The depth of the groove 106 is, for example, 300 nm.

[Fig. 4]
The CVD silicon oxide film 104 is selectively removed using hydrofluoric acid vapor. A thermal oxide film 107 is formed on the inner surface of the groove 106. The thickness of the thermal oxide film 107 is, for example, 4 nm. An element isolation trench including the trench 106 and the thermal oxide film 107 is obtained through the above steps.

[Fig. 5]
A polysilazane film 108 is formed on the entire surface of the substrate using a spin coating method. Hereinafter, a method for forming the polysilazane film 108 will be described in detail.

A perhydrogenated silazane (perhydrosilazane) polymer [(SiH ₂ NH) n] is dispersed in a solvent such as xylene or dibutyl ether to produce a perhydrogenated silazane polymer solution.

  By a spin coating method, a perhydrogenated silazane polymer solution is applied onto the silicon substrate 101 to form a coating film containing the perhydrogenated silazane polymer. Since the coating film is formed by coating a perhydrogenated silazane polymer solution, the high-aspect-ratio element isolation groove is not coated with voids (unfilled) and seams (seamless unfilled). Embedded in.

  The conditions for forming the coating film by the spin coating method are, for example, as follows. The rotation speed of the silicon substrate 101 is 4000 rpm, the rotation time is 30 seconds, the dropping amount of the perhydrogenated silazane polymer solution is 8 cc, and the target coating film thickness is 500 nm.

  After the coating film is formed, the silicon substrate 101 is heated to 180 ° C. by hot play, and then the silicon substrate 101 is baked for 3 minutes in an inert gas atmosphere. Thereby, the solvent in the perhydrogenated silazane polymer solution is volatilized, and the coating film is changed to the polysilazane film 108. In the polysilazane film 108 at this stage, carbon or hydrocarbon derived from the solvent remains as an impurity about several to dozens of percent.

  Next, the silicon substrate 101 is introduced into a diffusion furnace having a temperature of about 200 ° C., and then the temperature in the diffusion furnace is raised to a predetermined temperature (220 to 280 ° C.). When the temperature is reached, the system waits for, for example, 5 minutes or more for temperature stabilization. Thereby, the uniformity of the temperature in the wafer surface and in the batch can be improved.

[Fig. 6]
Water vapor is introduced into the diffusion furnace, and the first oxidation treatment is performed on the polysilazane film 108 in a water vapor atmosphere 109 that satisfies a predetermined condition. The pressure (partial pressure) of water vapor in the water vapor atmosphere 109 is 20 Kpa to 40 Kpa. The temperature of the water vapor atmosphere 109 is 220 ° C. to 280 ° C. The processing time is about 1 hour, for example.

  FIG. 22 is a diagram showing the relationship between the in-plane uniformity of the thickness of an oxide film formed by oxidizing a bare silicon wafer in a water vapor atmosphere and the pressure. From FIG. 22, it can be seen that when the pressure exceeds 40 Kpa, the in-plane uniformity decreases rapidly. When the pressure exceeds 40 Kpa, the oxidation amount increases rapidly on the periphery of the wafer. This is the reason for the decrease in in-plane uniformity. Therefore, in the present embodiment, the pressure of the first oxidation treatment is set to 40 Kpa or less.

FIG. 23 is a diagram showing the relationship between the C concentration and pressure of an oxide film formed by oxidizing a bare silicon wafer in a water vapor atmosphere. From FIG. 23, it can be seen that when the pressure is less than 20 Kpa, the C concentration rapidly increases and the C concentration exceeds 3 × 10 ¹⁹ cm ⁻³ . Since C in the oxide film becomes a fixed charge, when the C concentration becomes a large value as described above, the electrical characteristics and reliability of the transistor in the memory cell are lowered. In particular, the flat band voltage (Vfb) shift of the transistor becomes significant. The Vfb shift becomes a problem when a high-k insulating film is used as the gate insulating film, that is, when the miniaturization of elements progresses. Therefore, in this embodiment, the pressure of the first oxidation treatment is set to 20 Kpa or more.

  FIG. 24 is a diagram showing the relationship between the density and temperature of an oxide film formed by oxidizing a bare silicon wafer in a water vapor atmosphere. From FIG. 24, it can be seen that when the temperature is lower than 220 ° C., the density of the oxide film (film density) rapidly decreases. A decrease in film density causes a decrease in wet etching resistance and a decrease in CMP resistance. Therefore, in this embodiment, the temperature of the first oxidation treatment is set to 220 ° C. or higher.

  FIG. 25 is a diagram showing the relationship between the C concentration and temperature of an oxide film formed by oxidizing a bare silicon wafer in a water vapor atmosphere. FIG. 25 shows that when the temperature exceeds 280 ° C., the C concentration increases rapidly. At the stage of the oxidation treatment in the steam atmosphere 109, C must be removed before the oxidation (shrinkage) of the film proceeds. When the temperature is high, the escape of C becomes worse. Therefore, in the present embodiment, the temperature of the first oxidation treatment is set to 280 ° C. or lower.

[Fig. 7]
After completion of the oxidation treatment (first oxidation treatment) in the water vapor atmosphere 109, the temperature in the diffusion furnace is further raised, and the second temperature is increased with respect to the polysilazane film 108 in the water vapor atmosphere 110 that satisfies a predetermined condition. Is oxidized. The pressure (partial pressure) of water vapor in the water vapor atmosphere 110 is equal to or lower than the pressure of the first oxidation treatment and is 20 to 40 Kpa. The temperature of the water vapor atmosphere 110 is 500 to 580 ° C. The processing time is, for example, about 10 minutes.

  In the present embodiment, the first and second oxidation treatments are performed in the same diffusion furnace. Thereby, processing time is shortened and productivity is improved. Furthermore, in the present embodiment, the first and second oxidation treatments are performed by a batch type processing apparatus. Thereby, the processing amount per unit time can be increased.

  FIG. 26 is a diagram showing the relationship between the thickness (oxide thickness) of an oxide film formed by oxidizing a bare silicon wafer in a water vapor atmosphere and the pressure. From FIG. 26, it can be seen that when the pressure exceeds 40 Kpa, the oxide film thickness increases rapidly. The rapid increase in the oxide film thickness means that the peripheral structure (for example, active area) of the polysilazane film is oxidized. Specifically, as shown in FIG. 27, the edge of the gate oxide film 102 is oxidized, thereby increasing the thickness of the edge (gate bird's beak) 102bk. The gate bird's beak 102bk prevents the miniaturization of the element. Therefore, in the present embodiment, the upper limit of the pressure of the second oxidation treatment is set to 40 Kpa or less.

  As shown in FIG. 28, the gate bird's beak becomes more problematic in the process of forming the element isolation trench after forming the gate of the transistor (second embodiment).

  On the other hand, the lower limit of the pressure of the second oxidation treatment is set to 20 Kpa or more for the same reason as in the case of the first oxidation treatment. The second oxidation treatment is performed at a pressure equal to or lower than the pressure of the first oxidation treatment. This is to suppress oxidation of an active area such as a gate bird's beak.

FIG. 29 is a diagram showing the relationship between the C concentration of an oxide film formed by oxidizing a bare silicon wafer in a water vapor atmosphere and the temperature. FIG. 28 shows that when the temperature is lower than 500 ° C., the C concentration rapidly increases and the C concentration exceeds 3 × 10 ¹⁹ cm ⁻³ . When the C concentration becomes such a large value, the Vfb shift becomes remarkable as described above. Therefore, in this embodiment, the temperature of the second oxidation treatment is set to 500 ° C. or higher.

  FIG. 30 is a diagram showing the relationship between the oxide film thickness on the bare silicon wafer formed by oxidizing the bare silicon wafer in a water vapor atmosphere and the temperature. FIG. 30 shows that when the temperature exceeds 580 ° C., the oxide film thickness rapidly increases. The rapid increase in oxide film thickness causes gate bird's beak as described above. Therefore, in this embodiment, the temperature of the second oxidation treatment is set to 580 ° C. or lower. The second oxidation treatment is performed at a higher temperature than the first oxidation treatment. This is because the polysilazane film 108 is sufficiently oxidized and densified.

  26 and 30 that the increase in the oxide film thickness can be suppressed to 1.5 nm or less by controlling the pressure of the first oxidation treatment and the temperature of the second oxidation treatment. According to the study by the inventors of the present application, it has been confirmed that deterioration of electrical characteristics such as Vfb shift can be suppressed by suppressing the increase in the oxide film thickness to 1.5 nm or less. In other words, it was confirmed that the peripheral structure of the active area around the polysilazane film 108 is not affected by suppressing the increase in the oxide film thickness to 1.5 nm or less.

[Fig. 8]
By the first and second oxidation treatments, impurities (carbon and hydrocarbons) in the polysilazane film 108 are removed, and part of the Si—N bonds in the polysilazane film 108 are converted into Si—O bonds. The film 108 is changed to the silicon oxide film 111. This reaction typically proceeds as shown below.

SiH ₂ NH + 2O → SiO ₂ + NH ₃
The oxide film of the embodiment obtained by performing the first and second oxidation treatments on the bare silicon wafer, and the oxidation treatment (500 ° C., 40 KPa, 15 minutes in a water vapor atmosphere) on the bare silicon wafer. The oxide film of the comparative example obtained by performing the heat treatment) was compared. As a result, the results shown in Table 1 were obtained.

  When the oxide film of the embodiment and the oxide film of the comparative example are compared, the oxide film thickness on the bare silicon wafer, which is a measure of the oxidation amount in the oxidation process, is almost equal. However, regarding the C concentration in the oxide film, the oxide film of the embodiment is １ ／ of the oxide film of the comparative example, and the C concentration is greatly reduced. Therefore, according to this embodiment, it is possible to form a silicon oxide film as an element isolation insulating film with good film quality.

  In order to reduce the concentration of impurities in the silicon oxide film by the oxidation treatment of the comparative example, it is necessary to increase the amount of oxidation of the polysilazane film. However, when the amount of oxidation of the polysilazane film is increased, an insulating film such as a silicon oxide film in the active area and a polysilicon film used as a gate electrode are also oxidized. Such oxidation of the film in the active area causes deterioration of electrical characteristics and reliability of the transistor.

  In order to suppress the oxidation of the film in the active area, the oxidation amount of the polysilazane film may be reduced. However, if the oxidation amount of the polysilazane film is reduced, the amount of impurities such as carbon remaining in the polysilazane film cannot be sufficiently reduced. Impurities remaining in the polysilazane film serve as positive fixed charges. Accordingly, even in the method of reducing the oxidation amount of the polysilazane film in order to suppress the oxidation of the film in the active area, the electrical characteristics of the transistor are similarly deteriorated.

  Thereafter, in order to further increase the density of the silicon oxide film 111, high-temperature annealing is performed. Typical conditions are an atmosphere of dry oxygen, a temperature of 900 ° C., and a time of 30 minutes.

[Fig. 9]
The silicon oxide film 111 is polished by a CMP process using the silicon nitride film 103 as a stopper, and the surface is flattened. Since the silicon oxide film 111 is sufficiently dense, deterioration of the silicon oxide film 111 during the CMP process is suppressed.

  Thereafter, a NAND type flash memory shown in FIG. 10 is obtained through known steps such as a step of removing the silicon nitride film 103 and a step of forming an element such as a transistor by a wet process using hot phosphoric acid. In FIG. 10, 112 is a floating gate electrode, 113 is an insulating film between gate electrodes, 114 is a control gate electrode, 115 is a silicide layer, and 116 is an interlayer insulating film.

(Second Embodiment)
11 to 20 are cross-sectional views for explaining the method for manufacturing a semiconductor device according to the second embodiment. 11 to 20 are cross-sectional views of the transistor in the channel width direction.

  In this embodiment, a process (STI process) for forming an element isolation region after forming a gate (gate oxide film, floating gate electrode) of a transistor will be described. In the STI process of this embodiment, the element isolation trench is filled with an HDP-CVD silicon oxide film and a polysilazane film, and first and second oxidation treatments are performed on the polysilazane film in a water vapor atmosphere under reduced pressure. And a step of changing the polysilazane film into a silicon oxide film.

[Fig. 11]
On the silicon substrate 201, a gate oxide film 202, a polycrystalline silicon film 203, a silicon nitride film 204, a CVD silicon oxide film 205, and a resist pattern 206 are sequentially formed. The gate oxide film 202 is a thermal oxide film. The polycrystalline silicon film 203 is processed to become a gate electrode. The silicon nitride film 204 is used as a polishing stopper during the CMP process.

[Fig. 12]
The CVD silicon oxide film 205 is etched by the RIE process using the resist pattern 206 as a mask. The etched CVD silicon oxide film 205 is used as a hard mask.

[FIG. 13]
The resist pattern 206 is removed by an asher process and a wet process using a mixed solution of sulfuric acid and hydrogen peroxide. Using the CVD silicon oxide film 205 as a mask, the silicon nitride film 204, the polycrystalline silicon film 203, the gate oxide film 202, and the silicon substrate 201 are sequentially etched by the RIE process, and a groove 207 is formed on the surface of the silicon substrate 201. . The depth of the groove 207 is, for example, 200 nm.

[FIG. 14]
The CVD silicon oxide film 205 is selectively removed using hydrofluoric acid vapor. A thermal oxide film 208 is formed on the inner surface of the groove 207 by thermal oxidation. The film thickness of the thermal oxide film 208 is 4 nm, for example. An element isolation trench including the trench 207 and the thermal oxide film 208 is obtained through the above steps.

[FIG. 15]
An HDP-CVD silicon oxide film 209 is formed on the entire surface of the substrate. The wide element isolation trench (groove 207 ′) is completely filled with the HDP-CVD silicon oxide film 209. However, the narrow element isolation trench (groove 207) is not completely filled with the HDP-CVD silicon oxide film 209. A slit-like gap remains in the narrow element isolation groove. The aspect ratio of the slit-shaped gap is 10 or more. Therefore, it is difficult to fill the narrow element isolation trench with only the HDP-CVD silicon oxide film 209.

[FIG. 16]
A polysilazane film 210 is formed on the entire surface of the substrate using a spin coating method. Hereinafter, a method for forming the polysilazane film 210 will be described in detail.

A perhydrogenated silazane (perhydrosilazane) polymer [(SiH ₂ NH) n] is dispersed in a solvent such as xylene or dibutyl ether to produce a perhydrogenated silazane polymer solution.

  By a spin coating method, a perhydrogenated silazane polymer solution is applied onto the silicon substrate 201 to form a coating film containing the perhydrogenated silazane polymer. Since the coating film is formed by coating a perhydrogenated silazane polymer solution, the high-aspect-ratio element isolation groove is not coated with voids (unfilled) and seams (seamless unfilled). Embedded in.

  The conditions for forming the coating film by the spin coating method are, for example, as follows. The rotation speed of the silicon substrate 201 is 4000 rpm, the rotation time is 30 seconds, the dropping amount of the perhydrogenated silazane polymer solution is 8 cc, and the target coating film thickness is 500 nm.

  After forming the coating film, the silicon substrate 201 is heated to 180 ° C. by hot play, and then the silicon substrate 201 is baked for 3 minutes in an inert gas atmosphere. Thereby, the solvent in the perhydrogenated silazane polymer solution is volatilized, and the coating film is changed to the polysilazane film 210. In the polysilazane film 210 at this stage, carbon or hydrocarbon derived from the solvent remains as an impurity about several percent to several tens of percent.

  Next, the silicon substrate 201 is introduced into a diffusion furnace having a temperature of about 200 ° C., and then the temperature in the diffusion furnace is raised to a predetermined temperature (220 to 280 ° C.). When it reaches the temperature, it waits for 5 minutes or more to stabilize the temperature. Thereby, the uniformity of the temperature in the wafer surface and in the batch can be improved.

[Fig. 17]
Water vapor is introduced into the diffusion furnace, and the first oxidation treatment is performed on the polysilazane film 210 in a water vapor atmosphere 211 that satisfies a predetermined condition. The pressure (partial pressure) of water vapor in the water vapor atmosphere 211 is 20 Kpa to 40 Kpa. The temperature of the water vapor atmosphere 211 is 220 ° C. to 280 ° C. The processing time is about 1 hour. That is, the range of the pressure and temperature of the first oxidation treatment of the present embodiment and the reason thereof are the same as those of the first oxidation treatment of the first embodiment.

[FIG. 18]
After the oxidation treatment (first oxidation treatment) in the water vapor atmosphere 211 is completed, the temperature in the diffusion furnace is further increased, and the second temperature is increased with respect to the polysilazane film 210 in the water vapor atmosphere 212 that satisfies a predetermined condition. The oxidation treatment is applied. The water vapor pressure (partial pressure) in the water vapor atmosphere 212 is equal to or lower than the pressure of the first oxidation treatment and is 20 to 40 Kpa. The temperature of the water vapor atmosphere 212 is 500 to 580 ° C. The processing time is, for example, about 10 minutes. The second oxidation treatment is performed at a pressure equal to or lower than the pressure of the first oxidation treatment and at a temperature higher than that of the first oxidation treatment. That is, the pressure and temperature ranges and the reasons for the second oxidation treatment of the present embodiment are the same as those of the second oxidation treatment of the first embodiment.

  In the case where the isolation trench is formed after forming the gate of the transistor by the conventional process, the gate bird's beak 102bk is generated in the silicon regions 101 and 112 above and below the end of the gate oxide film 102 as shown in FIG. To do. However, the gate bird's beak 102bk is suppressed by setting the upper limit of the pressure of the second oxidation treatment to 40 Kpa or less as in this embodiment. This contributes to element miniaturization. Further, thermal deterioration of the gate oxide film 102 due to a thermal process during the STI process is also suppressed.

  In the present embodiment, the first and second oxidation treatments are performed in the same diffusion furnace. Thereby, processing time is shortened and productivity is improved. Furthermore, in the present embodiment, the first and second oxidation treatments are performed by a batch type processing apparatus. Thereby, the processing amount per unit time can be increased.

[FIG. 19]
By the first and second oxidation treatments, impurities (carbon and hydrocarbons) in the polysilazane film 210 are removed, and part of the Si—N bonds in the polysilazane film 210 are converted into Si—O bonds. The film 210 is changed to a silicon oxide film 213.

  Thereafter, in order to further increase the densification of the silicon oxide film 21, high temperature annealing is performed. Typical conditions are an atmosphere of dry oxygen, a temperature of 900 ° C., and a time of 30 minutes. The nitrogen concentration in the silicon oxide film 213 after the annealing is 2%.

[FIG. 20]
The silicon oxide film 213 is polished by the CMP process using the silicon nitride film 204 as a stopper, and the surface is flattened. Since the silicon oxide film 213 is sufficiently densified, deterioration of the silicon oxide film 213 during the CMP process is suppressed.

  Thereafter, the flash memory shown in FIG. 21 is obtained through known steps such as a step of removing the silicon nitride film 204 and a step of forming an element such as a transistor by a wet process using hot phosphoric acid. In FIG. 20, 214 is an inter-gate electrode insulating film, 215 is a control gate electrode, 21 is a silicide layer, and 217 is an interlayer insulating film.

  The present invention is not limited to the first and second embodiments. For example, in the first embodiment, an example of a single layer film using a polysilazane film as a buried film of an element isolation trench has been shown. However, as in the second embodiment, an HDP-CVD silicon oxide film, a polysilazane film, A laminated film containing may be used. It is also possible to use a laminated film including an HTO film and a polysilazane film instead of the HDP-CVD silicon oxide film.

  In the above embodiment, the case where the present invention is applied to a polysilazane film used as an element isolation insulating film has been described. However, the present invention can also be applied to an insulating film for other uses such as an interlayer insulating film. is there.

  For example, the polysilazane film of the embodiment can be used instead of the HDP-CVD silicon oxide film used as the interlayer insulating film. In this case, unlike the case where the HDP-CVD silicon oxide film is formed, plasma damage does not occur on the region where the interlayer insulating film is formed. This prevents changes in the properties of the film in the region where the interlayer insulating film is formed, for example, the etching stopper film.

  In the above embodiment, the case where a silicon substrate is used as the substrate has been described. However, an SOI substrate or a silicon substrate including a SiGe region can also be used.

  Further, in the above embodiment, the case of a NAND type flash memory has been described, but the present invention can also be applied to a flash memory other than a NAND type (for example, a NOR type). Furthermore, the present invention can be applied to a semiconductor device other than a flash memory.

  The embodiment described above is summarized as follows.

(1) A method for manufacturing a semiconductor device includes a step of applying a solution containing a perhydrogenated silazane polymer on a substrate, a step of heating the solution to form a film containing a perhydrogenated silazane polymer, And oxidizing the film in a water vapor atmosphere under reduced pressure to change the film to an insulating film containing silicon and oxygen.

(2) In the above (1), the insulating film is an element isolation insulating film or an interlayer insulating film.

(3) In the above (1) or (2), the oxidation treatment includes a first oxidation treatment and a second oxidation treatment, and the second oxidation treatment is a pressure equal to or lower than the pressure of the first oxidation treatment. And at a higher temperature than the first oxidation treatment.

(4) A method of manufacturing a semiconductor device includes a step of forming an element isolation groove on a surface of a semiconductor substrate, a solution containing a perhydrogenated silazane polymer is applied on the semiconductor substrate, and the element isolation groove is formed with the solution. A step of embedding, a step of heating the solution to form a film containing a perhydrogenated silazane polymer that embeds the element isolation trench, and oxidizing the film in a water vapor atmosphere under reduced pressure. And changing to an insulating film containing silicon and oxygen.

(5) In the above (4), the method further includes a step of forming a gate insulating film that is element-isolated in the element isolation trench before the film is oxidized in the steam atmosphere under reduced pressure.

(6) In the above (4) or (5), before applying a solution containing a perhydrogenated silazane polymer on the semiconductor substrate, a part of the element isolation trench is formed in a silicon oxide film by an HDP-C6VD process. The method further includes the step of embedding.

(7) In any one of the above (1) to (6), the oxidation treatment includes a first oxidation treatment performed at a pressure of 20 KPa to 40 KPa and a second oxidation treatment performed at a pressure of 20 KPa to 40 KPa. And the pressure of the second oxidation treatment is set to be equal to or lower than the pressure of the first oxidation treatment.

(8) In the above (7), the first oxidation treatment is performed at a temperature of 220 ° C. to 280 ° C., and the second oxidation treatment is performed at a temperature of 500 ° C. to 580 ° C.

(9) In the above (8), the method further includes a step of wet etching the insulating film or a step of polishing the insulating film.

(10) In any one of the above (7) to (9), the first oxidation treatment and the second oxidation treatment are continuously performed in the same apparatus.

(11) In any one of the above (7) to (10), the first oxidation treatment and the second oxidation treatment are performed in a batch diffusion furnace.

(12) In any one of the above (7) to (11), the first oxidation treatment is constant after the temperature in the diffusion furnace into which the substrate or the semiconductor substrate is introduced reaches 220 ° C. to 280 ° C. After a lapse of time, a step of introducing a water vapor atmosphere into the diffusion furnace is included.

  Furthermore, the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

  In addition, various modifications can be made without departing from the scope of the present invention.

Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment following FIG. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment following FIG. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment following FIG. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment following FIG. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment following FIG. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment following FIG. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment following FIG. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment following FIG. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 2nd Embodiment following FIG. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 2nd Embodiment following FIG. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 2nd Embodiment following FIG. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 2nd Embodiment following FIG. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 2nd Embodiment following FIG. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 2nd Embodiment following FIG. FIG. 18 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the second embodiment following FIG. 17. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 2nd Embodiment following FIG. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 2nd Embodiment following FIG. Sectional drawing which shows the semiconductor device which concerns on 2nd Embodiment. The figure which shows the relationship between the in-plane uniformity of the film thickness of the oxide film formed by oxidizing a bare silicon wafer in water vapor | steam atmosphere, and a pressure. The figure which shows the relationship between C density | concentration and the pressure of the oxide film formed by oxidizing a bare silicon wafer in water vapor | steam atmosphere. The figure which shows the relationship between the density of the oxide film formed by oxidizing a bare silicon wafer in water vapor | steam atmosphere, and temperature. The figure which shows the relationship between C density | concentration and temperature of the oxide film formed by oxidizing a bare silicon wafer in water vapor | steam atmosphere. The figure which shows the relationship between the film thickness of an oxide film formed by oxidizing a bare silicon wafer in water vapor | steam atmosphere, and a pressure. Sectional drawing which shows the gate bird's beak in the case of making after a gate. Sectional drawing which shows the gate bird's beak in the case of gate point making. The figure which shows the relationship between C density | concentration and temperature of the oxide film formed by oxidizing a bare silicon wafer in water vapor | steam atmosphere. The figure which shows the relationship between the oxide film thickness of the oxide film formed by oxidizing a bare silicon wafer in water vapor | steam atmosphere, and temperature.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 101 ... Silicon substrate, 102 ... Gate oxide film, 103 ... Silicon nitride film, 104 ... CVD silicon oxide film, 105 ... Resist pattern, 106 ... Groove, 107 ... Thermal oxide film, 108 ... Polysilazane film, 109 ... Water vapor atmosphere, 110 DESCRIPTION OF SYMBOLS ... Steam atmosphere, 111 ... Silicon oxide film, 112 ... Floating gate electrode, 113 ... Inter-gate electrode insulating film, 114 ... Control gate electrode, 115 ... Silicide layer, 116 ... Interlayer insulating film, 201 ... Silicon substrate, 202 ... Gate oxidation Film 203: Polycrystalline silicon film (floating gate electrode) 204 ... Silicon nitride film 205 ... CVD silicon oxide film 206 ... Resist pattern 207 ... Groove 208: Thermal oxide film 209 ... HDP-CVD silicon oxide film 210 ... polysilazane film, 211 ... water vapor atmosphere, 212 ... water vapor atmosphere, 13 ... silicon oxide film, 214 ... gate insulating film, 215 ... control gate electrode, 216 ... silicide layer, 217 ... interlayer insulating film.

Claims (5)

Applying a solution containing a perhydrogenated silazane polymer on a substrate;
Heating the solution to form a film comprising a perhydrogenated silazane polymer;
And a step of oxidizing the film in a water vapor atmosphere under reduced pressure to change the film into an insulating film containing silicon and oxygen. The oxidation treatment includes a first oxidation treatment and a second oxidation treatment,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the second oxidation treatment is performed at a pressure equal to or lower than the pressure of the first oxidation treatment, and is performed at a higher temperature than the first oxidation treatment. The oxidation treatment includes a first oxidation treatment performed at a pressure of 20 KPa to 40 KPa, and a second oxidation treatment performed at a pressure of 20 KPa to 40 KPa, and the pressure of the second oxidation treatment is set to the first oxidation treatment. The method of manufacturing a semiconductor device according to claim 1, wherein the pressure is set to be equal to or lower than a pressure of the oxidation treatment. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the first oxidation treatment is performed at a temperature of 220 ° C. to 280 ° C., and the second oxidation treatment is performed at a temperature of 500 ° C. to 580 ° C. 5. 5. The method of manufacturing a semiconductor device according to claim 3, wherein the first oxidation treatment and the second oxidation treatment are continuously performed in the same apparatus.

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