JP2006269479A - Process for fabricating semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To inspect characteristics of a semiconductor element without performing FIB.
A method of manufacturing a semiconductor device according to the present invention includes a step of forming a semiconductor device on a product semiconductor substrate, and forming a monitor semiconductor device on a monitor semiconductor substrate 11 to electrically connect the monitor semiconductor device. And a step of inspecting characteristics. The step of inspecting the electrical characteristics of the monitoring semiconductor device includes the step of forming the insulating film 20 on the monitoring semiconductor element, and the insulating film 20 is arranged in a layout different from the connection holes of the semiconductor device. A step of forming second connection holes 20d, 20e, 20f located on the semiconductor element, and an electrode 22d connected to the monitoring semiconductor element on the insulating film 20 via the second connection holes 20d, 20e, 20f , 22e, 22f, and a step of connecting a test terminal to the electrodes 22d, 22e, 22f and inputting a signal.
[Selection] Figure 3

Description

  The present invention relates to a method for manufacturing a semiconductor device. In particular, the present invention relates to a method for manufacturing a semiconductor device capable of inspecting characteristics of a semiconductor element without performing fine processing by FIB (Focused Ion Beam).

  FIG. 7A is a cross-sectional view for explaining the structure of a conventional semiconductor device. The semiconductor device illustrated in this drawing includes a first transistor 100a and a second transistor 100b. The drain 107c of the first transistor 100a also serves as the source of the second transistor 100b.

A first interlayer insulating film 108 and a second interlayer insulating film 111 are stacked on the first transistor 100a and the second transistor 100b, respectively. Tungsten plugs 109a and 109b are embedded in the first interlayer insulating film 108, respectively. The tungsten plug 109 a connects the Al alloy wiring 110 a formed on the first interlayer insulating film 108 and the source 107 a of the first transistor, and the tungsten plug 109 b is formed on the first interlayer insulating film 108. The formed Al alloy wiring 110b and the drain 107b of the second transistor are connected.
An Al alloy pad 112 and a passivation film 113 are formed on the second interlayer insulating film 111.

  By the way, in order to inspect whether or not the manufacturing conditions of the semiconductor device are appropriate, it is necessary to measure the characteristics of the manufactured semiconductor device and confirm whether or not the measurement result is a desired value. .

  FIG. 7B is a cross-sectional view for describing a method for inspecting the characteristics of the first transistor 100a and the characteristics of the second transistor 100b in the semiconductor device having the structure of FIG. In order to measure the characteristics of the first transistor 100a and the characteristics of the second transistor 100b, first, the passivation film 113, the Al alloy pad 112, and the second interlayer insulating film 111 are polished and removed, and an Al alloy wiring is obtained. Each of 110a and 110b is exposed.

  Next, using FIB, a connection hole located on the drain 107c is formed in the remaining film of the second interlayer insulating film 111 and the first interlayer insulating film 108, and a tungsten plug 109c is embedded in this connection hole. Next, on the remaining film of the second interlayer insulating film 111, electrodes 114a and 114b connected to the Al alloy wirings 110a and 110b, respectively, and an electrode 114c connected to the tungsten plug 109c are formed.

After that, by connecting a test terminal (not shown) to each of the electrodes 114a and 114c, the characteristics of the first transistor 100a are measured, and by connecting the terminal to each of the electrodes 114b and 114c, the second The characteristics of the transistor 100b are measured. Each of the electrodes 114a, 114b, and 114c is formed larger than the Al alloy wirings 110a and 110b so that the terminals can be easily brought into contact with each other (see Patent Document 1).
JP-A-5-67633 (FIG. 3 and 13th paragraph)

  In the above method, in order to inspect the characteristics of the semiconductor device, it is necessary to perform microfabrication using FIB. For this reason, there is a possibility that a semiconductor element such as a transistor may be damaged, and a characteristic of the semiconductor element may be deteriorated (for example, a parasitic capacitance or a resistance may be added).

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of inspecting the characteristics of a semiconductor element without performing fine processing by FIB. There is.

In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a semiconductor device on a semiconductor substrate for products,
Forming a semiconductor device for monitoring on the semiconductor substrate for monitoring, and inspecting the electrical characteristics of the semiconductor device for monitoring, and inspecting the formation conditions of the semiconductor device;
Comprising
The step of forming the semiconductor device includes:
Forming a semiconductor element on the semiconductor substrate for products;
Forming a first insulating film on the semiconductor element;
Forming in the first insulating film a first connection hole disposed in a first layout and positioned on the semiconductor element;
Forming a wiring connected to the semiconductor element via the first connection hole on the first insulating film;
Comprising
The step of inspecting the formation conditions of the semiconductor device includes:
Forming a monitoring semiconductor element on the monitoring semiconductor substrate;
Forming a second insulating film on the monitoring semiconductor element;
Forming a plurality of second connection holes disposed in the second insulating film in a second layout different from the first layout and positioned on the monitoring semiconductor element;
Forming a plurality of electrodes connected to the monitoring semiconductor element via the plurality of second connection holes on the second insulating film; and inputting a signal by connecting a testing terminal to the electrodes The process of carrying out.

  According to this method for manufacturing a semiconductor device, the layout of the second connection holes formed in the second insulating film is different from the layout of the first connection holes formed in the first insulating film. Different. Therefore, the monitoring semiconductor device can be inspected for a portion different from the semiconductor device. Therefore, it is not necessary to perform fine processing by FIB by inspecting the monitoring semiconductor device instead of the semiconductor element.

The step of forming the semiconductor element includes a step of forming a first transistor and a second transistor that functions as a source of the drain of the first transistor,
The step of forming the monitoring semiconductor element includes: a first monitoring transistor; a second monitoring transistor whose drain is the source of the first monitoring transistor; and the first and second transistors. Comprising the step of forming under the same conditions,
In the step of forming the first connection hole, the first connection hole is formed on a source of the first transistor and on a drain of the second transistor;
In the step of forming the second connection hole, the second connection hole may be formed on each of the source and drain of the first monitor transistor and on the drain of the second monitor transistor. Good.

  In this case, the characteristics of the first transistor and the characteristics of the second transistor cannot be independently checked. However, by connecting the inspection terminals to the electrodes connected to the source and drain of the first monitoring transistor, the first monitoring transistor can be connected without fine processing by FIB. The characteristics can be examined as a substitute for the characteristics of the first transistor.

  Also, the characteristics of the second transistor cannot be independently examined. However, the step of connecting the inspection terminal to the electrode includes connecting the inspection terminal to the electrode connected to the drain of the first monitoring transistor and the drain of the second monitoring transistor, respectively. By doing so, the characteristics of the second monitor transistor can be inspected as a substitute for the characteristics of the second transistor without performing fine processing by FIB.

The step of forming the semiconductor element includes the step of forming a transistor,
The step of forming the monitoring semiconductor element comprises the step of forming a monitoring transistor under the same conditions as the transistor,
In the step of forming the first connection hole, the first connection hole is formed on each of two impurity regions serving as a source and a drain of the transistor,
In the step of forming the second connection hole, the second connection hole may be formed on the monitoring impurity region which is the source or drain of the monitoring transistor, two spaced apart from each other.

  In this way, the characteristics of the monitoring impurity region can be inspected as a substitute for the characteristics of the impurity region without performing fine processing by FIB.

The step of forming the semiconductor element includes the step of forming a transistor,
The step of forming the monitoring semiconductor element comprises the step of forming a monitoring transistor under the same conditions as the transistor,
In the step of forming the first connection hole, the first connection hole is formed on a gate electrode of the transistor,
In the step of forming the second connection hole, the second connection hole may be formed on the monitor gate electrode of the monitor transistor so as to be separated from each other.

  In this way, the characteristics of the monitoring gate electrode can be inspected as a substitute for the characteristics of the gate electrode without performing fine processing by FIB.

The step of forming the monitoring semiconductor element includes the step of forming a first conductivity type well in the monitoring semiconductor substrate;
Forming a second conductivity type monitoring impurity region in the well;
Comprising
In the step of forming the second connection hole, the second connection hole may be formed on the well and on the monitoring impurity region under the same conditions as the first connection hole.

  When a mask shift occurs when forming the second connection hole, the second connection hole to be located on the monitoring impurity region is located on the well. In this case, the plurality of electrodes are conducted through the well. For this reason, the mask displacement when forming the second connection hole can be detected as a substitute for the mask displacement when forming the first connection hole without performing fine processing by FIB.

In the step of forming the monitoring impurity region, a plurality of the monitoring impurity regions are formed in the well at positions separated from each other,
In the step of forming the second connection hole, the second connection hole may be formed on each of the plurality of impurity regions and at different positions from the well.
In this way, it is possible to finely inspect the mask displacement when forming the dummy connection hole by examining which electrode is conducting.

  In the semiconductor device manufacturing method described above, in the step of forming the electrode, it is preferable that the width of the electrode is wider than the width of the wiring.

BEST MODE FOR CARRYING OUT THE INVENTION

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a flowchart for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. First, a product semiconductor device is manufactured using a product silicon substrate (S2). When the number of manufacturing times exceeds a certain number (or the running time of the apparatus exceeds a certain time) (S4: Yes), a monitoring semiconductor element is manufactured using a monitoring silicon substrate, and the characteristics of the semiconductor element are inspected. To do. If the characteristics are out of the specified range, the manufacturing conditions of the semiconductor device are adjusted (S6).

  Each drawing in FIG. 2 is a cross-sectional view for explaining in detail a manufacturing process (S2 in FIG. 1) of a semiconductor device for a product. First, as shown in FIG. 2A, a first conductivity type well 40a is formed in a silicon substrate 1. Next, a groove is formed in the silicon substrate 1, and the element isolation film 2 is embedded in the groove. The element isolation film 2 may be formed by a LOCOS method.

  Next, the silicon substrate 1 is thermally oxidized. Thus, the gate insulating film 3a of the first transistor and the gate insulating film 3b of the second transistor are formed on the silicon substrate 1, respectively.

  Next, a polysilicon film is formed on the entire surface including the gate insulating films 3a and 3b by the CVD method. Next, a photoresist film is applied on the polysilicon film, and this photoresist film is exposed and developed. Thereby, a resist pattern is formed on the polysilicon film. Next, the polysilicon film is etched using the resist pattern as a mask. As a result, the gate electrode 4a of the first transistor is formed on the gate insulating film 3a, and the gate electrode 4b of the second transistor is formed on the gate insulating film 3b. Thereafter, the resist pattern is removed.

  Next, a second conductivity type impurity is introduced into the silicon substrate 1 using the gate electrodes 4a and 4b and the element isolation film 2 as a mask. As a result, the low concentration impurity region 6a of the first transistor and the low concentration impurity region 6b of the second transistor are formed in the silicon substrate 1, respectively.

  Next, a silicon oxide film is formed on the entire surface including the gate electrodes 4a and 4b, and the silicon oxide film is etched back. Thereby, side walls 5a and 5b are formed on the side walls of the gate electrodes 4a and 4b, respectively.

Next, a second conductivity type impurity is introduced into the silicon substrate 1 using the sidewalls 5a and 5b, the gate electrodes 4a and 4b, and the element isolation film 2 as a mask. As a result, impurity regions 7a and 7b serving as the source and drain of the first transistor and impurity regions 7c serving as the drain of the second transistor are formed in the silicon substrate 1, respectively. The impurity region 7b of the first transistor also functions as the source of the second transistor.
In this way, the first transistor and the second transistor are formed on the silicon substrate 1.

  Next, as shown in FIG. 2B, a first interlayer insulating film 20 is formed on the entire surface including the first and second transistors by a CVD method. Next, a photoresist film (not shown) is formed on the first interlayer insulating film 20, and this photoresist film is exposed and developed using a reticle. Thereby, a resist pattern is formed on the first interlayer insulating film 20. Next, the first interlayer insulating film 20 is etched using this resist pattern as a mask. As a result, a connection hole 20a located on the impurity region 7a of the first transistor and a connection hole 20b located on the impurity region 7c of the second transistor are formed in the first interlayer insulating film 20. Thereafter, the resist pattern is removed.

  Next, a tungsten film is formed in each of the connection holes and on the first interlayer insulating film 20 by a CVD method. Next, the tungsten film located on the first interlayer insulating film 20 is polished and removed by the CMP method. Thereby, tungsten plugs 21a and 21b are formed in the connection holes 20a and 20b, respectively.

  Next, an Al alloy film is formed on each of the above tungsten plugs and on the first interlayer insulating film 20 by a sputtering method. Next, a photoresist film is applied on the Al alloy film, and the photoresist film is exposed and developed. Thereby, a resist pattern is formed on the Al alloy film. Next, the Al alloy film is etched using this resist pattern as a mask. Thereby, Al alloy wirings 22 a and 22 b are formed on the first interlayer insulating film 20. Al alloy wirings 22a and 22b are connected to tungsten plugs 21a and 21b, respectively.

  Next, a second interlayer insulating film 23 is formed on the first interlayer insulating film 20 and each of the Al alloy wirings 22a and 22b by a CVD method. Next, connection holes 23 a and 23 b located on the Al alloy wirings 22 a and 22 b are formed in the second interlayer insulating film 23. The method for forming these connection holes is the same as the method for forming the connection holes in the first interlayer insulating film 20.

  Next, tungsten plugs 24a and 24b are embedded in the connection holes 23a and 23b, respectively. The method of embedding the tungsten plug in these connection holes is the same as the method of embedding the tungsten plug in the connection hole of the first interlayer insulating film 20.

  Next, an Al alloy film is formed by sputtering on the second interlayer insulating film 23 and the tungsten plugs 24a and 24b. Next, a photoresist film (not shown) is applied on the Al alloy film, and this photoresist film is exposed and developed. Thereby, a resist pattern is formed on the Al alloy film. Next, the Al alloy film is etched using this resist pattern as a mask. As a result, Al alloy pads 25 a and 25 b connected to the tungsten plugs 24 a and 24 b are formed on the second interlayer insulating film 23. Thereafter, the resist pattern is removed.

  Next, a passivation film 26 in which a silicon oxide film and a silicon nitride film are stacked in this order is formed on the second interlayer insulating film 23 and the Al alloy pads 25a and 25b. Next, a photoresist film (not shown) is applied on the passivation film 26, and this photoresist film is exposed and developed. Thereby, a resist pattern is formed on the passivation film 26. Next, the passivation film 26 is etched using this resist pattern as a mask. As a result, openings are formed in the passivation film 26 on the Al alloy pads 25a and 25b. Thereafter, the resist pattern is removed.

  The semiconductor device formed in this manner includes a first transistor and a second transistor. The impurity region 7b serving as the drain of the first transistor also serves as the source of the second transistor. Further, the tungsten plug and the electrode are not formed on the impurity region 7b. For this reason, the characteristics of the first transistor and the characteristics of the second transistor cannot be independently examined. However, as shown below, by manufacturing a semiconductor element for monitoring and using this semiconductor element, the characteristics of the first transistor and the characteristics of the second transistor can be independently examined.

  3A and 3B describe in detail a method for manufacturing a first monitor semiconductor element on the monitor silicon substrate 11 and a method for inspecting the semiconductor element (S6 in FIG. 1). FIG. FIG. 3C is a plan view of the semiconductor device in the state of FIG.

  First, as shown in FIG. 3A, a second conductivity type well 40b is formed in a silicon substrate 11 for monitoring, and an element isolation film 12 is embedded in the silicon substrate 11. These forming methods and forming conditions are the same as the forming methods and forming conditions of the well 40a and the element isolation film 2 shown in FIG.

  Next, the gate insulating film 13a of the first monitoring transistor and the gate insulating film 13b of the second monitoring transistor are formed on the silicon substrate 11, respectively. Next, the gate electrode 14a of the first monitoring transistor is formed on the gate insulating film 13a, and the gate electrode 14b of the second monitoring transistor is formed on the gate insulating film 13b. These forming methods and forming conditions are the same as the forming methods and forming conditions of the gate insulating films 3a and 3b and the gate electrodes 4a and 4b in FIG.

  Next, the low concentration impurity region 16a of the first monitor transistor and the low concentration impurity region 16b of the second monitor transistor are formed on the silicon substrate 11, respectively. These forming methods and forming conditions are the same as the forming methods and forming conditions of the low-concentration impurity regions 6a and 6b in FIG.

  Next, side walls 15a and 15b are formed on the side walls of the gate electrodes 14a and 14b, respectively. These forming methods and forming conditions are the same as the forming methods and forming conditions of the sidewalls 5a and 5b in FIG.

  Next, impurity regions 17a and 17b serving as the source and drain of the first monitoring transistor and an impurity region 17c serving as the drain of the second monitoring transistor are formed on the silicon substrate 11. The impurity region 17b of the first monitor transistor also serves as the source of the second monitor transistor. The formation method and formation conditions of the impurity regions 17a, 17b, and 17c are the same as the formation method and formation conditions of the impurity regions 7a, 7b, and 7c in FIG.

  In this way, the first monitoring transistor and the second monitoring transistor are formed on the monitoring silicon substrate 11. These monitoring transistors have the same structure as the first transistor and the second transistor shown in FIG.

  Next, as shown in FIG. 3B, a first interlayer insulating film 20 is formed on the entire surface including the first monitoring transistor and the second monitoring transistor by a CVD method. Next, connection holes 20d, 20e, and 20f located on the impurity regions 17a, 17b, and 17c, respectively, are formed on the first interlayer insulating film 20. Next, tungsten plugs 21d, 21e, and 21f are embedded in the connection holes 20d, 20e, and 20f, respectively. These forming methods and forming conditions are the same as the forming methods and forming conditions of the connection holes 20a and 20b and the tungsten plugs 21a and 21b in FIG.

  Next, an Al alloy film is formed on each of the above tungsten plugs and on the first interlayer insulating film 20 by a sputtering method. Next, a photoresist film is applied on the Al alloy film, and the photoresist film is exposed and developed. Thereby, a resist pattern is formed on the Al alloy film. Next, the Al alloy film is etched using this resist pattern as a mask. Thus, Al alloy pads 22d, 22e, and 22f are formed on the first interlayer insulating film 20. The Al alloy pads 22d, 22e, and 22f are connected to the tungsten plugs 21d, 21e, and 21f, respectively.

  Next, the characteristics of the first monitoring transistor are inspected by connecting a terminal 50 for inspection to each of the Al alloy pads 22d and 22e and inputting a signal. Further, the characteristics of the second monitor transistor are inspected by connecting a test terminal 50 to each of the Al alloy pads 22e and 22f and inputting a signal. When the characteristics of the first monitoring transistor or the characteristics of the second monitoring transistor are outside the specified range, the manufacturing conditions of the semiconductor device are adjusted.

  Here, as shown in FIG. 3C, since no other wiring or the like is formed on the first interlayer insulating film 20, each of the Al alloy pads 22d, 22e, and 22f can be made sufficiently large ( For example, the width is made larger than the width of the Al alloy wiring 22a shown in FIG. For this reason, the inspection terminal 50 can be easily connected to each of the Al alloy pads 22d, 22e, and 22f in the inspection process described later.

  As described above, according to the first monitoring semiconductor element, the tungsten plug and the Al alloy pad connected to the tungsten plug are provided on the impurity regions 17a, 17b, and 17c of the first monitoring transistor and the second monitoring transistor, respectively. Is formed. Therefore, the characteristics of the first monitoring transistor and the characteristics of the second monitoring transistor can be measured independently without performing microfabrication using FIB. Therefore, it is possible to determine whether or not the manufacturing conditions of the semiconductor device are appropriate without performing microfabrication using FIB.

  Further, since each of the Al alloy pads 22d, 22e, and 22f connected to the dummy transistor can be made sufficiently large, the inspection terminal 50 can be easily connected to the Al alloy pads 22d, 22e, and 22f.

  FIG. 4 is a cross-sectional view for explaining in detail a method for manufacturing a second monitor semiconductor element on the monitor silicon substrate 11 and a method for inspecting the semiconductor element (S6 in FIG. 1). Hereinafter, the same components as those in the example shown in FIG. In this example, the formation conditions of the impurity regions to be the source and drain are inspected.

  First, the well 40b, the element isolation film 2, the gate insulating films 13a and 13b, the gate electrodes 14a and 14b, the side walls 15a and 15b, the low-concentration impurity regions 16a and 16b, and the impurity regions 17a, 17b, and 17c are formed. A first monitoring transistor and a second monitoring transistor are formed. Next, a first interlayer insulating film 20 is formed on the entire surface including the first monitoring transistor and the second monitoring transistor. These forming methods and forming conditions are the same as those in the example shown in FIG. However, the impurity region 17c is wider than the example shown in FIG.

  Next, connection holes 20 f and 20 g are formed in the first interlayer insulating film 20. Each of the connection holes 20f and 20g is located on the impurity region 17c and is separated from each other. The method and conditions for forming these connection holes are the same as the method for forming the connection holes in the first interlayer insulating film 20 and the formation conditions at this time in the example shown in FIG.

  Next, tungsten plugs 21f and 21g are embedded in the connection holes 20f and 20g, respectively. The method of filling these tungsten plugs is the same as the method of filling the tungsten plugs in the connection holes of the first interlayer insulating film 20 in the example shown in FIG.

  Next, Al alloy pads 22 f and 22 g are formed on the first interlayer insulating film 20. The Al alloy pads 22f and 22g are connected to the tungsten plugs 21f and 21g and are sufficiently large. These forming methods are the same as the method of forming an Al alloy pad on the first interlayer insulating film 20 in the example shown in FIG.

  Next, an inspection terminal 50 is connected to each of the Al alloy pads 22f and 22g, and a signal is input to inspect the electrical characteristics (for example, resistance) of the impurity region 17c. If the electrical characteristics of the impurity region 17c are outside the specified range, the manufacturing conditions of the impurity region are adjusted.

  As described above, according to the second monitoring semiconductor element, it is possible to determine whether or not the electrical characteristics of the impurity region are within a specified range without performing microfabrication using FIB. If it is outside the specified range, the manufacturing conditions (for example, impurity concentration) of the impurity region can be adjusted. Further, since the Al alloy pads 22f and 22g are sufficiently large, the inspection terminals can be easily connected to the Al alloy pads 22f and 22g, respectively.

  FIG. 5 is a cross-sectional view for explaining in detail a method for manufacturing a third monitor semiconductor element on the monitor silicon substrate 11 and a method for inspecting the semiconductor element (S6 in FIG. 1). In this example, the formation condition of the gate electrode is inspected. Hereinafter, the same components as those in the example shown in FIG. FIG. 5 shows a cross section in a direction orthogonal to the respective drawings in FIG. 3, that is, in a direction in which the gate electrode extends.

  First, after forming 40b on the silicon substrate 1, the element isolation film 2 is embedded. Next, the gate insulating film 13a, the gate electrode 14a, the sidewall 15a (not shown in this figure), the low concentration impurity region (not shown in this figure), the impurity region (not shown in this figure), and the first The interlayer insulating film 20 is formed. These forming methods and forming conditions are the same as those in the example shown in FIG.

  Next, connection holes 20 h and 20 i are formed in the first interlayer insulating film 20. Each of the connection holes 20h and 20i is located on the gate electrode 14a and is separated from each other. The method and conditions for forming these connection holes are the same as the method for forming the connection holes in the first interlayer insulating film 20 and the formation conditions in the example shown in FIG.

  Next, tungsten plugs 21h and 21i are embedded in the connection holes 20h and 20i, respectively. The method of filling these tungsten plugs is the same as the method of filling the tungsten plugs in the connection holes of the first interlayer insulating film 20 in the example shown in FIG.

  Next, Al alloy pads 22 h and 22 i are formed on the first interlayer insulating film 20. The Al alloy pads 22h and 22i are connected to the tungsten plugs 21h and 21i, respectively. These forming methods are the same as the method of forming an Al alloy pad on the first interlayer insulating film 20 in the example shown in FIG. Each of the Al alloy pads 22h and 22i is formed sufficiently large.

  Next, an inspection terminal 50 is connected to each of the Al alloy pads 22h and 22i, and a signal is input to inspect the electrical characteristics of the gate electrode 14a (for example, resistance). If the electrical characteristics of the gate electrode 14a are outside the specified range, the manufacturing conditions of the gate electrode 4a are adjusted.

  As described above, according to the third monitoring semiconductor element, it is possible to determine whether or not the electrical characteristics of the gate electrode are within a specified range without performing microfabrication using FIB. If it is out of the specified range, the manufacturing conditions of the gate electrode can be adjusted. Further, since the Al alloy pads 22h and 22i are sufficiently large, the inspection terminals can be easily connected to the Al alloy pads 22h and 22i, respectively.

  FIGS. 6A and 6B are cross-sectional views for explaining in detail a method for manufacturing a fourth monitoring semiconductor element and a method for inspecting the semiconductor element (S6 in FIG. 1). FIG. 6C is a plan view for explaining the layout of the connection holes in the state of FIG. Hereinafter, the same components as those in the example shown in FIG.

  First, as shown in FIG. 6A, after forming the first conductivity type well 40b in the silicon substrate 1, the element isolation film 2 is embedded. Next, a photoresist film (not shown) is applied to the entire surface including the well 40b, and this photoresist film is exposed and developed. As a result, a resist pattern 60 is formed on the silicon substrate 1. Next, a second conductivity type impurity is introduced into the silicon substrate 1 using the resist pattern 60 and the element isolation film 2 as a mask. As a result, impurity regions 17d, 17e, and 17f that are separated from each other are formed in the well 40b. The formation conditions of the impurity regions 17d, 17e, and 17f are the same as the formation conditions of the impurity regions 17a, 17b, and 17c in FIG. 3, for example.

  Thereafter, as shown in FIG. 6B, the resist pattern 60 is removed. Next, a first interlayer insulating film 20 is formed by a CVD method. Next, connection holes 20j, 20k, 20l, and 20m are formed in the first interlayer insulating film 20. The connection hole 20j is located on the well 40b, and the connection holes 20k, 20l, and 20m are located on the impurity regions 17d, 17e, and 17f, respectively. The formation method and formation conditions of these connection holes are the same as the method and formation conditions of forming the connection holes in the first interlayer insulating film 20 in the example shown in FIG.

  Next, tungsten plugs 21j, 21k, 21l, and 21m are embedded in the connection holes 20j, 20k, 20l, and 20m, respectively. The method of filling these tungsten plugs is the same as the method of filling the tungsten plugs in the connection holes of the first interlayer insulating film 20 in the example shown in FIG.

  Here, the layout of each of the connection holes 20k, 20l, and 20m and the tungsten plugs 21k, 21l, and 21m will be described with reference to FIG. These connection holes and tungsten plugs are located above the impurity regions 17d, 17e, and 17f that are square, but have different distances to the well 40b. Specifically, the connection hole 20k and the tungsten plug 21k are located in the vicinity of the upper left corner of the impurity region 17d, and the connection hole 20l and the tungsten plug 21l are located at the center of the impurity region 17e. 21m is located near the lower right corner of the impurity region 17f.

  When the connection hole is formed in the first interlayer insulating film 20 and the mask displacement in the left direction or the upward direction in the figure is more than a certain value, all of the connection hole and the tungsten plug are in the left direction or the upward direction in the figure. As a result, the tungsten plug 21k is positioned on the well 40b. Further, when the mask displacement is further large, each of the tungsten plugs 21k and 21l is located on the well 40b.

  In addition, when forming a connection hole in the first interlayer insulating film 20, if the mask displacement in the right direction or the downward direction in the drawing occurs more than a certain value, the tungsten plug 21m is placed on the well 40b for the same reason as described above. Located in. Further, when the mask displacement is further large, each of the tungsten plugs 21l and 21m is located on the well 40b.

  For this reason, it is possible to measure the mask displacement when the connection hole is formed in the first interlayer insulating film 20 by inspecting whether or not the electrode 22j in the dummy area 10b is electrically connected to the other electrode. . That is, the inspection terminal 50 is connected to any one of the Al alloy pads 22k, 22l, and 22m and the Al alloy pad 22j, and it is inspected whether or not they are electrically connected.

  When the mask displacement when forming the connection holes 20a and 20b is the left direction or the upward direction in FIG. 6C and the size is a certain value or more, the tungsten plug 21k is positioned on the well 40b. Therefore, the Al alloy pads 22j and 22k are electrically connected to each other through the well 40b. When the mask displacement is further large, the tungsten plug 21l is also located on the well 40b, so that the Al alloy pads 22j and 22l are electrically connected to each other via the well 40b.

  Further, when the mask displacement when forming the connection holes 20a and 20b is rightward or downward in FIG. 6C and its size is a certain value or more, the tungsten plug 21m is placed on the well 40b. Therefore, the Al alloy pads 22j and 22m are electrically connected to each other through the well 40b. When the mask displacement is further large, the tungsten plug 21l is also located on the well 40b, so that the Al alloy pads 22j and 22l are electrically connected to each other via the well 40b.

  As described above, according to the present embodiment, by checking whether the Al alloy pad 22j is electrically connected to any of the Al alloy pads 22k, 22l, and 22m, or is not electrically connected to any of the Al alloy pads 22k, the mask displacement is prevented. Direction and size can be estimated. When a mask displacement is detected, the mask displacement can be corrected by adjusting the position of the reticle and the exposure conditions when exposing the photoresist film on the first interlayer insulating film 20.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.

9 is a flowchart for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. (A) is sectional drawing for demonstrating the manufacturing process (S2 of FIG. 1) of the semiconductor device for products in detail, (B) is sectional drawing for demonstrating the next process of (A). (A) is sectional drawing for demonstrating the method to manufacture the semiconductor element for 1st monitors, (B) is sectional drawing for demonstrating the next process of (A), (C) is (B). FIG. Sectional drawing for demonstrating the method to manufacture the semiconductor element for 2nd monitors Sectional drawing for demonstrating the method to manufacture the semiconductor element for 3rd monitors (A) is sectional drawing for demonstrating the method for manufacturing the semiconductor element for 4th monitors, (B) is sectional drawing for demonstrating the next process of (A), (C) is (B). FIG. (A) is sectional drawing for demonstrating the structure of the conventional semiconductor device, (B) is sectional drawing for demonstrating the method to test | inspect the semiconductor device of (A).

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Element isolation film, 3a, 3b, 13a, 13b ... Gate insulating film, 4a, 4b, 14a, 14b ... Gate electrode, 5a, 5b, 15a, 15b ... Side wall, 6a, 6b, 16a , 16b ... low-concentration impurity regions, 7a, 7b, 7c, 17a, 17b, 17c, 17d, 17e, 17f ... impurity regions, 20 ... first interlayer insulating film, 20a, 20b, 20d, 20e, 20f, 20g, 20h, 20i, 20j, 20k, 20l, 20m ... connection hole, 21a, 21b, 21d, 21e, 21f, 21g, 21h, 21i, 21j, 21k, 21l, 21m ... tungsten plug, 22a, 22b ... Al alloy wiring, 22d, 22e, 22f, 22g, 22h, 22i, 22j, 22k, 22l, 22m ... Al alloy pad, 23 ... second Interlayer insulating film, 23a, 23b ... connection hole, 24a, 24b ... tungsten plug, 25a, 25b ... Al alloy pad, 26 ... passivation film, 40a, 40b ... well, 50 ... terminal, 60 ... resist pattern, 100a ... first Transistor 100b ... second transistor 107a ... source 107b, 107c ... drain 108 ... first interlayer insulating film 109a, 109b, 109c ... tungsten plug 110a, 110b ... Al alloy wiring 111 ... second Interlayer insulating film, 112 ... Al alloy pad, 113 ... passivation film, 114a, 114b, 114c ... electrode

Claims (9)

Forming a semiconductor device on a semiconductor substrate for products;
Forming a semiconductor device for monitoring on the semiconductor substrate for monitoring, and inspecting the electrical characteristics of the semiconductor device for monitoring, and inspecting the formation conditions of the semiconductor device;
Comprising
The step of forming the semiconductor device includes:
Forming a semiconductor element on the semiconductor substrate for products;
Forming a first insulating film on the semiconductor element;
Forming in the first insulating film a first connection hole disposed in a first layout and positioned on the semiconductor element;
Forming a wiring connected to the semiconductor element via the first connection hole on the first insulating film;
Comprising
The step of inspecting the formation conditions of the semiconductor device includes:
Forming a monitoring semiconductor element on the monitoring semiconductor substrate;
Forming a second insulating film on the monitoring semiconductor element;
Forming a plurality of second connection holes disposed in the second insulating film in a second layout different from the first layout and positioned on the monitoring semiconductor element;
Forming a plurality of electrodes connected to the monitoring semiconductor element via each of the plurality of second connection holes on the second insulating film; and connecting a test terminal to the electrodes to send a signal Input process;
A method for manufacturing a semiconductor device comprising: The step of forming the semiconductor element includes a step of forming a first transistor and a second transistor that functions as a source of the drain of the first transistor,
The step of forming the monitoring semiconductor element includes: a first monitoring transistor; a second monitoring transistor whose drain is the source of the first monitoring transistor; and the first and second transistors. Comprising the step of forming under the same conditions,
In the step of forming the first connection hole, the first connection hole is formed on a source of the first transistor and on a drain of the second transistor;
In the step of forming the second connection hole, the second connection hole is formed on each of the source and drain of the first monitoring transistor and on the drain of the second monitoring transistor. A method for manufacturing a semiconductor device according to claim 1.   The step of connecting an inspection terminal to the electrode comprises the step of connecting the inspection terminal to the electrode connected to the source and drain of the first monitoring transistor, respectively. A method for manufacturing a semiconductor device.   The step of connecting the inspection terminal to the electrode includes the step of connecting the inspection terminal to the electrode connected to the drain of the first monitoring transistor and the drain of the second monitoring transistor, respectively. The manufacturing method of the semiconductor device of Claim 2 which comprises these. The step of forming the semiconductor element includes the step of forming a transistor,
The step of forming the monitoring semiconductor element comprises the step of forming a monitoring transistor under the same conditions as the transistor,
In the step of forming the first connection hole, the first connection hole is formed on each of two impurity regions serving as a source and a drain of the transistor,
2. In the step of forming the second connection hole, the second connection hole is formed on the monitor impurity region which becomes the source or drain of the monitor transistor, and is formed two apart from each other. The manufacturing method of the semiconductor device of description. The step of forming the semiconductor element includes the step of forming a transistor,
The step of forming the monitoring semiconductor element comprises the step of forming a monitoring transistor under the same conditions as the transistor,
In the step of forming the first connection hole, the first connection hole is formed on a gate electrode of the transistor,
2. The semiconductor device according to claim 1, wherein in the step of forming the second connection hole, the second connection hole is formed on the monitor gate electrode of the monitor transistor so as to be spaced apart from each other. Production method. The step of forming the monitoring semiconductor element includes the step of forming a first conductivity type well in the monitoring semiconductor substrate;
Forming a second conductivity type monitoring impurity region in the well;
Comprising
2. In the step of forming the second connection hole, the second connection hole is formed on each of the well and the monitoring impurity region under the same condition as the first connection hole. The manufacturing method of the semiconductor device as described in 2 .. In the step of forming the monitoring impurity region, a plurality of the monitoring impurity regions are formed in the well at positions separated from each other,
8. The semiconductor device according to claim 7, wherein, in the step of forming the second connection hole, the second connection hole is formed on each of the plurality of impurity regions and at a position where the distance from the well is different from each other. .   The method for manufacturing a semiconductor device according to claim 1, wherein in the step of forming the electrode, the width of the electrode is made wider than the width of the wiring.

Images