CN118841402B - Semiconductor test structure and semiconductor test method - Google Patents
Semiconductor test structure and semiconductor test method Download PDFInfo
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- CN118841402B CN118841402B CN202411328560.XA CN202411328560A CN118841402B CN 118841402 B CN118841402 B CN 118841402B CN 202411328560 A CN202411328560 A CN 202411328560A CN 118841402 B CN118841402 B CN 118841402B
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- 238000012360 testing method Methods 0.000 title claims abstract description 120
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 238000010998 test method Methods 0.000 title abstract description 9
- 238000005259 measurement Methods 0.000 claims abstract description 98
- 238000002955 isolation Methods 0.000 claims abstract description 68
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims description 27
- 238000005530 etching Methods 0.000 claims description 22
- 238000010586 diagram Methods 0.000 description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 16
- 229920005591 polysilicon Polymers 0.000 description 15
- 229920002120 photoresistant polymer Polymers 0.000 description 14
- 239000010409 thin film Substances 0.000 description 11
- 238000000206 photolithography Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention provides a semiconductor test structure and a semiconductor test method, wherein the semiconductor test structure comprises a substrate, a plurality of shallow trench isolation regions, a plurality of semiconductor test structures and a semiconductor test structure, wherein the substrate is provided with a well region and a plurality of shallow trench isolation regions; the device comprises a shallow trench isolation region, a plurality of measurement structure groups, a test voltage end and a plurality of test grid electrodes, wherein the measurement structure groups comprise grid electrodes to be measured and an active region, the grid electrodes to be measured are arranged on the surface of the shallow trench isolation region, the active region is arranged on the top of a well region and is positioned on one side of the shallow trench isolation region, the plurality of grid electrodes to be measured are electrically connected to the test voltage end, current values are measured on the active region, and the leakage position of the grid electrodes to be measured is determined based on the measured current values. The invention can determine the measurement structure group with the electric leakage phenomenon and the measurement structure group without the electric leakage phenomenon.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a semiconductor test structure and a semiconductor test method.
Background
In the semiconductor process, shallow trench isolation (STI, shallow trench isolation) is often used to perform process isolation, so that a recess region is formed at the boundary between the shallow trench isolation region and the active region. After the polysilicon thin film layer is formed, the polysilicon thin film layer at the position of the concave area is distorted, and after the polysilicon thin film layer is etched to form a grid electrode, the polysilicon residue is easy to occur at the position of the concave area. When the interval between the grid electrode and the active region is smaller, the residual polysilicon at the position of the concave region can cause the grid electrode and the active region to generate short circuit to generate leakage phenomenon, so that the circuit is invalid. However, in the prior art, a specific position of the gate leakage cannot be determined. Therefore, there is a need for improvement.
Disclosure of Invention
The invention provides a semiconductor test structure and a semiconductor test method, which are used for solving the technical problem that the specific position of grid leakage cannot be judged in the prior art.
The invention provides a semiconductor test structure, comprising:
The substrate is provided with a well region and a plurality of shallow trench isolation regions, the shallow trench isolation regions are positioned on the well region, and the bottoms of the well regions are continuous;
A plurality of measurement structure groups, wherein the measurement structure groups comprise a grid electrode to be measured and an active region, the grid electrode to be measured is arranged on the surface of the shallow trench isolation region, the active region is arranged on the top of the well region and is positioned at one side of the shallow trench isolation region, and
The grid electrode to be tested is electrically connected to the test voltage end, a current value is measured on the active area, and the leakage position of the grid electrode to be tested is determined based on the measured current value.
In an embodiment of the present invention, the gate to be tested includes a first gate and a second gate, a plurality of the first gates and/or a plurality of the second gates are electrically connected to the test voltage terminal, a current value is measured on the active area, and a leakage position of the first gate and/or the second gate is determined based on the measured current value.
In one embodiment of the present invention, in the measurement structure group, a path direction along the first gate, the active region, and the second gate is denoted as an alignment direction;
When the first grid electrodes are electrically connected to the test voltage end, the measured current value on the active area is larger than the normal current value, or when the second grid electrodes are electrically connected to the test voltage end, the measured current value on the active area is larger than the normal current value, the first grid electrodes or the second grid electrodes are determined to deviate in the alignment direction.
In one embodiment of the present invention, when the plurality of first gates are electrically connected to the test voltage terminal, the measured current value on the active area is greater than the normal current value, and when the plurality of second gates are electrically connected to the test voltage terminal, the measured current value on the active area is greater than the normal current value, it is determined that the measurement structure group is deviated in etching process.
In one embodiment of the invention, in the set of measurement structures, the active region is located between the first gate and the second gate.
In one embodiment of the present invention, in the measurement structure set, a distance between the active region and the first gate or the second gate is set to be zero or 10nm to 100nm.
The invention also provides a semiconductor test method, which comprises the following steps:
providing a substrate, forming a well region on the surface of the substrate, and forming a plurality of shallow trench isolation regions on the well region, wherein the bottoms of the well regions are continuous;
Forming a grid electrode to be tested on the surface of the shallow trench isolation region, and forming an active region on the surface of the well region, wherein the active region is arranged on the top of the well region and is positioned on one side of the shallow trench isolation region;
Grouping and marking a plurality of gates to be measured and a plurality of active areas as a plurality of measurement structure groups, wherein the measurement structure groups comprise the gates to be measured and the active areas;
and electrically connecting a plurality of grids to be tested to a test voltage end, measuring current values on the active area, and determining the leakage position of the grids to be tested based on the measured current values.
In one embodiment of the present invention, the grouping of the plurality of gates under test and the plurality of active regions into a plurality of measurement structure groups, the measurement structure groups including the gates under test and the active regions, includes:
an active region is formed on the surface of the well region between two adjacent gates to be tested, so that two gates to be tested are arranged between the two adjacent active regions;
The grid electrode to be detected on one side of the active region is marked as a first grid electrode, and the grid electrode to be detected on the other side of the active region is marked as a second grid electrode;
The first grid electrode, the active region and the second grid electrode are marked as one measuring structure group, and a plurality of first grid electrodes, a plurality of active regions and a plurality of second grid electrodes are grouped into a plurality of measuring structure groups.
In one embodiment of the present invention, the step of electrically connecting the plurality of gates to be tested to a test voltage terminal, measuring a current value on the active area, and determining a leakage position of the gates to be tested based on the measured current value includes:
in the measurement structure group, the path direction along the first grid electrode, the active region and the second grid electrode is marked as an alignment direction;
Electrically connecting the first gates to the test voltage terminal, when the measured current value on the active region is larger than the normal current value, or electrically connecting the second gates to the test voltage terminal, and when the measured current value on the active region is larger than the normal current value, determining that the first grid electrode or the second grid electrode is deviated in the alignment direction.
In one embodiment of the present invention, the step of electrically connecting the plurality of gates to be tested to a test voltage terminal, measuring a current value on the active area, and determining a leakage position of the gates to be tested based on the measured current value includes:
Electrically connecting a plurality of first grid electrodes to the test voltage end, when the measured current value on the active area is larger than the normal current value, and electrically connecting a plurality of second grid electrodes to the test voltage end, and determining that the measurement structure group deviates in etching process when the measurement current value on the active area is larger than the normal current value.
The semiconductor test structure and the semiconductor test method have the beneficial effects that the grid electrode to be tested in the plurality of measurement structure groups is electrically connected to the test voltage end, and the current value is measured on the active area. If the grid electrode to be measured in the measurement structure group has a leakage phenomenon, the grid electrode to be measured, the well region and the active region are conducted, and leakage current is generated. If the grid electrode to be measured in the measurement structure group does not generate leakage phenomenon, the grid electrode to be measured, the well region and the active region are not conducted, and leakage current is not generated. The invention performs electrical test on a plurality of measurement structure groups to determine the measurement structure groups with electric leakage and the measurement structure groups without electric leakage.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of an electron microscope in a semiconductor structure provided in the prior art.
Fig. 2 is a schematic diagram of a leakage current 50 between a gate and an active region in a semiconductor structure according to the prior art.
Fig. 3 is a schematic diagram illustrating the positions of a gate and an active region in a semiconductor structure according to the prior art.
Fig. 4 is a schematic diagram showing the positions of the gate and the active region in another semiconductor structure according to the prior art.
Fig. 5 is a schematic diagram illustrating connection of a semiconductor test structure according to an embodiment of the invention.
Fig. 6 is a schematic diagram illustrating connection of another semiconductor test structure according to an embodiment of the invention.
FIG. 7 is a schematic cross-sectional view of A-A in FIG. 5 according to an embodiment of the present invention.
Fig. 8 is a schematic structural diagram of a substrate according to an embodiment of the present invention.
Fig. 9 is a schematic structural diagram of etching a substrate to form a shallow trench isolation region according to an embodiment of the present invention.
FIG. 10 is a schematic diagram of a structure for depositing Shallow Trench Isolation (STI) regions according to one embodiment of the present invention.
FIG. 11 is a schematic diagram of polishing a shallow trench isolation according to an embodiment of the present invention.
Fig. 12 is a schematic structural diagram of an active region formed by ion implantation of a well region according to an embodiment of the present invention.
Fig. 13 is a schematic structural diagram of forming a polysilicon thin film layer on the surfaces of an active region and a shallow trench isolation region according to an embodiment of the present invention.
Fig. 14 is a schematic structural diagram of forming photoresist on a surface of a polysilicon thin film layer according to an embodiment of the present invention.
Fig. 15 is a schematic structural diagram of etching a polysilicon thin film layer to form a gate according to an embodiment of the present invention.
Fig. 16 is a schematic structural diagram of forming a dielectric layer on the surfaces of an active region, a shallow trench isolation region and a gate according to an embodiment of the present invention.
Fig. 17 is a schematic structural diagram of forming a sidewall by dry etching a dielectric layer according to an embodiment of the present invention.
Fig. 18 is a schematic diagram of a leakage current 50 between the gate and the active region in fig. 17 according to an embodiment of the present invention.
Fig. 19 is a schematic diagram illustrating steps of a semiconductor testing method according to an embodiment of the invention.
Fig. 20 is a schematic diagram of step S30 in fig. 19 according to an embodiment of the invention.
Fig. 21 is a schematic diagram illustrating a step S40 in fig. 19 according to an embodiment of the invention.
Description of the reference numerals
10. The device comprises a substrate, 110, a well region, 120, a shallow trench isolation region, 20, a polycrystalline silicon film layer, 210, a concave region, 220, a gate to be tested, 230, a dielectric layer, 240, a side wall, 30, an active region, 310, a contact hole, 410, a first test voltage, 420, a second test voltage, 50, leakage current 50, 510, a gap, 60 and photoresist.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
In the following description, numerous details are set forth in order to provide a more thorough explanation of embodiments of the present invention, it will be apparent, however, to one skilled in the art that embodiments of the present invention may be practiced without these specific details, in other embodiments, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the embodiments of the present invention.
Referring to fig. 5 to 21, the present invention provides a semiconductor test structure and a semiconductor test method, which can be applied in the field of shallow trench isolation (STI, shallow trench isolation) process of a semiconductor, and can determine the leakage position of a gate 220 to be tested by measuring the current value between the gate 220 to be tested and an active region 30. The present invention analyzes whether the polysilicon remaining at the position of the recess 210 between the gate 220 to be tested and the active region 30 will cause a short circuit between the gate 220 to be tested and the active region 30. The following detailed analysis is performed by specific examples.
Referring to fig. 5, 6 and 7, in one embodiment of the present invention, a semiconductor test structure is provided, which may include a substrate 10, a set of measurement structures and a test voltage terminal. Wherein the substrate 10 may be provided with a well region 110 and a shallow trench isolation region 120, the shallow trench isolation region 120 is located on the well region 110, and the bottom of the well region 110 is continuous. The measurement structure set may include a gate 220 to be measured and an active region 30, the gate 220 to be measured may be disposed on a surface of the shallow trench isolation region 120, and the active region 30 may be disposed on top of the well region 110 and on one side of the shallow trench isolation region 120. The gate 220 to be tested is electrically connected to the test voltage terminal, and the current value is measured on the active region 30.
Specifically, as shown in fig. 7, the substrate 10 (Sub) serves as a reference plane and a mechanical support, and device structures such as a well region 110, a shallow trench isolation region 120, a gate 220 to be tested, and an active region 30 may be formed on the surface of the substrate 10. In the field of cmos, when a plurality of nmos and pmos are required to be simultaneously formed on a substrate 10, a local substrate is formed for one type of transistor, which is called a well region 110. In the present embodiment, the well region 110 is formed on the substrate 10, and the bottom of the well region 110 is made continuous.
Specifically, as shown in fig. 7, shallow trench isolation (STI, shallow trench isolation) 120 is used for a process below 0.25um, and a silicon nitride mask may be used to deposit, pattern, etch silicon to form a trench, and fill the trench with deposited oxide to isolate the deposited oxide from the silicon. In this embodiment, the shallow trench isolation region 120 can be used to prevent the gate under test 220 on top of it from generating leakage current.
Referring to fig. 5 and 6, in an embodiment of the present invention, the number of measurement structure sets may be plural, and electrical tests may be performed on the plural measurement structure sets to determine the measurement structure set with the leakage phenomenon and the measurement structure set without the leakage phenomenon. The gates 220 to be tested in the plurality of measurement structure sets are electrically connected to the test voltage terminal, and the current value is measured on the Active Area (AA) 30. For example, all the gates under test 220 or a portion of the gates under test 220 in the plurality of measurement structure sets are electrically connected to a test voltage terminal, and the test voltage terminal is used to provide a voltage to the gates under test 220 and measure a current value on the active region 30.
Of course, more than two test voltage terminals may be provided, for example, the test voltage terminals include a first test voltage 410 and a second test voltage 420. Part of the gates 220 to be tested in the plurality of measurement structure groups are electrically connected to the first test voltage 410, and other gates 220 to be tested in the plurality of measurement structure groups are electrically connected to the second test voltage 420, and measurement current values corresponding to the first test voltage 410 and the second test voltage 420 can be respectively obtained on the active region 30.
Because the bottom of the well region 110 is continuous, the test voltage terminal is used to provide the voltage to the gate 220 to be tested, and if the gate 220 to be tested, the well region 110 and the active region 30 are conductive, the gate 220 to be tested in the measurement structure set will generate the leakage current 50. The test voltage terminal is used for providing voltage to the gate 220 to be tested, and if the gate 220 to be tested, the well region 110 and the active region 30 are not conductive, the gate 220 to be tested in the measurement structure set will not generate leakage phenomenon, and the leakage current 50 will not be generated.
Specifically, as shown in fig. 5 and 7, the dimension of the gate 220 to be measured along the source and drain (not shown) directions is referred to as the length (L) of the gate 220 to be measured, and the dimension of the gate 220 to be measured along the source and drain directions is referred to as the width (W) of the gate 220 to be measured. The gates 220 to be tested in the plurality of measurement structure sets are electrically connected to the test voltage terminal, and the current value is measured on the active region 30. If the measured current value of the active region 30 in some of the measurement structure groups is greater than the normal current value, and the measured current value of the active region 30 in other measurement structure groups is equal to the normal current value, it is determined that the alignment deviation of the gate 220 to be measured in the measurement structure groups in the length direction thereof occurs only if the measurement structure groups corresponding to the measured current value greater than the normal current value are indicated to have the leakage phenomenon.
Specifically, the gate 220 to be tested in the plurality of measurement structure sets is electrically connected to the test voltage terminal, and the current value is measured on the active region 30. If the measured current value on the active region 30 in all the measurement structure groups is greater than the normal current value, it is determined that all the measurement structure groups have deviation in etching process, which indicates that all the measurement structure groups have leakage.
In one embodiment of the present invention, the number of gates 220 and active regions 30 to be measured in the set of measurement structures is not limited. For example, in one measurement structure group, the number of gates 220 to be measured is one, and the number of active regions 30 is one. When the electrical test is performed on the gates 220 to be tested in the plurality of measurement structure groups, one gate 220 to be tested corresponds to one active region 30.
As another example, as shown in fig. 7, in one measurement structure group, the number of gates 220 to be measured is two, and the number of active regions 30 is one. The active region 30 may be located between two gates under test 220, where the gate under test 220 on one side of the active region 30 is denoted as a first gate and the gate under test 220 on the other side of the active region 30 is denoted as a second gate. When the electrical test is performed on the to-be-tested gate 220 in the plurality of measurement structure sets, the plurality of first gates or the plurality of second gates are electrically connected to the test voltage terminal, and the current value is measured on the active area 30, so as to improve the test efficiency of the to-be-tested gate 220. In other embodiments, the number of the gates 220 and the active regions 30 to be measured in one measurement structure group may be adjusted accordingly.
Referring to fig. 5, 6 and 7, in one embodiment of the present invention, in the measurement structure set, a path direction along the first gate, the active region 30 and the second gate is denoted as an alignment direction. The gates 220 to be tested are electrically connected to the test voltage terminals, for example, a first test voltage 410 may be set on the first gates and a second test voltage 420 may be set on the second gates. The first test voltage 410 is set on the plurality of first gates, the measured current value on the active region 30 is greater than the normal current value, and the second test voltage 420 is set on the plurality of second gates, and when the measured current value on the active region 30 is equal to the normal current value, it indicates that the first gates deviate in the alignment direction. The first gate, the well region 110, and the active region 30 are conductive, and a leakage current 50 is generated.
Or the second test voltage 420 is set on the plurality of second gates, the measured current value on the active region 30 is greater than the normal current value, and the first test voltage 410 is set on the plurality of first gates, and when the measured current value on the active region 30 is equal to the normal current value, it indicates that the second gates deviate in the alignment direction. The second gate, the well region 110, and the active region 30 are conductive, and a leakage current 50 is generated.
Referring to fig. 5, 6 and 7, in one embodiment of the present invention, a first test voltage 410 is set on a plurality of first gates, a measured current value on the active region 30 is greater than a normal current value, and a second test voltage 420 is set on a plurality of second gates, wherein when the measured current value on the active region 30 is greater than the normal current value, it indicates that the measured structure group deviates in etching process. The first gate, the well region 110, and the active region 30 are conductive, and the second gate, the well region 110, and the active region 30 are conductive, thereby generating the leakage current 50.
Referring to fig. 5, 6 and 7, in one embodiment of the present invention, in the measurement structure set, the distance between the active region 30 and the gate 220 to be measured is set to zero or 10 nm-100 nm, the bottoms of the well regions 110 are continuous, adjacent active regions 30 are connected by the well regions 110 at the bottoms, and the adjacent active regions 30 are separated by the shallow trench isolation regions 120 in the horizontal direction.
Referring to fig. 8 to 18, a specific preparation process of the semiconductor test structure according to the present invention is shown below.
Referring to fig. 8, in the cmos field, when a plurality of nmos and pmos devices are required to be simultaneously formed on a substrate 10, a local substrate, referred to as a well 110, is formed for one type of transistor. In this embodiment, the substrate 10 (Sub) serves as a reference plane and a mechanical support, the well region 110 may be formed on the surface of the substrate 10, and the bottom of the well region 110 is made continuous. A Photoresist (PR) 60 may be formed on the surface of the well region 110, and the photoresist 60 may cause the exposed portion of the well region 110 surface to be removed during etching.
Referring to fig. 9, in an embodiment of the present invention, the well region 110 and the photoresist 60 are subjected to photolithography and etching processes, so that shallow trench isolation (STI, shallow trench isolation) regions 120 are formed on the well region 110, and the number of the shallow trench isolation regions 120 may be plural.
Referring to fig. 10, in one embodiment of the present invention, the shallow trench isolation region 120 may be filled with a deposited oxide such that the deposited oxide is isolated from the silicon. That is, by opening the shallow trench isolation region 120 on the well region 110, the gate 220 to be tested on top of the shallow trench isolation region 120 is prevented from generating leakage current during the subsequent process. After filling the deposited oxide in the shallow trench isolation region 120, the photoresist 60 may be removed.
Referring to fig. 11, in one embodiment of the present invention, after the photoresist 60 is removed, a chemical mechanical Polishing (CMP, chemical Mechanical Polishing) process may be performed on the well 110 and the shallow trench isolation 120 to planarize the surfaces of the well 110 and the shallow trench isolation 120.
Referring to fig. 12, in an embodiment of the present invention, an Active Area (AA) 30 is formed on the surface of the well 110 by Ion Implantation (IMP), a source, a drain, a gate, and other structures of a field effect transistor are formed on the Active Area 30, and two adjacent Active areas 30 are isolated by a shallow trench isolation region 120.
Referring to fig. 13, in one embodiment of the present invention, a polysilicon thin film layer 20 is formed on the surfaces of the well region 110, the shallow trench isolation region 120, and the active region 30. As shown in fig. 14, a photoresist 60 may be formed on the surface of the polysilicon thin film layer 20, the photoresist 60 may be located over the shallow trench isolation region 120, and the width of the photoresist 60 is smaller than the width of the shallow trench isolation region 120. Photoresist 60 may cause the exposed portions of the surface of polysilicon film layer 20 to be removed during etching.
Referring to fig. 15, in an embodiment of the present invention, the polysilicon thin film layer 20 and the photoresist 60 are subjected to photolithography and etching processes, so that a gate 220 to be tested is formed on top of the shallow trench isolation region 120, and the width of the gate 220 to be tested is smaller than the width of the shallow trench isolation region 120.
Referring to fig. 16, in one embodiment of the present invention, photoresist 60 is removed and a dielectric layer 230 is formed on the surfaces of active region 30, well 110, and gate under test 220. As shown in fig. 17, by using the characteristic of dry etching anisotropy, the dielectric layer 230 is dry etched, so that a sidewall (spacer) 240 is formed at a step position between the gate 220 to be tested and the well region 110. The side wall 240 plays a role in protecting the side wall of the gate 220 to be tested, and can be used for preventing the surface of the gate 220 to be tested from being damaged, and prolonging the service time of the gate 220 to be tested.
Referring to fig. 18, a contact hole 310 is formed in the active region 30 and the gate 220 to be tested, and a metal wire is connected in the contact hole 310, so that an electrical test can be performed on the active region 30 and the gate 220 to be tested by the metal wire, and a leakage position of the gate 220 to be tested is determined based on a measured current value.
Referring to fig. 5, 7 and 18, in one embodiment of the present invention, if the gate 220 to be tested is not deviated in the length (L) direction thereof or the gate 220 to be tested is not deviated in the etching process, i.e. the gate 220 to be tested is formed in the normal process, the measured current value on the active area 30 is equal to the normal current value when the plurality of gates 220 to be tested are electrically connected to a test voltage terminal. When the gate 220 to be measured deviates in the length (L) direction thereof or when the gate 220 to be measured deviates in the etching process, that is, the gate 220 to be measured is formed in the deviated process, as shown in fig. 3 and 4, the gap 510 between the gate 220 to be measured and the active region 30 is too small, so that the gate 220 to be measured is conducted with the active region 30. As shown in fig. 2, the leakage current 50 is formed among the gate 220 to be tested, the recess region 210 and the active region 30, and the measured current value on the active region 30 is larger than the normal current value when the recess region 210 is located between the gate 220 to be tested and the active region 30.
Specifically, when the gate 220 to be tested is deviated in the length (L) direction thereof, even if the etching process of the gate 220 to be tested is changed, a conductive short circuit condition between the gate 220 to be tested and the active region 30 may occur. Therefore, the position and alignment accuracy of the gate 220 to be measured can be changed in the semiconductor process, so that the gap 510 between the gate 220 to be measured and the active region 30 can be normal, and the gate 220 to be measured and the active region 30 can be separated.
Specifically, when the gate 220 to be tested deviates in the etching process, the gate 220 to be tested is not turned on with the active region 30 due to the deviation of the gate 220 to be tested in the length (L) direction, so that the conducting short circuit condition between the gate 220 to be tested and the active region 30 still occurs by changing the position and alignment accuracy of the gate 220 to be tested. Therefore, the etching process of the gate 220 to be tested can be changed in the semiconductor manufacturing process, so that the gap 510 between the gate 220 to be tested and the active region 30 can be normal, and the gate 220 to be tested and the active region 30 can be separated.
Since the gate 220 to be measured is deviated in the length (L) direction thereof, the gate 220 to be measured is deviated in the etching process, which are two completely different technical problems, and the solutions thereof are also completely different. Therefore, in the case of a short circuit between the gate 220 to be tested and the active region 30, it is necessary to determine the specific reason for the conduction between the gate 220 to be tested and the active region 30, and to make different improvement measures.
Referring to fig. 7 to 19, in one embodiment of the present invention, a semiconductor testing method is provided, which includes the following specific steps.
Step S10, providing a substrate, forming a well region on the surface of the substrate, forming a plurality of shallow trench isolation regions on the well region, and enabling the bottoms of the well regions to be continuous.
And S20, forming a gate to be tested on the surface of the shallow trench isolation region, and forming an active region on the surface of the well region, wherein the active region is arranged on the top of the well region and is positioned at one side of the shallow trench isolation region.
And S30, grouping and marking a plurality of gates to be tested and a plurality of active areas into a plurality of measurement structure groups, wherein the measurement structure groups comprise the gates to be tested and the active areas.
Step S40, electrically connecting a plurality of grids to be tested to a test voltage end, measuring current values on the active area, and determining the leakage position of the grids to be tested based on the measured current values.
The analysis is described below by means of specific examples.
Step S10, providing a substrate, forming a well region on the surface of the substrate, forming a plurality of shallow trench isolation regions on the well region, and enabling the bottoms of the well regions to be continuous.
In one embodiment of the present invention, as shown in fig. 8, the well region 110 may be formed on the surface of the substrate 10, and the bottom of the well region 110 is made continuous. As shown in fig. 9, the well region 110 is subjected to photolithography and etching processes, so that shallow trench isolation regions 120 are formed on the well region 110, and the number of the shallow trench isolation regions 120 may be plural.
And S20, forming a gate to be tested on the surface of the shallow trench isolation region, and forming an active region on the surface of the well region, wherein the active region is arranged on the top of the well region and is positioned at one side of the shallow trench isolation region.
In one embodiment of the present invention, as shown in fig. 12, an active region 30 may be formed on the surface of the well region 110 by means of ion implantation, the active region 30 is disposed on the top of the well region 110 and located at one side of the shallow trench isolation region 120, and two adjacent active regions 30 are isolated by the shallow trench isolation region 120. As shown in fig. 13, a polysilicon thin film layer 20 is formed on the surfaces of the well region 110, the shallow trench isolation region 120, and the active region 30. As shown in fig. 14 and 15, the polysilicon thin film layer 20 is subjected to photolithography and etching processes, so that a gate 220 to be tested is formed on top of the shallow trench isolation region 120, and the width of the gate 220 to be tested is smaller than the width of the shallow trench isolation region 120.
And S30, grouping and marking a plurality of gates to be tested and a plurality of active areas into a plurality of measurement structure groups, wherein the measurement structure groups comprise the gates to be tested and the active areas.
In an embodiment of the present invention, the number of the measurement structure sets may be plural, and electrical tests may be performed on the plural measurement structure sets to determine the measurement structure set having the leakage phenomenon and the measurement structure set not having the leakage phenomenon. The gates 220 to be tested in the plurality of measurement structure sets are electrically connected to the test voltage terminal, and the current value is measured on the active region 30. Since the bottom of the well region 110 is connected, if the leakage phenomenon occurs in the gate 220 to be measured in the measurement structure set, the gate 220 to be measured, the well region 110 and the active region 30 are conducted, and a leakage current 50 is generated. If the gate 220 to be tested in the measurement structure set does not generate leakage, the gate 220 to be tested, the well region 110 and the active region 30 are not conducted, and no leakage current 50 is generated.
Step S40, electrically connecting a plurality of grids to be tested to a test voltage end, measuring current values on the active area, and determining the leakage position of the grids to be tested based on the measured current values.
In one embodiment of the present invention, the gate 220 to be tested in the plurality of measurement structure sets is electrically connected to the test voltage terminal, and the current value is measured on the active region 30.
Specifically, if the measured current value on the active region 30 in some of the measurement structure groups is greater than the normal current value, and the measured current value on the active region 30 in other measurement structure groups is equal to the normal current value, it is determined that the alignment deviation of the gate 220 to be measured in the measurement structure groups in the length direction thereof occurs only in the measurement structure groups corresponding to the measurement structure groups having the measured current value greater than the normal current value.
Specifically, if the measured current value on the active region 30 in all the measurement structure groups is greater than the normal current value, it is determined that all the measurement structure groups have deviation in the etching process, which indicates that all the measurement structure groups have leakage.
Referring to fig. 20, in an embodiment of the present invention, step S30 may include step S310, step S320 and step S330. In this step S310, the active region 30 is formed on the surface of the well region 110 between two adjacent gates 220 to be tested, so that two gates 220 to be tested are located between two adjacent active regions 30. Step S320 may be represented by marking the gate 220 to be measured on one side of the active region 30 as a first gate and marking the gate 220 to be measured on the other side of the active region 30 as a second gate. Step S330 may be represented by grouping the first gates, the active regions 30, and the second gates into a plurality of measurement structure groups.
Specifically, in one measurement structure group, the number of gates 220 to be measured is two, and the number of active regions 30 is one. The active region 30 may be located between two gates under test 220, where the gate under test 220 on one side of the active region 30 is denoted as a first gate and the gate under test 220 on the other side of the active region 30 is denoted as a second gate. When the electrical test is performed on the to-be-tested gate 220 in the plurality of measurement structure sets, the plurality of first gates or the plurality of second gates are electrically connected to the test voltage terminal, and the current value is measured on the active area 30, so as to improve the test efficiency of the to-be-tested gate 220.
Referring to fig. 21, in an embodiment of the present invention, step S40 may include step S410, step S420 and step S430. In the measurement structure set, the path direction along the first gate, the active region 30, and the second gate is denoted as the alignment direction in step S410. Step S420 may be represented by electrically connecting a plurality of first gates to the test voltage terminal, and determining that the measurement structure group is deviated in the alignment direction when the measured current value of the active region 30 is greater than the normal current, or electrically connecting a plurality of second gates to the test voltage terminal, and determining that the measured current value of the active region 30 is greater than the normal current. Step S430 may be expressed as electrically connecting the plurality of first gates to the test voltage terminal, determining that the measurement structure group is deviated in the etching process when the measured current value of the active region 30 is greater than the normal current, and electrically connecting the plurality of second gates to the test voltage terminal, wherein the measured current value of the active region 30 is greater than the normal current.
In summary, the present invention provides a semiconductor test structure and a semiconductor test method, which have the unexpected technical effects of electrically connecting the gates to be tested in the plurality of measurement structure sets to the test voltage terminal and measuring the current value on the active region. If the grid electrode to be measured in the measurement structure group has a leakage phenomenon, the grid electrode to be measured, the well region and the active region are conducted, and leakage current is generated. If the grid electrode to be measured in the measurement structure group does not generate leakage phenomenon, the grid electrode to be measured, the well region and the active region are not conducted, and leakage current is not generated. The invention performs electrical test on a plurality of measurement structure groups to determine the measurement structure groups with electric leakage and the measurement structure groups without electric leakage.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure. As used in the description herein and throughout the claims that follow, unless otherwise indicated, "a", "an", and "the" include plural references. Also, as used in the description herein and throughout the claims that follow, unless otherwise indicated, the meaning of "in..once again" includes "in..once again" and "on.
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