JP2006267942A - Drive unit of display device and liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide the drive unit of a display device, which can generate generate the most suitable driving signal even when being arbitrarily mounted by a user or the like. <P>SOLUTION: The drive unit of the display device has a driving signal generation part for generating a driving signal for driving the display device and drives the display device from the outside, and the drive unit includes a comparison part for comparing a test driving signal to be outputted to the display device by the driving signal generation part with a feedback signal outputted from the display device with respect to the test driving signal, and an adjustment part for setting the driving signal generation part on the basis of the comparison result of the comparison part. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a drive IC (external drive device) for driving a display panel from the outside of the panel.

  In order to reduce the cost of a display panel (for example, an LCD module), as shown in FIG. 8, a method of mounting an external drive device for the display panel on a circuit board on the user side has been proposed.

  First, an operation example of a display panel (LCD) and an external driving device for driving the display panel (LCD) will be briefly described with reference to FIG. As shown in the figure, the display panel 102 includes a source driver 103, a gate driver 105, source lines s1 to sn, gate lines g1 to gm, and thin film transistors Tr (1,1) to (n, m). With. The source driver 103 includes a source shift register 108 and a sampling (switch) circuit 118, and the gate driver 105 includes a gate shift register 109 and a sampling (switch) circuit 119. On the other hand, the external drive device 101 includes a drive signal generator 120 having a source drive signal generator 121 and a gate drive signal generator 122, a DA converter 111, and a level shifter 112, and a source on the display panel 102 side. The driver 103 and the gate driver 105 are controlled.

  The thin film transistors Tr (1, 1) to (n, m) of the display panel 102 are provided in the vicinity of intersections of the source lines s1 to sn and the gate lines g1 to gm. For example, near the intersection of the source line si (where i is an integer of 1 ≦ i ≦ n, and so on) and the gate line gj (where j is an integer of 1 ≦ j ≦ m, and so on). Tr (i, j) is provided. The thin film transistor Tr (i, j) has its source electrode connected to the source line si, its gate electrode connected to the gate line gj, and its drain electrode connected to a pixel capacitor (not shown). A signal voltage from the source driver 103 is written into the pixel capacitor via the source line si and the source electrode and drain electrode of the thin film transistor Tr (i, j).

  The external driving device 101 converts externally input video data (digital data) into an analog signal by the DA converter 111, and sets the analog signal to a voltage level suitable for panel driving by the level shifter (or amplifier) 112, and also a source driver 103 and the gate driver 105 are controlled as follows.

  That is, based on an input signal from the video signal source 133 to the drive signal generator 120, the gate drive signal generator 122 outputs a gate drive signal to the gate driver 105, selects one arbitrary gate line gj, The drive signal generator 121 outputs a source drive signal to the shift register 108 to turn on / off the sampling (switch) circuit 118. Thus, video data (analog signal) for one line (gate line) output from the video signal source 133 via the DA converter 111 and the level shifter 112 is converted into the source lines s1 to sn and the thin film transistor Tr (1, j). Is written in each pixel capacity via .about. (N, j).

  By sequentially performing this process (process of one horizontal period) for all the gate lines (g1 to gm), signals are written to the pixel capacitors connected to all the thin film transistors Tr (1,1) to (n, m), and display is performed. The panel 102 is displayed.

  The source lines s1 to sn are driven by a method in which signals (potentials) are simultaneously applied from the sampling (switch) circuit 116 to all the source lines s1 to sn, or an arbitrary source line si is connected by the sampling (switch) circuit 116. Examples include a method of selecting and applying a signal voltage to the selected source line. Note that an appropriate circuit (for example, a latch circuit or a hold circuit) is provided in the display panel 102 or the external driving device 101 in accordance with each method.

  Returning to FIG. 8, when the external driving device 101 is mounted on a circuit board on the user (for example, set maker) side instead of the display panel (for example, the initial timing setting value is stored in the register of the external driving device 101. When the drive signal generator 121 reads a set value from the register as an initial setting before the start of driving and generates a drive signal based on the set value), the mounting state and arrangement state of the external drive device 101 are designed by the user. I will leave it to you.

  That is, the wiring resistance, parasitic capacitance, noise, etc. (see FIG. 6) between the external drive device 101 and the display panel 102 cannot be grasped in advance, and parameters related to signal transmission (signal delay time, etc., as shown in FIGS. 6 and 7). Graphs (a) to (c)) cannot be assumed (the above parameters are related to confidential information on the user side and are difficult to obtain). Therefore, it is very difficult to optimize the timing setting of the gate drive signal and the source drive signal. On the other hand, it is difficult to convey panel-specific parameters such as the wiring delay time of the display panel to the user side because it is related to confidential information on the panel side.

  Patent Document 1 discloses a configuration in which a delay adjustment circuit in which two or more delay circuits having different delay times are provided in parallel to detect the TFT characteristics and adjust the delay time of the clock signal as appropriate. Patent Document 2 discloses a control signal supplied to a terminal block in order to eliminate a shift in the phase relationship between a signal line selection period and a video signal due to variation in characteristics of TFTs constituting a shift register in a signal line driver. And a reference pulse are compared by a phase comparator, and a configuration is provided in which a phase correction circuit for correcting the phase of a clock pulse output from a timing controller according to the phase difference is disclosed. However, even if the configuration described in Patent Documents 1 and 2 can solve the problem caused by the characteristic variation of the TFT in the display device, the gate drive signal of the drive device (drive IC) arbitrarily mounted on the display device or The timing of the source drive signal cannot be optimized.

Therefore, when the driver IC is arbitrarily mounted on the user side, the drive timing is designed with a time margin (a margin that does not cause a problem even if the signal is slightly delayed) in the timing of the drive signal.
JP 2000-193934 A (publication date: July 14, 2000) JP 2001-228827 A (publication date: August 24, 2001)

  However, if there is a time margin in the timing of the drive signal in this way, there is a problem that power consumption increases and high-speed display of moving images and the like becomes difficult.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a display device drive device that can generate an optimal drive signal even if it is arbitrarily mounted by a user or the like.

  In order to solve the above-described problem, the display device drive device of the present invention includes a drive signal generation unit that generates a drive signal for driving the display device, and drives the display device from the outside. A drive signal generator for comparing a test drive signal output to the display device and a feedback signal from the display device with respect to the test drive signal, and a drive signal generation based on a comparison result of the comparator And an adjustment unit for setting the unit.

  According to the above configuration, the test drive signal and the feedback signal from the display device are compared in the comparison unit, and the adjustment unit sets the drive signal generation unit based on the comparison result. That is, a signal delay after being mounted by a user or the like is detected, and this is reflected in the generation of the drive signal. As a result, an optimum drive signal can be generated and output to the display device even if it is arbitrarily mounted by a user or the like. As a result, display quality improvement and power saving of the display device can be realized.

  The drive device for the display device includes a drive signal generation unit that generates a drive signal for driving the display device, and is a drive device for the display device that drives the display device from the outside. The generation unit may generate the drive signal based on a difference between the test drive signal output to the display device and a feedback signal from the display device with respect to the test drive signal. .

  In the display device drive device of the present invention, it is preferable that the comparison unit compares a phase shift between the test drive signal and the feedback signal. According to the above configuration, the signal delay can be detected with high accuracy.

  In the display device drive device of the present invention, it is preferable that the test drive signal is fed back after passing through a plurality of dummy wirings formed in the display device. According to the above configuration, the signal delay in the display device can be reflected in the adjustment of the drive signal generation unit.

  In the display device drive device of the present invention, the dummy wiring preferably includes a plurality of dummy wirings formed along the data signal lines. According to the above configuration, the signal delay in the data signal line can be reflected in the adjustment of the drive signal generation unit.

  In the display device drive device of the present invention, it is preferable that the dummy wiring includes a plurality of dummy wirings formed along the scanning signal lines. According to the above configuration, the signal delay in the scanning signal line can be reflected in the adjustment of the drive signal generation unit.

  In the display device driving device of the present invention, it is preferable that the dummy wiring includes a dummy wiring that passes through a pixel portion of a non-display area in the display device. According to the above configuration, it is possible to detect a delay caused by a component (for example, liquid crystal) of the pixel unit (for example, due to a parasitic capacitance of the liquid crystal), and reflect this in adjustment of the drive signal generation unit. Can do.

  The display device of the present invention is a display device that is driven by the drive device for the display device, and has a plurality of dummy wirings that can be connected to the drive device for the display device.

  In the display device, it is preferable that the dummy wiring includes a plurality of dummy wirings formed along the data signal lines.

  In the display device, it is preferable that the dummy wiring includes a plurality of dummy wirings formed along the scanning signal lines.

  The liquid crystal display device of the present invention is characterized by including the drive device for the display device.

  As described above, according to the present invention, the signal delay after being mounted by the user or the like can be accurately detected, and this can be reflected in the generation of the drive signal. As a result, an optimum drive signal can be generated even if it is arbitrarily mounted by a user or the like, and display quality can be improved and power can be saved.

  One embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a schematic diagram showing a configuration of a driving IC according to the present invention, FIG. 2 is a schematic diagram showing a configuration of a liquid crystal module according to the present invention, and FIG. 3 is a case where the liquid crystal module and the driving IC are mounted. It is a schematic diagram which shows the structure of these. Note that the liquid crystal module and the driving IC are suitable for a small and medium display device such as a mobile phone, a digital camera, and a PDA, and can be applied to an instrument panel of a vehicle.

  As shown in FIG. 2, the liquid crystal module 2 (display device / liquid crystal display device) includes a source driver 3, a gate driver 5, source lines S1 to Sn (data signal lines), and gate lines G1 to Gm (scanning). Signal lines), dummy lines (dummy wirings) Ds1, Ds2, and DL3 along the source lines, dummy lines (dummy wirings) Dg1, Dg2, and Dl3 along the gate lines, and thin film transistors TR (1, 1) to ( n, m). The source driver 3 includes a source shift register 8 and a sampling (switch) circuit 18, and the gate driver 5 includes a gate shift register 9 and a sampling (switch) circuit 19.

  The dummy lines (Ds1, Ds2, DL3, Dg1, Dg2, Dl3) are bus lines that are formed outside the display area 2x (non-display area) and are not related to the display itself. Its function is to output a signal voltage obtained by sampling the steep rise of the video signal in a dummy line (non-display area), and then use a stable signal in the display area so as not to affect the display. Or, when a disconnection occurs due to missing pattern of the source line and gate line at the time of manufacturing the liquid crystal module, the signal is bypassed using a dummy line to the part where the signal cannot be transmitted, and the signal is delivered to the original disconnection part, etc. There is a function. Each of the dummy lines may be originally provided because of the above function, or may be newly provided (separately) for driving signal adjustment.

  On the other hand, as shown in FIG. 1, the drive IC 1 (drive device of the display device) includes a drive signal generator 21 (drive signal generation unit), a phase comparator 23 (comparison unit), a decoder 24, a register 22, and an addition. A liquid crystal module having an optimum drive signal (gate drive signal / source drive signal) adjusted by the adjustment unit 29, including an adjustment unit 29 having an adjustment unit 25, a signal processing unit 33, a DA converter 11, and a level shifter 12. 2 source driver 3 and gate driver 5 are controlled. The drive IC 1 is configured separately from the liquid crystal module 2 and is optionally mounted on a user side substrate, for example.

  As shown in FIG. 2, the thin film transistors TR (1, 1) to (n, m) of the liquid crystal module 2 are provided in the vicinity of intersections of the source lines S1 to Sn and the gate lines G1 to Gm. For example, near the intersection of the source line Si (where i is an integer of 1 ≦ i ≦ n, and so on) and the gate line Gj (where j is an integer of 1 ≦ j ≦ m, and so on). TR (i, j) is provided. The thin film transistor TR (i, j) has its source electrode connected to the source line Si, its gate electrode connected to the gate line Gj, and its drain electrode connected to a pixel capacitor (not shown). A signal voltage from the source driver 3 is written into the pixel capacitor via the source line Si and the source electrode and drain electrode of the thin film transistor TR (i, j).

  Here, the dummy line Ds1 is supplied to the pixel portion of the non-display area (outside the display area 2x) located at one end (opposite side of the gate driver 5) in the direction along the gate line of the liquid crystal module 2. It is provided in parallel with the line. The dummy line Ds2 is provided in a non-pixel portion (a region not filled with liquid crystal outside the pixel portion 2y) so as to be parallel to the dummy line Ds1. The dummy line DL3 is provided outside the gate driver 5 (non-pixel portion) in parallel with the source line.

  Further, the dummy line Dg1 is formed in a pixel portion of a non-display area (outside of the display area 2x) located at one end portion in the direction along the source line of the liquid crystal module 2 (the opposite end portion of the source driver 5) It is provided in parallel with the gate line. The dummy line Dg2 is provided in a non-pixel portion (a region not filled with liquid crystal outside the pixel portion 2y) so as to be parallel to the dummy line Dg1. The dummy line Dl3 is provided outside the source driver 3 (non-pixel portion) in parallel with the gate line.

  Here, the dummy line Ds1 is connected to the source shift register 8 at one end and is connected to the dummy line Ds2 at the other end. The dummy line Ds2 is connected to the dummy line Dl3 at one end and is connected to the dummy line Ds1 at the other end. Further, one end of the dummy line DL3 can be connected to the connector, and the other end is connected to the dummy line Dg2. The dummy line Dg1 is connected to the gate shift register 9 at one end and to the dummy line Dg2 at the other end. The dummy line Dg2 is connected to the dummy line DL3 at one end and to the dummy line Dg1 at the other end. Further, one end of the dummy line D13 can be connected to the connector, and the other end is connected to the dummy line Ds2.

  Next, image display operations of the drive IC 1 and the liquid crystal module 2 will be described with reference to FIGS. In the present embodiment, the drive IC 1 and the liquid crystal module 2 are connected by a connector 30 (see FIG. 3).

  The drive IC 1 drives the source driver 3 and the gate driver 5 as follows. The signal processing unit 33 performs predetermined video processing on externally input video data (digital data), outputs the video data to the DA converter 11, and outputs a control signal to the drive signal generator 21. The DA converter 11 converts the video data input from the signal processing unit 33 into an analog signal and outputs the analog signal to the level shifter (or amplifier) 12. The level shifter 12 sets the analog signal (signal potential) to a voltage level suitable for panel driving.

  The drive signal generator 21 receives a control signal from the signal processing unit 33, outputs a gate drive signal to the gate shift register 9, and selects an arbitrary gate line Gj (all thin film transistors connected to the gate line Gj). The gate electrodes of TR (1, j) to (n, j) are turned ON). In synchronism with this, the drive signal generator 21 outputs a source drive signal to the source shift register 8 to turn the sampling (switch) circuit 18 on and off. Thereby, an analog signal (signal potential) for one line (gate line) from the level shifter 12 is written to each pixel capacitor via the source lines S1 to Sn and the thin film transistors TR (1, j) to (n, j). .

  By sequentially performing this process (process in one horizontal period) for all the gate lines (G1 to Gm), signals are written in the pixel capacitors connected to all the thin film transistors TR (1, 1) to (n, m), and the liquid crystal Module 2 is displayed.

  The source lines S1 to Sn can be driven by a method in which signals (potentials) are simultaneously applied from the sampling (switch) circuit 18 to all the source lines S1 to Sn, or an arbitrary source line Si is connected by the sampling (switch) circuit 18. Examples include a method of selecting and applying a signal voltage to the selected source line. In accordance with each method, the liquid crystal module 2 or the driving IC 1 is provided with an appropriate circuit (for example, a latch circuit or a hold circuit).

  Next, setting of the drive signal generation unit (drive signal optimization) in the drive IC 1 will be described. The driving IC 1 is provided with an adjusting unit 29 (see FIG. 1), and a predetermined timing (initial value) is stored in the register 22 of the adjusting unit 29. The drive signal generator 21 reads an initial value from the register 22 as an initial setting before starting the liquid crystal module drive, generates two test drive signals for the source and the gate based on the initial value, and outputs the test drive signals to the liquid crystal module. Output to 2 side.

  Then, the test drive signal for the gate includes wiring of the connector 30 (see FIG. 3), wiring within the gate driver 5 (for example, the gate shift register 9), dummy line Dg1, dummy line Dg2, dummy line DL3, and connector 30. The signal is fed back to the driving IC 1 (phase comparator 23). On the other hand, the test drive signal for the source passes through the wiring of the connector 30, the source driver (for example, the source shift register 8), the dummy line Ds 1, the dummy line Ds 2, the dummy line D 13, and the wiring of the connector 30. Feedback to the device 23). Thus, the signal fed back to the driving IC 1 (feedback signal) is a signal before the input of the liquid crystal module 2 due to the parasitic capacitance and parasitic resistance in the liquid crystal module 2 in addition to the parasitic capacitance and parasitic resistance when the driving IC 1 is mounted. (Refer to the graphs (a) to (c) of FIG. 5).

  Therefore, each feedback signal is input to the phase comparator 23 and compared (phase comparison) with the source or gate test drive signal. This comparison result (phase comparison result) is sampled and digitized by the decoder 24 and output to the adder 25. The adder 25 adds the initial value of the register 22 and the output from the decoder 24 and outputs this to the drive signal generator 21. The drive signal generator 21 adjusts the timing of the drive signal based on the output from the adder 25 (sets it optimally).

  In this way, the test drive signal is fed back via the source driver 3 and the dummy wirings Ds1 and Ds2, etc., so that the setting of the drive signal generator 21 by the adjustment unit 29 is performed in the source driver 3 and the source lines S1 to Sn. The signal delay can be reflected. Further, by feeding back the test drive signal via the gate driver 5 and the dummy wirings Dg1 and Dg2, etc., the setting of the drive signal generator 21 by the adjusting unit 29 is set in the gate driver 5 or in the gate lines G1 to Gn. Signal delay can be reflected. In addition, since the dummy wirings Ds1 and Dg1 pass through the pixel portion in the non-display area, it is possible to detect a signal delay caused by the constituent member (for example, liquid crystal) of the pixel portion 2y (for example, due to the parasitic capacitance of the liquid crystal). This can be reflected in the setting of the drive signal generator 21 by the adjustment unit 29. As described above, even if the driving IC 1 is arbitrarily mounted by a user or the like, the driving signal generator 21 can generate optimal driving signals (gate driving signal and source driving signal) and output them to the liquid crystal module 2. Then, by driving the drivers 3 and 5 of the liquid crystal module 2 with the drive signals (gate drive signal and source drive signal) at the optimal timing, display quality can be improved and power can be saved.

  The configuration of the phase comparator 23 and the waveform shaping thereof will be described below with reference to FIGS. 4 and 5 (a) to (f). As shown in FIG. 4, the test drive signal output from the drive signal generator 21 (see FIG. 5 graph (c)) and the feedback (FB) signal input from the liquid crystal module 2 (see FIG. 5 graph (a)). Are input to the terminal Q and the terminal P, respectively. The two signals are sampled at the timing of the sampling signal. The test drive signal is latched as it is (see graph (e) in FIG. 5), while the FB signal is latched after waveform shaping by the Schmitt trigger element (see graph (d) in FIG. 5). Thereafter, only the FB signal is inverted, and AND is performed, and this is output to the adjustment unit 29 (see FIG. 1) as a comparator output signal (see graph (f) in FIG. 5).

  The liquid crystal module and the driving IC are suitable for a small and medium display device such as a mobile phone, a digital camera, and a PDA, and can be applied to an instrument panel of a vehicle.

It is a block diagram which shows the structure of the drive IC of this invention. It is a block diagram which shows the structure of the liquid crystal module of this invention. It is a block diagram which shows the structure at the time of connecting the said drive IC and the said liquid crystal module. It is a block diagram which shows the structure of the phase comparator of this drive IC. It is a graph which shows each signal waveform seen with the phase comparator of FIG. It is a schematic diagram explaining the cause of the signal delay in a drive IC and a liquid crystal module. It is a graph which shows the signal waveform in each part of FIG. It is a schematic diagram which shows the structure of the conventional external drive device and a display panel.

Explanation of symbols

1 Drive IC (Driver for display device)
2 Liquid crystal module (display device / liquid crystal display device)
2x display area 2y pixel unit 3 source driver 5 gate driver 8 source shift register 9 gate shift register 11 DA converter 12 level shifter 21 drive signal generator (drive signal generation unit)
22 register 23 phase comparator (comparator)
24 Decoder 25 Adder 29 Adjustment unit 33 Signal processing unit Ds1, Ds2, DL3 Dummy line (dummy wiring)
Dg1, Dg2, Dl3 dummy line (dummy wiring)
S1 to Sn source line (data signal line)
G1 to Gn gate lines (scanning signal lines)
TR (i, j) Thin film transistor

Claims (11)

A drive device for a display device having a drive signal generation unit for generating a drive signal for driving the display device, and driving the display device from the outside,
A comparison unit that compares the test drive signal output to the display device by the drive signal generation unit and a feedback signal from the display device with respect to the test drive signal;
A drive device for a display device, comprising: an adjustment unit configured to set a drive signal generation unit based on a comparison result of the comparison unit. A drive device for a display device that has a drive signal generation unit that generates a drive signal for driving the display device, and that drives the display device from the outside,
The drive device for a display device, wherein the drive signal generation unit generates the drive signal based on a difference between a test drive signal output to the display device and a feedback signal from the display device for the test drive signal.   The display device drive device according to claim 1, wherein the comparison unit compares the phase of the test drive signal with the phase of the feedback signal.   2. The display device drive device according to claim 1, wherein the test drive signal is fed back after passing through a plurality of dummy wirings formed in the display device.   5. The drive device for a display device according to claim 4, wherein the dummy wiring includes a plurality of dummy wirings formed along the data signal line.   5. The display device driving device according to claim 4, wherein the dummy wiring includes a plurality of dummy wirings formed along the scanning signal lines.   7. The display device driving device according to claim 5, wherein the dummy wiring includes a dummy wiring that passes through a pixel portion of a non-display area in the display device. A display device driven by the display device drive device according to claim 4,
A display device comprising a plurality of dummy wirings connectable to a driving device of the display device.   9. The display device according to claim 8, wherein the dummy wiring includes a plurality of dummy wirings formed along the data signal line.   9. The display device according to claim 8, wherein the dummy wiring includes a plurality of dummy wirings formed along the scanning signal line.   A liquid crystal display device comprising the display device according to claim 8.

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