JP2006262574A - Secondary battery protection circuit, battery pack and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To utilize a technology for shortening a delay time of a detection signal in each of a discharging overcurrent state and a charging overcurrent state that has conventionally been used for testing, to a protection function at normal discharging and charging. <P>SOLUTION: This secondary battery protection circuit is provided with: a conventional charging overcurrent detection circuit 22; a conventional discharging overcurrent detection circuit 23; a shortening circuit 25 that shortens a delay time in a delay means together with the delay means (27, 28), a discharging path shut-off means (29a, discharging controlling FET), and charging path shut-off means (20, 29b, charging controlling FETs); and an abnormality detection circuit 25a that detects that the potential (V-) of a charger negative terminal becomes higher than a threshold Vt (Vt>>Vh) that is set in advance for detecting an abnormal discharging state at discharging, or that the potential becomes lower than a threshold Ve (Ve<<Vj) that is set in advance for detecting an abnormal charging state at charging. When the abnormality detection circuit detects an abnormal discharging state and an abnormal charging state, the abnormality detection circuit starts the shortening circuit and expedites the shut-off of a discharging current path and a charging current path. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a secondary battery such as a lithium (Li) ion / lithium (Li) polymer secondary battery used in various electronic devices such as a mobile phone, a notebook computer, and a PDA (Personal Digital Assistance). More particularly, the present invention relates to a secondary battery protection technique suitable for reducing the number of parts and reducing the size and cost.

  As secondary batteries used in various electronic devices such as mobile phones, notebook computers, and PDAs (Personal Digital Assistance), there are lithium-ion batteries and lithium-poly batteries. When these secondary batteries are overcharged, metallic lithium Will deposit and lead to an accident. In addition, if overdischarge is repeatedly performed, the number of times of charge and discharge is extremely deteriorated.

  In order to cope with such problems, a protection circuit (secondary battery protection circuit) including a power MOSFET is provided for disconnecting the secondary battery from the charge / discharge device body when overcharge or overdischarge is detected. It has been.

  FIG. 3 is a block diagram showing a configuration example of a conventional secondary battery protection circuit and a battery pack using the same, 31 is a secondary battery protection circuit (described as “protection device” in the figure), and 32 is an overcharge detection. Circuit, 33 is an overdischarge detection circuit, 34 is an overcurrent detection circuit, 35 is a short circuit detection circuit, 36 is an abnormal charger detection circuit, 36a is an N-channel FET, 37 is an oscillation circuit, 38 is a counter circuit, 39a and 39b are Logic circuit, 30 is a level shift, 311 is a battery pack, 312 is a positive terminal, 313 is a negative terminal, 314 is a charger, 315 is a secondary battery such as a lithium (Li) ion / lithium (Li) polymer secondary battery, etc. C (1) is a capacitor, R (1-5) is a resistor, Vdd is a substrate potential terminal of the secondary battery protection circuit 1, Vss is a ground terminal of the secondary battery protection circuit 1, D ut the overdischarge detection output terminal, Cout is the overcharge detection output terminal, V- is charger negative potential input terminal.

  The battery pack 311 using such a secondary battery protection circuit 31 is used for various electronic devices such as a mobile phone, a notebook computer, and a PDA, for example, and protects the secondary battery provided in the battery pack 311. The circuit 31 is roughly composed of an overcharge detection circuit 32, an overdischarge detection circuit 33, a charge overcurrent detection circuit 34a, a discharge overcurrent detection circuit 34b, a short circuit detection circuit 35a, an abnormal charger detection circuit 36, and the like. The secondary battery cell 315 is protected from overcharge, overdischarge, overcurrent, short circuit, etc. by detecting overcharge, overdischarge, overcurrent, short circuit, etc. of the secondary battery cell 315.

  However, for example, in overdischarge detection by the overdischarge detection circuit 33, when the divided potential of the battery voltage Vdd is close to the end voltage at which the discharge operation should be stopped, the voltage margin becomes small, and sudden load fluctuations cause the load When the overcurrent flows, the battery voltage VCC temporarily becomes lower than the end voltage due to the impedance of the battery, and it is erroneously determined that the discharge voltage itself becomes lower than the end voltage, and the discharge capacity is substantially lowered below the actual capacity. End up.

  In the charging overcurrent circuit 34a, when overcurrent flows during charging and the voltage at the terminal V- decreases to a value that becomes Vss (0V), the charging overcurrent is detected and Cout is set to a low level. Although the charging control FET is turned off to prevent further charging current from flowing, it may be determined that the V-voltage has fallen to a value at which it becomes Vss (0 V) by mistake.

  In order to cope with such a problem, in the example of FIG. 3, a delay function including an oscillation circuit 37 and a counter circuit 38 is provided. Hereinafter, this delay function will be described with reference to FIG.

  The circuit shown in FIG. 8 is described in Patent Document 1, and is for preventing erroneous detection at the time of discharging in the protection circuit of the secondary battery. In this circuit, the output of the detector (COMP804) is The protection switch (807) is not immediately turned off even when the voltage falls below the cutoff voltage, but the protection switch (807) is turned off only when the state continues for a certain period or longer. Here, the internal oscillator 801 is turned off. And a timer comprising a frequency dividing counter 802 is used.

  In FIG. 8, the voltage comparison circuit COMP 804 compares the reference voltage (V 4) with the divided voltage VCC / N, and when the battery voltage VCC becomes equal to or lower than the end voltage, a low level signal is output to reset the frequency dividing counter 802. To start counting. When the counted value reaches a value set in advance by the decoder 805, the latch circuit 805a is set to turn off the protection switch 807 composed of a MOS transistor.

  However, if the battery voltage VCC returns to a voltage equal to or higher than the original end voltage before the frequency dividing counter 802 reaches a preset value, a reset signal is generated and the frequency dividing counter 802 is reset during counting. As a result, if the setting by the decoder circuit 805 is set to a relatively long time in consideration of load fluctuations, the protection switch 807 can be used even when the battery voltage VCC temporarily drops below the end voltage due to load fluctuations. Is not turned off, and malfunction can be avoided.

  Further, as in the case of such overdischarge, all of the delay time upon detection of overcharge, overcurrent, and short circuit can be determined by the internal oscillation circuit and the counter. In this technique, it is not necessary to provide an external capacitor for determining the delay time, and the number of parts of the protection circuit board can be reduced.

  In this way, in the circuit of FIG. 3, for example, overcharge and overdischarge are detected by the overcharge detection circuit 32, the overdischarge detection circuit 33, the charge overcurrent detection circuit 34a, the discharge overcurrent detection circuit 34b, and the short circuit detection circuit 35a. When an overcurrent or a short circuit is detected, the oscillation circuit 37 starts operating and the counter circuit 38 starts to operate.

  Then, when the delay time set at each detection is counted, the output of the Cout terminal becomes low level in the case of overcharge through the logic circuits 39a and 39b and the level shift 30, and the charge control FET is turned off and over. In the case of discharge or short circuit, the output of the Dout terminal is at a low level, and the discharge control FET is turned off.

  The abnormal charger detection circuit 36 is connected to the overcurrent detection circuit 34 and the short circuit detection circuit 35 when an abnormal charger 314 or the like is connected to the terminals 312 and 313 and a large voltage is applied to the battery pack 311. This is a circuit for preventing the shift of the overcurrent detection voltage value and the short circuit detection voltage value due to the time-dependent change of the Vth of the transistor by turning off the FET switch 36a so that the potential of the V-terminal is not applied.

  In the secondary battery protection circuit 31 having such a configuration, the delay time by the counter circuit 38 at the time of overdischarge detection by the overdischarge detection circuit 33 is normally about 20 mS (milliseconds), the charge overcurrent detection circuit 34a and the discharge overcurrent. The delay time at the time of overcurrent detection by the detection circuit 34b is about 10 mS, the delay time at the time of short circuit detection by the short circuit detection circuit 35a is about 1 mS, and the delay time at the time of overcharge detection by the overcharge detection circuit 32 is 1S (seconds) or more. is there.

  Such a delay time at the time of detection becomes a problem in the function test of the secondary battery protection circuit 31 at the time of production of the battery pack 311. That is, when testing a protective circuit board provided with such an internal oscillation circuit and a counter, the delay time when detecting overdischarge and overcurrent is generally about 20 mS (milliseconds). Although there is not so much influence, the delay time when overcharge is detected is normally set to about several seconds (1 second or more). Therefore, when testing the overcharge detection operation, a time of several seconds or more is necessary.

  In particular, when measuring (testing) an accurate overcharge detection voltage value, a waiting time of several seconds or more is required every time the voltage is stepped. Therefore, assuming that the detection voltage can be measured in 25 steps, the waiting time Is 2 seconds, the time required to measure the overcharge detection voltage value is 50 seconds, which is not a practical level because it takes too much time for mass production.

  In order to cope with such a problem, the secondary battery protection circuit 31 in FIG. 3 is provided with a test terminal (described as “TEST” in the figure) and a shortening circuit 35. This test terminal shortens the delay time of the delay circuit that determines the delay time when detecting overcharge, overdischarge, discharge overcurrent, charge overcurrent, and short circuit by increasing the oscillation frequency, thereby reducing the test time. This technique shortens the cost of the inspection process, and such techniques are described in, for example, Patent Documents 2 to 4.

  Furthermore, in Patent Document 5, as shown in FIG. 9, a test control circuit 920 is provided in the oscillation circuit, and the test shortening function is merged with the charger minus voltage input terminal (V−). A technique is described in which the number of test terminals is reduced to reduce the circuit scale, the chip area is reduced, and the cost is reduced.

  The circuit shown in FIG. 9 is a ring oscillator using a constant current inverter and a capacitor. The oscillation frequency includes constant current values of constant currents 926 and 928, values of capacitors 929 and 930, and thresholds of inverters 931 and 932. Determined by. For example, when a high level is normally input to the “Cout” state signal and a normal low level is input to the input of the hysteresis inverter 933, the gate voltages of the Pch transistors 923 and 924 are high, and thus Pch Transistors 923 and 924 are OFF. Therefore, the oscillation frequency is determined by the values of the constant currents 926 and 928 and the capacitors 929 and 930.

  However, if V− is lowered to a level lower than Vss while the Cout state signal remains high, a high level is input to the hysteresis inverter 933, the gate voltages of the Pch transistors 923 and 924 become low, and the Pch transistors 923 and 924 Since the constant current value that determines the oscillation frequency becomes “constant current 926 + constant current 925” and “constant current 928 + constant current 927”, the oscillation frequency increases, and the delay time when overcharge is detected is reduced. Can be shortened.

  For example, when the ratio of the constant current 926 and the constant current 925 and the ratio of the constant current 928 and the constant current 927 is “1: 9”, the oscillation frequency can be reduced to 1/10 and the delay time can be reduced to 1/10. . In this case, the test time of the semiconductor device or the protection circuit board on which the semiconductor device is mounted can be reduced to 1/10.

  However, in the secondary battery protection circuit shown in each of Patent Documents 3 to 5, for example, discharge overcurrent detection (mainly detected at about several A due to overload and the detection state is maintained at about several mS to several tens of mS. A function that disables discharge) and a function that detects short-circuits (mainly detected at several tens of A or more due to output short-circuits and holds the detection state for several hundred μS to become discharge-disabled) are provided separately. Individually, it has a detection circuit and a delay circuit (if it is composed of a clock circuit and a counter circuit, it may have a decoder circuit and a flip-flop circuit individually with a common clock circuit and counter circuit). The number of parts is required, which hinders downsizing.

  In addition, regarding the charge overcurrent detection function, when an overcurrent flows during charging and the voltage at the terminal V- decreases to a value that becomes Vss (0 V), the charge control FET is turned OFF, and more It only implements a function that prevents charging current from flowing.

JP-A-9-182283 JP 2001-268810 A JP 2002-186173 A JP 2002-176730 A JP 2005-012852 A

  The problem to be solved is that the conventional technology does not effectively use the technology for reducing the delay time during the test for the protection of the secondary battery.

  The object of the present invention is to solve the problems of the prior art, to reduce the circuit scale of the secondary battery protection circuit, to reduce the product chip area and to reduce the cost, and to charge the secondary battery during charging. It is possible to more efficiently perform protection.

  In order to achieve the above object, the secondary battery protection circuit (for example, the secondary battery protection circuit 21 shown in FIG. 2) of the present invention has (1) a function of protecting the secondary battery (battery cell 215) during discharge. Discharge overcurrent detection means (discharge) for detecting that the potential (V−) of the charger minus terminal of the secondary battery is higher than a threshold value Vh set in advance for detecting the discharge overcurrent state when the secondary battery is discharged. Overcurrent detection circuit 24b), delay means (oscillation circuit 27, counter circuit 28) for outputting a detection result signal of the discharge overcurrent state by the discharge overcurrent detection means with a predetermined time Th delayed, and this delay When the detection result signal is output from the means, the discharge path interruption means (logic circuit 29a, discharge control FET) that interrupts the discharge current path is newly added, and the potential of the charger minus terminal (when the secondary battery is discharged) ( When it is detected that-) is higher than a threshold value Vt (Vt >> Vh) set in advance for detecting an abnormal discharge state, the delay time in the delay means is shortened and the discharge current path is interrupted by the discharge path interrupt means. Means (abnormality detection circuit 25a, shortening circuit 25) are provided. (2) As a protection function during charging of the secondary battery, the potential (V−) of the charger minus terminal of the secondary battery is set in advance to detect the charge overcurrent state when the secondary battery is charged. The charge overcurrent detection means (charge overcurrent detection circuit 24a) for detecting that the voltage is lower than Vj, and the detection result signal of the charge overcurrent state by the charge overcurrent detection means is delayed by a predetermined time Tj by the delay means. In addition to charging path blocking means (logic circuit 29b, level shift 20, charge control FET) that cuts the charging current path when output, the potential (V-) of the charger minus terminal is newly charged when the secondary battery is charged. Is detected to be lower than a threshold value Ve (Ve << Vj) set in advance for detecting an abnormal charging state, the shortening means is activated to shorten the delay time in the delay means, and the charging path blocking means Characterized in that a means for advancing the interruption of the charging current pathway by.

  According to the present invention, the technology for shortening the delay time of each detection signal in the discharge overcurrent state and the charge overcurrent state, which has been used for testing in the past, is used for the protection function during normal discharge and charge. By doing so, for example, the conventional short-circuit detection protection function can be easily realized, and the charge overcurrent protection control can be performed in two stages, thereby reducing the cost by reducing the circuit and the chip area. This can be realized and the function of the secondary battery protection circuit can be improved.

  The best mode for carrying out the present invention will be described below with reference to the drawings. FIG. 1 is a circuit showing a characteristic first structural example of a secondary battery protection circuit according to the present invention, and FIG. 2 is a configuration example of a battery pack provided with a secondary battery protection circuit according to the present invention. FIG.

  In FIG. 2, 21 is a secondary battery protection circuit according to the present invention (denoted as “protection device” in the figure), 22 is an overcharge detection circuit, 23 is an overdischarge detection circuit, 24 is an overcurrent detection circuit, and 25 and 25a. Is a shortening circuit and an abnormality detection circuit characteristic of the present invention, 26 is an abnormal charger detection circuit, 26a is an N-channel FET, 27 is an oscillation circuit, 28 is a counter circuit, 29a and 29b are logic circuits, 20 is a level shift, 211 is a battery pack, 212 is a positive terminal, 213 is a negative terminal, 214 is a charger, 215 is a secondary battery cell such as a lithium (Li) ion / lithium (Li) polymer secondary battery, and the like C (1 ) Is a capacitor, R (1-5) is a resistor, Vdd is a substrate potential terminal of the secondary battery protection circuit 21, Vss is a ground terminal of the secondary battery protection circuit 21, and Dout is an overdischarge detection. Power terminal, Cout is the overcharge detection output terminal, V- charger negative potential input terminal.

  The battery pack 211 using the secondary battery protection circuit 21 is used for various electronic devices such as a mobile phone, a notebook computer, and a PDA, for example, and protects the secondary battery provided in the battery pack 211. The circuit 21 is roughly composed of an overcharge detection circuit 22, an overdischarge detection circuit 23, a charge overcurrent detection circuit 24a, a discharge overcurrent detection circuit 24b, an abnormal charger detection circuit 26, and an abnormality detection circuit 25a. The secondary battery cell 15 is protected from overcharge, overdischarge, and overcurrent by detecting overcharge, overdischarge, overcurrent, and the like of the secondary battery cell 15.

  For example, when overcharge, overdischarge, charge overcurrent, or discharge overcurrent is detected by the overcharge detection circuit 22, overdischarge detection circuit 23, charge overcurrent detection circuit 24a, or discharge overcurrent detection circuit 24b, the oscillation circuit 27 starts to operate, and the counter circuit 28 starts to operate. When the delay time set at the time of each detection is counted, the output of the Cout terminal becomes low level in the case of overcharge and charge overcurrent through the logic circuits 29a and 29b and the level shift 20, and the charge control FET In the case of overdischarge or discharge overcurrent, the output of the Dout terminal becomes low level and the discharge control FET is turned off.

  The abnormal charger detection circuit 26 is connected to the charging overcurrent detection circuit 24a and the discharge overcurrent detection circuit 24b when a large voltage is applied to the battery pack 211 when the abnormal charger 214 or the like is connected. The FET switch 26a is turned off so that (V-potential) is not directly applied, and at the same time, the FET switch 24c is turned on, whereby the ground potential (Vss) is applied to the inputs of the charge overcurrent detection circuit 24a and the discharge overcurrent detection circuit 24b. In order to prevent the charge overcurrent detection voltage value and the discharge overcurrent detection voltage value from shifting due to the change with time of Vth of the input transistors constituting the charge overcurrent detection circuit 24a and the discharge overcurrent detection circuit 24b. Circuit.

  As described above, in this example, the overdischarge detection circuit 23 and the discharge overcurrent detection circuit 24b are provided as a function of protecting the battery cell 215 at the time of discharging. At the time of discharging, it is detected that the potential obtained by dividing the power supply potential Vdd by the resistors R3 and R4 is lower than a predetermined threshold for overdischarge detection, and the discharge overcurrent detection circuit 24b When discharging, for example, a discharge current of several A (amperes) flows, the potential (V−) of the charger minus terminal is higher than a threshold value Vh, for example, about 50 mV to 300 mV, which is set in advance for detecting a discharge overcurrent state. Detect that

  These detection result signals are input to a delay circuit including the oscillation circuit 27 and the counter circuit 28, delayed by a time corresponding to each of the detection result signals, and input to the logic circuit 29a. The logic circuit 29a sets Dout to a low level. The discharge control FET is turned on to interrupt the discharge current path.

  In this example, the conventional “short circuit detection circuit” is not provided, but instead, an “abnormality detection circuit 25a” is provided. The abnormality detection circuit 25a detects a short circuit, and the shortening circuit 25 discharges. By interrupting the current path early, the secondary battery cell 215 can be protected from a short circuit.

  That is, when the battery cell 215 is discharged, the abnormality detection circuit 25a causes the potential (V−) of the charger minus terminal to flow, for example, when a short-circuit current that is several times to several tens of times the current assumed for the discharge overcurrent flows. When it is detected that the threshold value Vt (Vt >> Vh) previously determined for detecting an abnormal discharge state is higher than 0.8 V to 2.0 V, for example, the detection result signal is output to the shortening circuit 25, and the shortening circuit 25 increases the oscillation frequency in the oscillation circuit 27 to increase the count speed by the counter circuit 28, thereby shortening the delay time by the delay circuit composed of the oscillation circuit 27 and the counter circuit 28. The discharge current path is interrupted earlier than the protection by the overcurrent detection circuit 24b.

  Thus, in this example, the conventional short-circuit protection function can be realized by the abnormality detection circuit 25a and the shortening circuit 25.

  In this example, an overcharge detection circuit 22 and a charge overcurrent detection circuit 24a are provided as functions for protecting the battery cell 215 during charging. The overcharge detection circuit 22 is provided when the battery cell 215 is charged. , Detecting that the potential obtained by dividing the power supply potential Vdd by the resistors R1 and R2 is higher than a threshold value that is set in advance for overcharge detection, and the charge overcurrent detection circuit 24a detects when the battery cell 215 is charged. For example, when a charging current of several A (amperes) flows, the potential (V−) of the charger minus terminal is compared with the ground potential (Vss), and a threshold value Vh set in advance for detecting a charging overcurrent state, For example, it is detected that the voltage is lower than about −50 mV to −300 mV.

  These detection result signals are input to a delay circuit composed of an oscillation circuit 27 and a counter circuit 28, and are input to the logic circuit 29b and the level shift 20 after being delayed by a corresponding time, similarly to the operation at the time of discharging. From the level shift 20, Cout is set to a low level, the charge control FET is turned on, and the charge current path is interrupted.

  Furthermore, in this example, the abnormality detection circuit 25a and the shortening circuit 25 realize a charge overcurrent protection function at a level different from that of the charge overcurrent detection circuit 24a. That is, when the battery cell 215 is charged, the abnormality detection circuit 25a causes an abnormal charging current of, for example, several tens of times to several tens of times of the current assumed for the charging overcurrent to flow through the charger minus terminal. When it is detected that the potential (V−) is lower than a threshold value Ve (Ve << Vj) set in advance for detecting an abnormal charging state, for example, about −0.8 V to −2.0 V, the detection result signal Is output to the shortening circuit 25. The shortening circuit 25 increases the oscillation frequency in the oscillation circuit 27 to increase the count speed of the counter circuit 28, thereby delaying the delay time by the delay circuit composed of the oscillation circuit 27 and the counter circuit 28. When the abnormal charging state occurs, the charging current path is interrupted earlier than the protection by the charging overcurrent detection circuit 24a.

  In this way, by appropriately setting the detection level of the abnormality detection circuit 25a, when a dangerous charging overcurrent higher than the level detected by the charging overcurrent detection circuit 24a flows, the protection is performed in a shorter time. Can work function.

  Hereinafter, a detailed configuration of the delay circuit including the abnormality detection circuit 25a and the shortening circuit 25, and the oscillation circuit 27 and the counter circuit 28, and the oscillation circuit 27 and the counter circuit 28 including the abnormality detection circuit 25a and the shortening circuit 25 are included. The operation for shortening the delay time in the delay circuit will be described with reference to FIG.

  In FIG. 1, a hysteresis inverter 13 constitutes an abnormal charge state detection means according to the present invention, and inverters 16 and 17 constitute an abnormal discharge state detection means according to the present invention, and P-channel (Pch) transistors 3, 4 and The constant currents 5 and 7 constitute shortening means according to the present invention, and the constant currents 6 and 8, the capacitors 9 and 10, and the inverters 11 and 12 constitute an oscillation circuit 27.

  The configuration of the oscillation circuit 27 is the same as that of the conventional one shown in FIG. 9 and is a ring oscillator using a constant current inverter and a capacitor. The oscillation frequency is a constant current value of constant currents 5 to 8, capacitors 9, It is determined by the value of 10 and the thresholds of the inverters 11 and 12.

  In this example, in the hysteresis inverter 13 constituting the abnormality detection circuit 25a, the potential (V-) of the charger minus terminal is used as the substrate voltage and the ground potential (Vss) is input, and the potential (V-) of the charger minus terminal is input. Is lower than the threshold value Ve, for example, a low level detection result signal is output when it is about -0.8V to -2.0V.

  For example, when a charging current assumed to be a normal charging overcurrent flows during charging, the potential (V−) of the charger minus terminal is about −50 mV to −300 mV, and the output of the hysteresis inverter 13 is The output of the inverter 16 becomes low level and the output of the inverter 17 becomes high level.

  In this case, the gate voltage of the Pch transistors 3 and 4 is at a high level, the Pch transistors 3 and 4 are turned OFF, the oscillation frequency is determined by the constant currents 6 and 8 and the values of the capacitors 9 and 10, and the overcharge detection circuit 22 and the overdischarge detection circuit 23, the charge overcurrent detection circuit 24a, and the discharge overcurrent detection circuit 24b, the counter circuit 28 counts at a normal speed.

  On the other hand, during charging, an abnormal charging current of several tens of times to several tens of times the current assumed for the charging overcurrent flows, so that the potential of the charger minus terminal (V−) is usually When the voltage threshold Ve is lower than the charging overcurrent detection voltage (-50 mV to -300 mV), for example, about -0.8 V to -2.0 V, the hysteresis inverter 13 outputs a low level detection result signal. The low level output of the inverter 13 is inverted twice by the inverter 16 and the inverter 17 and input to the gates of the P-channel (Pch) transistors 3 and 4 constituting the shortening circuit 25.

  In this way, when the gate voltage of the Pch transistors 3 and 4 becomes a low level, the Pch transistors 3 and 4 are turned ON (on), whereby the value of the constant current that determines the oscillation frequency is “constant current 6+”. Constant current 5 "and" constant current 8 + constant current 7 "are obtained, the oscillation frequency is increased, the count operation of the counter circuit 28 is speeded up, and the delay time as the delay means is shortened.

  For example, when the ratio of the constant current 6 to the constant current 5 and the ratio of the constant current 8 to the constant current 7 is “1: 9”, the oscillation frequency can be 1/10 and the delay time can also be 1/10. .

  As described above, when an abnormal charging current flows several tens of times to several tens of times, which is assumed to be a normal charging overcurrent, and dangerous, the overcharge based on the detection result of the charge overcurrent detection circuit 24a is detected. The current protection operation takes time and cannot be dealt with. However, by detecting that an abnormal charging current has flowed in the hysteresis inverter 13, the charging current path can be cut off in a short time, and the countermeasure can be taken.

  The inverter 16 constituting the abnormality detection circuit 25a receives the output of the hysteresis inverter 13 as an input and performs the above-described inversion operation at the time of charging, but uses the potential (V−) of the charger minus terminal as the substrate voltage. At the time of discharging, for example, a short-circuit current of several tens of times to several tens of times the current assumed for the discharge overcurrent flows, and the potential (V−) of the negative terminal of the charger is the discharge overcurrent detection circuit. When the threshold voltage Vh (e.g., 0.8 V to 2.0 V) higher than the voltage (50 mV to 300 mV) detected at 24b is exceeded, the substrate voltage of the N channel transistor constituting the inverter 16 is V-, and the N channel transistor The drain voltage of the inverter 16, that is, the output of the inverter 16, is almost V-voltage (0.8 V to 2.0 V), that is, high level.

  The high level output of the inverter 16 is inverted by the inverter 17 and input to the gates of the Pch transistors 3 and 4 constituting the shortening circuit 25, the gate voltage of the Pch transistors 3 and 4 becomes low level, and the Pch transistors 3 and 4 The constant current values that determine the oscillation frequency are “constant current 6 + constant current 5” and “constant current 8 + constant current 7”, the oscillation frequency increases, and the count operation of the counter circuit 28 is accelerated. The delay time as the delay means is shortened.

    In the case of the short circuit state, it exceeds about ½ of the power supply voltage of the inversion voltage of the inverter 17, so the abnormal discharge overcurrent state is detected and the delay time is shortened. For example, when the delay time is set to 12 ms based on the detection result by the discharge overcurrent detection circuit 24b and the delay time reduction rate is 1/30, the delay time when the short circuit is detected by the abnormality detection circuit 25a is 400 μs. Thus, the standard short-circuit search protection operation is performed.

  Incidentally, also for the secondary battery protection circuit provided with such an abnormality detection circuit 25a, it is required to reduce the delay time during the test when performing the test in the production process. Hereinafter, the secondary battery protection circuit according to the present invention having a test function will be described with reference to FIGS.

  FIG. 4 is a circuit diagram showing a second characteristic example of the secondary battery protection circuit according to the present invention, and FIG. 5 is a third characteristic configuration of the secondary battery protection circuit according to the present invention. FIG. 6 is a circuit showing a fourth example of a characteristic component of the secondary battery protection circuit according to the present invention. FIG. 7 is a characteristic of the secondary battery protection circuit according to the present invention. It is a circuit which shows the 5th example of a component part.

  In the circuit shown in FIG. 4, the abnormality detection circuit 25a according to the present invention is built in the conventional test control circuit 920 shown in FIG. 9, and the inverters 416 and 417 in FIG. 4 are newly incorporated. The abnormality detection circuit 25a is configured.

  The delay time at the time of overdischarge detection by the overdischarge detection circuit 23 in FIG. 2 is about 20 mS, the delay time at the time of overcurrent detection by the discharge overcurrent detection circuit 24b and the charge overcurrent detection circuit 24a is about 10 mS, and abnormal The delay time at the time of short circuit detection by the detection circuit 26a is about 1 mS, but the delay time at the time of overcharge detection by the overcharge detection circuit 22 is 1 S or more.

  Therefore, in the circuits shown in FIGS. 4 and 9, when the secondary battery protection circuit is tested, the “Cout” terminal is set to a high level (overcharge is not detected), and V− is set to a level lower than Vss. By fixing to, the test time is shortened by increasing the frequency of the oscillation circuit and shortening the delay time.

  In FIG. 4, the constituent elements 43 to 49 and 410 to 412 substantially correspond to the constituent elements 3 to 9 and 10 to 12 in FIG. 1, and constitute the oscillation circuit 27 and the shortening circuit 25. This is not described here.

  4, reference numeral 413 corresponds to the hysteresis inverter 933 in FIG. 9, reference numeral 414 corresponds to the inverter 934 in FIG. 9, and reference numeral 415 corresponds to the NAND circuit 935 in FIG.

  4 corresponds to the inverter 16 in FIG. 1, and the reference numeral 417 corresponds to the inverter 17 in FIG. The hysteresis inverter 413 corresponds to the hysteresis inverter 933 in FIG. 9 and also corresponds to the hysteresis inverter 13 in FIG.

  In such a configuration, for example, when a high level is input to the Cout state signal and a low level is input to the input of the hysteresis inverter 413, the hysteresis inverter 413 outputs a high level, and the inverters 416, 417, The low level is input to the NAND circuit 415 via 414, the output of the NAND circuit 415 becomes high level, the gate voltage of the Pch transistors 3 and 4 is high level, and the Pch transistors 3 and 4 are turned OFF, so oscillation The frequency is determined by the values of the constant currents 46 and 48 and the capacitors 19 and 410, resulting in a normal delay time.

  However, at the time of the test, if the charger minus terminal potential V− is lowered to a level lower than the ground electron Vss while the Cout state signal remains at the high level, the high level is input to the hysteresis inverter 413 and the hysteresis inverter 413 changes to the low level. The high level is input to the NAND circuit 415 via the inverters 416, 417, and 414, the output of the NAND circuit 415 becomes low level, the gate voltage of the Pch transistors 3 and 4 is low level, and the Pch transistor 3 , 4 are ON, and the constant current values that determine the oscillation frequency are “constant current 46 + constant current 45” and “constant current 48 + constant current 47”, and the oscillation frequency increases. The delay time at the time of charge detection can be shortened.

  Further, in the normal charging / discharging operation instead of the test time, as described with reference to FIG. 1, the abnormal inverter 413 and the inverter 416 constituting the abnormality detecting circuit 26a cause an abnormal overcurrent during the charging / discharging operation. When the state is detected, the Pch transistors 3 and 4 are turned ON, the oscillation frequency of the oscillation circuit 27 is increased, the delay time can be shortened, and the charge current path and the discharge current path are cut off faster. Can do.

  For example, when the ratio of the constant current 46 to the constant current 45 and the ratio of the constant current 48 to the constant current 47 is set to “1: 9”, the oscillation frequency at the time of detecting overcharge becomes 1/10, and the delay time is also 1/9. Can be 10. In this case, the test time can be reduced to 1/10.

  However, when there is a charge overcurrent detection function (when the charge overcurrent detection circuit 24a is provided and operating), the overcharge detection circuit 22 detects overcharge because the setting of the charge overcurrent detection delay time is about 10 mS. The delay time is sufficiently short compared with about 1S, and even when the time is shortened during the test, the overcharge protection cannot be tested because the charge overcurrent protection always works before the overcharge protection.

  As a countermeasure, in this example, when the output from the inverter 417 is at a low level, this low level signal is output as a charge overcurrent detection inhibition mode signal, and the charge overcurrent detection by the charge overcurrent detection circuit 24a is prohibited. In this case, the charge overcurrent detection delay time cannot be shortened.

  When there is no charge overcurrent detection function, there is no need to set such a charge overcurrent detection prohibit mode, and when there is no need to reduce the overcharge detection test time, the charge overcurrent detection prohibit mode is set. There is no need to do.

  Further, as shown in FIG. 5, in the case of a configuration in which a test mode is set by providing a conventional test terminal and inputting a test signal, the shortening mode and the charge overcurrent detection are in an independent state without interference, There is no need to set the charge overcurrent detection prohibit mode.

  Also in FIG. 5, as in the configuration of FIG. 4, the components of reference numerals 53 to 59 and 510 to 512 substantially correspond to the components of reference numerals 3 to 9 and 10 to 12 in FIG. An oscillating circuit 27 and a shortening circuit 25 are configured and will not be described here.

  In FIG. 5, reference numeral 513 corresponds to the hysteresis inverter 933 in FIG. 9, and reference numeral 514 corresponds to the inverter 934 in FIG. However, in this example, a NOR circuit 515 is provided instead of the NAND circuit 935 in FIG.

  5 corresponds to the inverter 16 in FIG. 1, and the reference numeral 517 corresponds to the inverter 17 in FIG. The hysteresis inverter 513 corresponds to the hysteresis inverter 933 in FIG. 9 and also corresponds to the hysteresis inverter 13 in FIG.

  In such a configuration, when a high level test signal is not input to the NOR circuit 515 and a low level is input to the input of the hysteresis inverter 513, the hysteresis inverter 513 outputs a high level, and the inverter A low level is input to the NOR circuit 515 via 516, 517, and 514, the output of the NOR circuit 515 becomes a high level, the gate voltage of the Pch transistors 3 and 4 is high, and the Pch transistors 3 and 4 are OFF. Therefore, the oscillation frequency is determined by the values of the constant currents 56 and 58 and the capacitors 59 and 510, resulting in a normal delay time.

  However, when a high-level test signal is input to the NOR circuit 515 during the test, the output of the NAND circuit 415 becomes low level, the gate voltages of the Pch transistors 53 and 54 are low level, and the Pch transistors 53 and 54 Therefore, the constant current values that determine the oscillation frequency are “constant current 46 + constant current 45” and “constant current 48 + constant current 47”, and the oscillation frequency becomes high. The delay time at the time of charge detection, overdischarge detection, charge overcurrent detection, and discharge overcurrent detection can be shortened.

  In addition, during the normal charging / discharging operation, not during the test, as described with reference to FIG. 1, the abnormal overcurrent during the charging / discharging operation flows by the hysteresis inverter 513 and the inverter 516 constituting the abnormality detecting circuit 26a. When the state is detected, the Pch transistors 53 and 54 are turned on, the oscillation frequency of the oscillation circuit 27 is increased, the delay time can be shortened, and the charge current path and the discharge current path are cut off faster. Can do.

  For example, when the ratio of the constant current 56 to the constant current 55 and the ratio of the constant current 58 to the constant current 57 is set to “1: 9”, the oscillation frequency at the time of detecting overcharge becomes 1/10, and the delay time is also 1/9. Can be 10. In this case, the test time and the time required for protection when an abnormal condition is detected can be reduced to 1/10.

  6 shows an example of a circuit for delaying the discharge overcurrent detection result when the oscillation circuit 27 and the counter circuit 28 in FIG. 2 are not used. In a normal state, the Pch transistor 63 is OFF, and FIG. When the detection result signal of the discharge overcurrent detection circuit 24b is input, the time for delaying the output of the discharge-side FET control signal 60 is determined by the constant current 76, the capacitor 79, and the threshold of the inverter 711.

The normal state is a case where the potential (V−) of the negative terminal of the charger is lower than the ground potential (Vss), and a case where the test signal is also at a low level. A protection operation for the detection result of the discharge overcurrent detection voltage (50 mV to 300 mV) by the detection circuit 24b is performed.

  In FIG. 6, reference numerals 614 and 615 correspond to the inverter 514 and the NOR circuit 515 in FIG. 5, and reference numerals 616 and 617 correspond to the inverter 16 and the inverter 17 in FIG. 1, and constitute the abnormality detection circuit 26a. . In this example, there is no charge overcurrent detection function, and the hysteresis inverters 13, 413, 513 in FIGS.

  In such a configuration, when the potential V− of the charger minus terminal becomes high (0.8V to 2.0V) until the voltage at which the inverter 616 outputs a low level, the output of the inverter 617 is low level, The output of the inverter 614 becomes a high level, and an abnormal charge state is detected by the abnormality detection circuit 26a of FIG. 2, or when the test signal is set to a high level, the output of the NOR circuit 615 becomes a low level in both cases. The transistor 63 is turned on, and the short circuit detection delay time is determined by the sum of the constant current 65 and the constant current 66 and the threshold of the capacitor 69 and the inverter 611.

  Here, when the ratio of the constant current 66 to the constant current 65 is 1: 9, the delay time can be reduced to 1/10. The capacitor 69 may be an IC built-in or an external component. When the test mode is not necessary, the NOR circuit 615 may be replaced with an inverter in series with the inverter 614.

  FIG. 7 shows an example of a circuit that delays the charge overcurrent detection result when the oscillation circuit 27 and the counter circuit 28 in FIG. 2 are not used. In a normal state, the Pch transistor 73 is OFF, and FIG. When the detection result signal of the charge overcurrent detection circuit 24a is input, the time for delaying the output of the charge side FET control signal 70 is determined by the constant current 76, the capacitor 79 and the threshold of the inverter 711.

  Note that the normal state is a case where the potential (V−) of the charger minus terminal is substantially the same as the ground potential (Vss) and the test signal is also at a low level. The protection operation is performed for the detection result of the charge overcurrent detection voltage (-50 mV to -300 mV) by the detection circuit 24a.

  7, reference numeral 714 and reference numeral 715 correspond to the inverter 514 and the NOR circuit 515 in FIG. 5, and reference numeral 713 corresponds to the hysteresis inverters 13, 413, 513 in FIGS. 1, 4 and 5, and the abnormality detection circuit 26a. Configure. In this example, there is no discharge overcurrent detection function, and the inverters 16, 17, 416, 417, 516, 517 in FIGS.

  In such a configuration, when the potential V− of the charger minus terminal is lower than the ground potential Vss (−0.8 V to −2.0 V) until the voltage at which the hysteresis inverter 613 outputs a low level, The output of the inverter 614 becomes a high level, and the abnormal discharge state is detected by the abnormality detection circuit 26a of FIG. 2, or the output of the NOR circuit 715 is either in the test mode when the test signal is set to the high level. The Pch transistor 73 is turned on and the short-circuit detection delay time is determined by the sum of the constant current 75 and the constant current 76 and the threshold of the capacitor 79 and the inverter 711.

  Here, if the ratio of the constant current 76 and the constant current 75 is 1: 9, the delay time can also be reduced to 1/10. The capacitor 79 may be an IC built-in or an external component. When the test mode is unnecessary, the NOR circuit 715 may be replaced with an inverter in series with the inverter 714.

  As described above with reference to FIGS. 1 to 7, in the secondary battery protection circuit of this example, as shown in FIG. 2, for example, a conventional charge overcurrent detection circuit 22, discharge overcurrent detection circuit 23, delay means are provided. (Oscillation circuit 27, counter circuit 28), discharge path blocking means (logic circuit 29a, discharge control FET), charge path blocking means (level shift 20, logic circuit 29b, charge control FET) constitute delay means. The shortening circuit 25 for shortening the delay time in the oscillation circuit 27, and the potential (V−) of the charger minus terminal are set to a threshold value Vt (for example, 0.8 V to 2.0 V) previously determined for detecting an abnormal discharge state at the time of discharging. Detection circuit that detects that the voltage becomes higher than the threshold value Ve (for example, −0.8 V to 2.0 V) that is set in advance for detecting an abnormal charging state during charging. 5a and is provided, hasten the interruption of the abnormality detecting circuit 25a in the abnormal discharge state and abnormal detecting a charging state to start the short circuit 25 a discharge current path and charging current path.

  That is, at the time of discharging, a discharge overcurrent of the secondary battery (when a discharge current of a number A lower than the short circuit flows) is detected, the discharge current path is cut off by the switch, and the secondary battery is discharged overcurrent. In addition to the function to protect against heat generation due to, for example, due to a short circuit, a short circuit current of several tens of times to several tens of times the current expected for the discharge overcurrent flows, so that the potential V− of the charger minus terminal is grounded. When the voltage Vt (about 0.8 V to about 2.0 V) higher than a predetermined normal overcurrent detection voltage Vh (about 50 mV to about 300 mV) is exceeded than the potential Vss, the oscillation circuit and the counter circuit By increasing the oscillation frequency in the delay circuit, the delay time is shortened, and the discharge current path is interrupted and protection is performed earlier than the detection of the discharge overcurrent.

  Also, during charging, the secondary battery's charging overcurrent (when a charging current of several A flows) is detected, and the charging current path is blocked by a switch to protect the secondary battery from heat generation due to the charging overcurrent. In addition to the function to perform, for example, when an abnormal charging current of several tens of times to several tens of times the current assumed for the charging overcurrent flows, the potential V− of the charger minus terminal becomes higher than the ground electron VSS. The oscillation frequency of the oscillation circuit is reduced when the voltage is lower than a predetermined voltage Ve (about -0.8 V to -2.0 V) lower than a predetermined normal overcurrent detection voltage Vj (about -50 mV to -300 mV). By increasing the delay time, the delay time is shortened, and the charge current path is cut off before the charge overcurrent detection to protect.

  As described above, in this example, when the level corresponding to the short circuit detection (about 0.8V to 2.0V) is detected, the delay time of the overcurrent detection circuit is shortened, and the same as the conventional short circuit protection function. With a delay time of several hundred microseconds, the discharge control FET can be turned off and the discharge current path can be cut off, so that a short circuit can be realized with fewer components, reducing costs by reducing the circuit and chip area. Can be realized.

  In addition, with respect to detection of the charge overcurrent, a first charge overcurrent detection function that detects with a normal charge current of about several A and holds the detection state about several mS to several tens of mS to make the charging prohibited state, Detecting with a more dangerous charge current of about several tens of A, it can be divided into two stages: a second charge overcurrent detection function that keeps the detection state only about several hundred μS and sets the charge prohibited state. The safety during charging can be further increased.

  In addition, according to this example, the technology for shortening the delay time of each detection signal in the discharge overcurrent state and the charge overcurrent state, which has been used for testing in the past, is provided with a protection function during normal discharge and charge. For example, the conventional short-circuit detection protection function can be easily realized, and the charge overcurrent protection control can be performed in two stages, thereby reducing the cost by reducing the circuit and the chip area. And the function of the secondary battery protection circuit can be improved.

  In addition, this invention is not limited to the example demonstrated using FIGS. 1-7, In the range which does not deviate from the summary, various changes are possible. For example, in this example, as the switching means for increasing the constant currents 5 and 7 in FIG. 1, the P-channel transistors 3 and 4 are provided and the constant currents 5 and 7 are increased and connected. Other switching elements may be used.

It is a circuit which shows the example of the 1st characteristic part in the secondary battery protection circuit concerning the present invention. It is a circuit diagram which shows the structural example of the battery pack which provided the secondary battery protection circuit concerning this invention. It is a block diagram which shows the structural example of the conventional secondary battery protection circuit and a battery pack using the same. It is a circuit which shows the characteristic 2nd structural example example in the secondary battery protection circuit concerning this invention. It is a circuit which shows the 3rd structural example of the characteristic in the secondary battery protection circuit concerning this invention. It is a circuit which shows the characteristic 4th structural example example in the secondary battery protection circuit concerning this invention. It is a circuit which shows the characteristic example of the 5th component in the secondary battery protection circuit concerning this invention. It is a block diagram which shows the structure of the circuit for preventing the misdetection at the time of discharge in the protection circuit of the conventional secondary battery. It is a circuit diagram which shows the circuit structure which implement | achieved the delay shortening function at the time of the conventional test.

Explanation of symbols

  3, 4, 43, 44, 53, 54, 63, 923, 924: P-channel (Pch) transistors, 5-8, 45-48, 55-58, 65, 66, 75, 76, 925-928: fixed Current 9, 10, 49, 410, 59, 69, 79, 510, 929, 930: Capacitor 11, 12, 16, 17, 411, 412, 414, 415, 417, 511, 512, 514, 516 517, 611, 614, 616, 617, 711, 714, 931, 932, 934: inverter, 13, 413, 513, 713, 933: hysteresis inverter, 20, 30: level shift, 21, 31: secondary battery protection Circuit ("protection device"), 22, 32: overcharge detection circuit, 23, 33: overdischarge detection circuit, 24a, 34a: charge overcurrent detection circuit, 24b 34b: discharge overcurrent detection circuit, 25, 35: shortening circuit, 25a: abnormality detection circuit, 26, 36: abnormality charger detection circuit, 24c, 26a, 34c, 36a: N-channel FET, 27, 37: oscillation circuit, 28, 38, 40, 50, 980: counter circuit, 29a, 29b, 39a, 39b: logic circuit, 35: short circuit detection circuit, 60: discharge side FET control signal, 211, 311: battery pack, 212, 312: plus Side terminal, 213, 313: minus side terminal, 214, 314: charger, 215, 315: secondary battery cell, 415, 935: NAND circuit, 515, 615, 715, 803: NOR circuit, 801: internal oscillator, 802: Frequency division counter, 804: Comparator, 805a: Latch, 806: Inverter, 807: FET, 920: Test Control circuit, 970: oscillation circuit, C: capacitor, R: resistance, Vdd: substrate potential terminal, Vss: ground terminal, Dout: overdischarge detection output terminal, Cout: overcharge detection output terminal, V-: charger negative potential Input terminal, TEST: Test terminal.

Claims (12)

A secondary battery protection circuit for protecting a secondary battery from overcurrent during discharge,
When the secondary battery is discharged, it is detected that the potential (V−) of the charger minus terminal of the secondary battery is higher than the threshold potential Vh set in advance for detecting the discharge overcurrent state from the ground potential (Vss). Discharge overcurrent detection means;
Delay means for outputting the detection result signal of the discharge overcurrent state by the discharge overcurrent detection means with a predetermined time Th delay;
A discharge path blocking means for blocking a discharge current path when the detection result signal is output from the delay means;
A shortening means for shortening the delay time Th in the delay means and a threshold voltage Vt (predetermined for detecting an abnormal discharge state) when the potential of the negative terminal of the charger (V−) is discharged when the secondary battery is discharged. Vt >> Vh), an abnormal discharge state detecting means for detecting that becomes higher than
A secondary battery protection circuit comprising: an abnormal discharge control means that activates the shortening means to quickly cut off a discharge current path by the discharge path cut-off means when the abnormal discharge state detection means detects the abnormal discharge state; . A secondary battery protection circuit for protecting a secondary battery from overcurrent during charging,
When the secondary battery is charged, it is detected that the potential (V−) of the charger minus terminal of the secondary battery is lower than the ground potential (Vss), which is lower than the threshold value Vj previously determined for detecting the charge overcurrent state. Charging overcurrent detection means;
Delay means for outputting the detection result signal of the charge overcurrent state by the charge overcurrent detection means with a delay of a predetermined time Tj;
Charging path blocking means for blocking the charging current path when the detection result signal is output from the delay means;
The shortening means for shortening the delay time Tj in the delay means and a potential (V−) of the charger minus terminal when the secondary battery is charged has a threshold value Ve ( An abnormal charging state detecting means for detecting that the voltage becomes lower than Ve <<Vj);
A secondary battery protection circuit comprising: an abnormal charge control unit that activates the shortening unit to quickly cut off the charging current path by the charge path cut-off unit when the abnormal charge state is detected by the abnormal charge state detection unit; . A secondary battery protection circuit for protecting a secondary battery from overcurrent during charging and discharging,
When the secondary battery is discharged, it is detected that the potential (V−) of the charger minus terminal of the secondary battery is higher than the threshold potential Vh set in advance for detecting the discharge overcurrent state from the ground potential (Vss). Discharge overcurrent detection means;
When charging the secondary battery, it is detected that the potential (V−) of the charger minus terminal of the secondary battery becomes lower than the ground potential (Vss), which is lower than the threshold value Vj set in advance for detecting the charge overcurrent state. Charging overcurrent detection means for
A delay means for outputting a detection result signal of a discharge overcurrent state by the discharge overcurrent detection means and a detection result signal of a charge overcurrent state by the charge overcurrent detection means with a predetermined time delay corresponding thereto, respectively; ,
A discharge path blocking means for blocking the discharge current path when the detection result signal of the discharge overcurrent state is output from the delay means;
Charging path blocking means for blocking the charging current path when the charging overcurrent state detection result signal is output from the delay means;
Shortening means for shortening the delay time in the delay means by a predetermined time;
Abnormal discharge state detection means for detecting that the potential (V−) of the charger minus terminal becomes higher than a threshold value Vt (Vt >> Vh) set in advance for detecting an abnormal discharge state when the secondary battery is discharged. When,
An abnormal discharge control means for activating the shortening means when the abnormal discharge state detection means detects the abnormal discharge state, and speeding up the interruption of the discharge current path by the discharge path interruption means;
Abnormal charge state detection means for detecting that the potential (V−) of the charger minus terminal is lower than a threshold value Ve (Ve << Vj) set in advance for detecting an abnormal charge state when the secondary battery is charged. When,
A secondary battery protection circuit comprising: an abnormal charge control unit that activates the shortening unit to quickly cut off the charging current path by the charge path cut-off unit when the abnormal charge state is detected by the abnormal charge state detection unit; . A secondary battery protection circuit according to claim 1 or claim 3,
The abnormal discharge state detection means includes
An inverter that outputs a detection result signal at a high level when the potential (V−) of the charger minus terminal becomes higher than a threshold value Vt using the potential (V−) of the charger minus terminal as a substrate voltage is provided. Secondary battery protection circuit. A secondary battery protection circuit according to any one of claims 2 and 3,
The abnormal charging state detection means includes:
The electric potential (V−) of the charger minus terminal is used as a substrate voltage and the ground potential (Vss) is input. The electric potential (V−) of the charger minus terminal is lower than the ground potential (Vss) and above the threshold Ve. A secondary battery protection circuit comprising an inverter that outputs a low-level detection result signal when the voltage becomes lower. The secondary battery protection circuit according to claim 3,
The abnormal charging state detection means includes:
The ground potential (Vss) is input using the potential (V−) of the charger minus terminal as the substrate voltage, and the potential (V−) of the charger minus terminal is lower than the ground potential (Vss) and the threshold value Ve. A first inverter that outputs a low-level detection result signal when lower than
The abnormal discharge state detection means includes
The first inverter is input, the potential of the charger minus terminal (V−) is the substrate voltage, and when the potential of the charger minus terminal (V−) is higher than the threshold value Vt, a high level detection result signal is output. A secondary battery protection circuit comprising a second inverter. A secondary battery protection circuit according to any one of claims 1 to 6,
Overdischarge detection means for detecting that the discharge partial potential (Vc) is lower than a predetermined threshold value for overdischarge detection when the secondary battery is discharged, and outputting a detection result signal to the delay means;
An overcharge detecting means for detecting that the divided voltage potential (Vd) is higher than a predetermined threshold for overcharge detection when charging the secondary battery and outputting a detection result signal to the delay means; Have
When the detection result signal from the overdischarge detection means is output after being delayed by a predetermined time Tc by the delay means, the discharge path interruption means is activated,
2. The secondary battery protection circuit according to claim 1, wherein when the detection result signal from the overcharge detection means is output after being delayed by a predetermined time Td by the delay means, the charge path interruption means is activated. A secondary battery protection circuit according to any one of claims 1 to 7,
Means for inputting a test mode signal;
A secondary battery protection circuit comprising test mode control means for activating the shortening means when a test mode signal is input through the means. The secondary battery protection circuit according to claim 7,
The ground potential (Vss) is input using the potential (V−) of the charger minus terminal as the substrate voltage, and the potential is low if the potential (V−) of the charger minus terminal is lower than the ground potential (Vss). A low level when the charging path blocking means is blocking the charging current path, a second inverter that outputs an output result obtained by inverting the output of the first inverter, and the charging path blocking means. Output means for outputting a high level when not shut off, and NAND means for performing a logical AND operation between the output from the output means and the output of the second inverter, and the output of the output means Is at the high level, the potential (V−) of the charger minus terminal is lower than the ground potential (Vss), and the output of the first inverter is at the low level. Force a high level, if the output of the NAND means and Robert, has a test control means for activating the reduction means as test settings,
The abnormal discharge state detection means includes
When the output of the first inverter is inputted and inverted, and the potential (V−) of the charger minus terminal is set to the substrate voltage, the potential (V−) of the charger minus terminal becomes higher than the threshold value Vt. A third inverter that outputs a level;
A fourth inverter that inputs and inverts the output of the third inverter and outputs it to the input terminal of the second inverter;
If the potential (V−) of the charger minus terminal becomes higher than the threshold value Vt and the output of the third inverter becomes high level, the output of the fourth inverter is low level and the output of the second inverter is When the output of the NAND means becomes a low level, the low level is output as a detection result signal to start the shortening means, and when the shortening means is started by the test control means, the third inverter A secondary battery for outputting a low level signal for setting a test mode for stopping an operation of detecting a charge overcurrent state by the charge overcurrent detection means and performing an operation test of the overcharge detection means. Protection circuit. A secondary battery protection circuit according to any one of claims 1 to 9,
The delay means includes counter means for counting at a predetermined time interval, and means for outputting the detection result signal when the count number by the counter means reaches a predetermined threshold value.
The secondary battery protection circuit, wherein the shortening means shortens a delay time in the delay means by reducing a count time interval of the counter means by a predetermined value.   A battery pack comprising the secondary battery protection circuit according to any one of claims 1 to 10.   An electronic apparatus using the battery pack according to claim 11.

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