JP2006254632A

JP2006254632A - Three-phase v-connected inverter

Info

Publication number: JP2006254632A
Application number: JP2005069663A
Authority: JP
Inventors: Takeyuki Matsumoto; 剛幸松本; Shinichiro Nagai; 真一郎長井; Shinji Sato; 伸二佐藤
Original assignee: Sanken Electric Co Ltd
Current assignee: Sanken Electric Co Ltd
Priority date: 2005-03-11
Filing date: 2005-03-11
Publication date: 2006-09-21
Anticipated expiration: 2025-03-11
Also published as: JP4839641B2

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a size and a cost of a three-phase inverter. <P>SOLUTION: A three-phase V-connected inverter circuit is formed and provided with first and third phase reactors Lu, Lw in an output stage of the inverter circuit, first and third phase current detectors CTu, CTw for detecting currents in the first and third reactors Lu, Lw, first and second filter capacitors Cu, Cw, and a voltage detecting means 5 for detecting voltages across the first and second filter capacitors Cu, Cw; predicts currents in the first and second filter capacitors Cu, Cw based on an output from the voltage detecting means 5; and generates an output current instruction value from a value converted into two-phase axes and a linkage current instruction value. A feedback control signal is formed of the output current instruction value, and outputs from the first and third phase current detectors CTu, CTw. PWM control pulses for first, second, third and fourth switches S1-S4 in the three-phase V-connected inverter circuit are formed based on the feedback control signal. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、力率制御が可能であり且つ低コスト化が可能な３相Ｖ結線インバータに関する。 The present invention relates to a three-phase V-connection inverter capable of power factor control and cost reduction.

ＣＯ₂排出量の増大に伴い燃料電池や太陽電池等を利用した分散型電源への期待が高まっている。この種の分散型電源を３相交流電力系統に連系させるためには力率制御可能な３相インバータが必要になる。また力率を１又は１に近くすることが要求される。３相インバータの交流出力端子における力率を制御するためには、３相交流出力端子を流れる系統電流をそれぞれ検出するための３個の電流検出器とインバータの出力段の３個のリアクトルを流れる電流をそれぞれ検出するための３個の電流検出器とが必要になる。このように６個の電流検出器を設けると必然的にインバータが大型且つコスト高になる。 As CO ₂ emissions increase, expectations for distributed power sources that use fuel cells, solar cells, and the like are increasing. In order to link this type of distributed power supply to a three-phase AC power system, a three-phase inverter capable of power factor control is required. It is also required that the power factor is 1 or close to 1. In order to control the power factor at the AC output terminal of the three-phase inverter, three current detectors for detecting system currents flowing through the three-phase AC output terminal and three reactors at the output stage of the inverter flow, respectively. Three current detectors for detecting each current are required. If six current detectors are provided in this way, the inverter inevitably becomes large and expensive.

３相インバータの電流検出器の個数を減らす方式が特許文献１に開示されている。ここに開示されている方式では、インバータの出力段のフィルタコンデンサの電圧を検出してフィルタコンデンサの電流を予測し、連系電流検出用の電流検出器を省いている。しかし、３相インバータの場合には、インバータ出力段の３個のリアクトルの電流を検出するための３個の電流検出器が必要になる。また、３相フルブリッジ型インバータのスイッチング回路を形成するために６個のスイッチが必要になる。従って、３相インバータが比較的大型且つコスト高になる。 A method of reducing the number of current detectors of a three-phase inverter is disclosed in Patent Document 1. In the system disclosed here, the voltage of the filter capacitor in the output stage of the inverter is detected to predict the current of the filter capacitor, and the current detector for detecting the interconnection current is omitted. However, in the case of a three-phase inverter, three current detectors for detecting the currents of the three reactors in the inverter output stage are required. In addition, six switches are required to form a switching circuit for a three-phase full-bridge inverter. Therefore, the three-phase inverter is relatively large and expensive.

３相インバータの小型化及び低コスト化を図るために３相Ｖ結線インバータを使用することが考えられる。しかし、３相Ｖ結線インバータの場合においても、力率制御を行うために２つの交流端子に流れる電流をそれぞれ検出するための２つの電流検出器と、出力段の２つのリアクトルに流れる電流をそれぞれ検出するための２つの電流検出器が必要になり、必然的に大型且つコスト高になる。
特開２００２−３５４６８１号公報 In order to reduce the size and cost of the three-phase inverter, it is conceivable to use a three-phase V-connection inverter. However, even in the case of a three-phase V-connection inverter, two current detectors for detecting currents flowing through two AC terminals in order to perform power factor control, and currents flowing through two reactors in the output stage, respectively. Two current detectors for detection are required, which inevitably increases in size and cost.
Japanese Patent Laid-Open No. 2002-354681

本発明が解決しようとする課題は力率制御可能な３相インバータのコストが高いことである。 The problem to be solved by the present invention is that the cost of a three-phase inverter capable of power factor control is high.

次に、本願発明を、実施例を示す図面の符号を参照して説明する。但し、特許請求の範囲及びここでの参照符号は本願発明の理解を助けるためのものであって、本願発明を限定するものではない。
上記課題を解決するための本発明は、直流電圧を供給するための第１及び第２の直流端子（１ａ、１ｂ）と、
前記第１及び第２の直流端子（１ａ、１ｂ）間の中間の電位を有する中間端子（１ｃ）と、
３相交流電圧の第１相電圧を出力するための第１相交流端子（２ｕ）と、
前記３相交流電圧の第２相電圧を出力するものであって、前記中間端子（１ｃ）に電気的に接続された第２相交流端子（２ｖ）と、
前記３相交流電圧の第３相電圧を出力するための第３相交流端子（２ｗ）と、
前記第１及び第２の直流端子（１ａ、１ｂ）間に接続された第１及び第２のスイッチ（Ｓ1 、Ｓ2 ）の直列回路と、
前記第１及び第２の直流端子（１ａ、１ｂ）間に接続された第３及び第４のスイッチ（Ｓ3 、Ｓ4 ）の直列回路と、
前記第１及び第２のスイッチ（Ｓ1 、Ｓ2 ）の相互接続点（Ｐ1 ）と前記第１相交流端子（２ｕ）との間に接続された第１相リアクトル（Ｌu ）と、
前記第３及び第４のスイッチ（Ｓ3 、Ｓ4 ）の相互接続点（Ｐ2 ）と前記第３相交流端子（２ｗ）との間に接続された第３相リアクトル（Ｌw ）と、
前記第１相交流端子（２ｕ）と前記第２相交流端子（２ｖ）との間に接続された第１のフィルタコンデンサ（Ｃu ）と、
前記第２相交流端子（２ｖ）と前記第３相交流端子（２ｗ）との間に接続された第２のフィルタコンデンサ（Ｃw ）と、
前記第１相リアクトル（Ｌu ）又は前記第１相交流端子（２ｕ）に流れる第１相電流（Ｉou又はIsu）を検出する第１相電流検出器（ＣＴu ）と、
前記第３相リアクトル（Ｌw ）又は前記第３相交流端子（２ｗ）に流れる第３相電流（Ｉow 又はIsｗ）を検出する第３相電流検出器（ＣＴw ）と、
前記第１及び第２のフィルタコンデンサ（Ｃu 、Ｃw ）の電圧をそれぞれ検出する電圧検出手段（５）と、
前記第１及び第３相電流検出器（ＣＴu 、ＣＴw ）の出力と前記電圧検出手段（５）の出力とに基づいて前記第１、第２及び第３相交流端子（２ｕ、２ｖ、２ｗ）における力率を所望値にするように前記第１〜第４のスイッチをオン・オフ制御するスイッチ制御パルスを形成して前記第１、第２、第３及び第４のスイッチの制御端子に供給する制御部（６）と
を具備していることを特徴とする３相Ｖ結線インバータに係わるものである。
なお、本発明における前記中間端子は、電気回路又は部品の端、又は複数の回路又は部品の相互接続点を意味している。 Next, the present invention will be described with reference to the reference numerals of the drawings showing the embodiments. However, the claims and the reference numerals used here are for helping the understanding of the present invention, and do not limit the present invention.
The present invention for solving the above-described problems includes first and second DC terminals (1a, 1b) for supplying a DC voltage,
An intermediate terminal (1c) having an intermediate potential between the first and second DC terminals (1a, 1b);
A first phase AC terminal (2u) for outputting a first phase voltage of a three-phase AC voltage;
A second phase AC voltage (2v) that outputs a second phase voltage of the three-phase AC voltage, and is electrically connected to the intermediate terminal (1c);
A third phase AC terminal (2w) for outputting a third phase voltage of the three-phase AC voltage;
A series circuit of first and second switches (S1, S2) connected between the first and second DC terminals (1a, 1b);
A series circuit of third and fourth switches (S3, S4) connected between the first and second DC terminals (1a, 1b);
A first phase reactor (Lu) connected between an interconnection point (P1) of the first and second switches (S1, S2) and the first phase AC terminal (2u);
A third phase reactor (Lw) connected between the interconnection point (P2) of the third and fourth switches (S3, S4) and the third phase AC terminal (2w);
A first filter capacitor (Cu) connected between the first phase AC terminal (2u) and the second phase AC terminal (2v);
A second filter capacitor (Cw) connected between the second phase AC terminal (2v) and the third phase AC terminal (2w);
A first phase current detector (CTu) for detecting a first phase current (Iou or Isu) flowing through the first phase reactor (Lu) or the first phase AC terminal (2u);
A third phase current detector (CTw) for detecting a third phase current (Iow or Isw) flowing through the third phase reactor (Lw) or the third phase AC terminal (2w);
Voltage detecting means (5) for detecting voltages of the first and second filter capacitors (Cu, Cw), respectively;
Based on the output of the first and third phase current detectors (CTu, CTw) and the output of the voltage detection means (5), the first, second and third phase AC terminals (2u, 2v, 2w). A switch control pulse for controlling on / off of the first to fourth switches is formed so as to set the power factor at a desired value, and supplied to the control terminals of the first, second, third and fourth switches. And a control unit (6) for the three-phase V-connection inverter.
The intermediate terminal in the present invention means an end of an electric circuit or a component, or an interconnection point of a plurality of circuits or components.

なお、請求項２に示すように、前記制御部は、
前記第１及び第２のフィルタコンデンサ（Ｃu 、Ｃw ）の３相で示す電流（Ｉcu、Ｉcｖ、Ｉcw）の値を前記電圧検出手段（５）の出力を使用して計算で求めるか又は実側で求め、前記３相で示す電流（Ｉcu、Ｉcｖ、Ｉcw）の値を２相軸に変換したものに相当する第１及び第２の信号（Ｉcd、Ｉcq）を作成するコンデンサ電流値作成手段（１１又は１１ａ）と、
前記第１、第２及び第３の交流端子（２ｕ、２ｖ、２ｗ）を流れる３相電流の目標値を２相軸に変換したものに相当する第１及び第２の連系電流指令値（Ｉsd^*、Ｉsq^*）を発生する連系電流指令値発生手段（１２）と、
前記連系電流指令値発生手段（１２）から得られた前記第１の連系電流指令値（Ｉsd^*）と前記コンデンサ電流値作成手段（１１又は１１ａ）から得られた前記第１の信号（Ｉcd）とに基づいて第１相出力電流指令値（Ｉod^*）を作成し、且つ前記第２の連系電流指令値（Ｉsq^*）と前記第２の信号（Ｉcq）とに基づいて第３相出力電流指令値（Ｉoq^*）を作成する出力電流指令値作成手段（１３）と、
前記出力電流指令値作成手段（１３）から得られた前記第１相及び第３相出力電流指令値（Ｉod^*、Ｉoq^*）と前記第１相及び第３相電流検出器（ＣＴu 、ＣＴw ）から得られた前記第１相及び第３相出力電流（Ｉou、Ｉow）の検出値とに基づいて第１相及び第３相帰還制御信号（Ｉfu、Ｉfw）を形成する帰還制御信号形成手段（１４）と、
前記帰還制御信号形成手段（１４）から得られた前記第１相及び第３相帰還制御信号（Ｉfu、Ｉfw）に基づいて前記第１、第２、第３及び第４のスイッチ（Ｓ1 、Ｓ2 、Ｓ3 、Ｓ4 ）をオン・オフ制御するためのスイッチ制御パルス（Ｇ1 、Ｇ2 、Ｇ3 、Ｇ4 ）を形成するスイッチ制御パルス形成手段（１５）とから成ることが望ましい。
また、請求項３に示すように、前記電圧検出手段（５）は、前記第１及び第２のフィルタコンデンサ（Ｃu 、Ｃw ）の電圧として前記第１及び第２相交流端子（２ｕ、２ｖ）間の線間電圧（Ｖuv）、及び前記第２及び第３相交流端子（２ｖ、２ｗ）間の線間電圧（Ｖvw）を検出すると共に、及び前記第３及び第１相交流端子（２ｗ、２ｕ）間の線間電圧（Ｖwu）を検出する手段を有し、
前記コンデンサ電流値作成手段（１１）は、
基準位相角（ωｔ）を示す信号を得るために前記電圧検出手段（５）に接続された位相検出手段（２０）と、
前記基準位相角（ωｔ）よりもπ／２進んだ進み位相角（ωｔ＋π／２）を示す信号を形成する進み位相角信号形成手段（２１）と、
前記電圧検出手段（５）から得られた３相の各線間電圧（Ｖuv、Ｖvw、Ｖwu）を前記進み位相角信号形成手段（２１）から得られた進み位相角（ωｔ＋π／２）にて回転座標変換してｄｑ座標軸で示すｄ軸成分電圧（Ｖd ）とｑ軸成分電圧（Ｖq ）を出力する第１の３相／ｄｑ座標変換手段（２２）と、
前記第１の３相／ｄｑ座標変換手段（２２）から得られた前記ｄ軸成分電圧（Ｖd ）及び前記ｑ軸成分電圧（Ｖq ）を前記第１及び第２のフィルタコンデンサ（Ｃu 、Ｃw ）のそれぞれのインピーダンス（１／ωＣ）で除算した値を示すｄ軸成分仮想無効電流（Ｉad）とｑ軸成分仮想無効電流（Ｉaq）とを形成する２相軸仮想無効電流信号形成手段（２３）と、
前記２相軸仮想無効電流信号形成手段（２３）から得られた前記ｄ軸成分仮想無効電流（Ｉad）と前記ｑ軸成分仮想無効電流（Ｉaq）とを前記基準位相角（ωｔ）にて回転逆座標変換し、前記第１及び第３相交流端子間にもフィルタコンデンサが接続されていると仮定した場合における第１、第２及び第３の３相軸仮想無効電流（Ｉau、Ｉav、Ｉaw）を示す信号を出力するｄｑ／３相座標変換手段（２４）と、
前記ｄｑ／３相座標変換手段（２４）から得られた前記第１の３相軸仮想無効電流（Ｉau）を示す信号を前記第１のフィルタコンデンサ（Ｃu ）に流れる無効電流を示す第１相信号（Ｉcu）と見なして伝送する手段（２５ｕ）と、
前記第２の３相軸仮想無効電流（Ｉav）を位相反転して前記第２のフィルタコンデンサ（Ｃw ）に流れる無効電流を示す第３相信号（Ｉcw）として出力する第３相信号形成手段（２６）と、
前記第１相信号（Ｉcu）と前記第３相信号（Ｉcw）との合成信号の位相反転信号に相当する第２相信号（Ｉcv）を形成する手段（２７）と、
前記第１、第２及び第３相信号（Ｉcu、Ｉcv、Ｉcw）を前記基準位相角（ωｔ）にて回転座標変換してｄｑ座標軸で示すｄ軸成分電流（Ｉcd）とｑ軸成分電流（Ｉcq）とを出力する第２の３相／ｄｑ座標変換手段（２９）とから成ることが望ましい。
また、請求項４に示すように、前記コンデンサ電流値作成手段（１１ａ）は、
基準位相角（ωｔ）を示す信号を得るために前記電圧検出手段（５）に接続された位相検出手段（２０）と、
前記第１、第２及び第３相交流端子（２ｕ、２ｖ、２ｗ）間の電圧、周波数、及び前記第１及び第２のフィルタコンデンサ（Ｃu 、Ｃw ）の容量を固定値として前記第１及び第２のフィルタコンデンサ（Ｃu 、Ｃw ）に流れる電流を計算又は実測でそれぞれ求めた第１及び第２のフィルタコンデンサ予測電流（Ｉcu、Ｉcw）を示す信号を発生するフィルタコンデンサ予測電流発生手段（４０）と、
前記第１のフィルタコンデンサ予測電流（Ｉcu）を示す信号を第１相信号と見なして伝送する手段（２５ｕ）と、
前記第２のフィルタコンデンサ予測電流（Ｉcw）を示す信号を第３相信号として伝送する手段（２５ｗ）と、
前記第１相信号（Ｉcu）と前記第３相信号（Ｉcw）との合成信号の位相反転信号に相当する第２相信号（Ｉcv）を形成する手段（２７）と、
前記第１、第２及び第３相信号（Ｉcu、Ｉcv、Ｉcw）を前記位相検出手段（２０）から得られた前記基準位相角（ωｔ）にて回転座標変換してｄｑ座標軸で示すｄ軸成分電流（Ｉcd）とｑ軸成分電流（Ｉcq）とを出力する３相／ｄｑ座標変換手段（２９）と
から成ることが望ましい。 In addition, as shown in Claim 2, the said control part is
The value of the current (Icu, Icv, Icw) indicated by the three phases of the first and second filter capacitors (Cu, Cw) is calculated by using the output of the voltage detection means (5) or on the actual side Capacitor current value creation means for creating first and second signals (Icd, Icq) corresponding to those obtained by converting the values of the currents (Icu, Icv, Icw) indicated by the three phases into the two-phase axes. 11 or 11a)
First and second interconnected current command values (corresponding to a target value of a three-phase current flowing through the first, second and third AC terminals (2u, 2v, 2w) converted to a two-phase axis ( Interconnected current command value generating means (12) for generating Isd ^* , Isq ^* ),
The first interconnect current command value (Isd ^* ) obtained from the interconnect current command value generating means (12) and the first signal (11 or 11a) obtained from the capacitor current value creating means (11 or 11a). The first phase output current command value (Iod ^* ) is created based on Icd) and the third phase based on the second interconnection current command value (Isq ^* ) and the second signal (Icq). Output current command value creation means (13) for creating a phase output current command value (Ioq ^* );
The first and third phase output current command values (Iod ^* , Ioq ^* ) and the first and third phase current detectors (CTu, CTw) obtained from the output current command value creating means (13). Feedback control signal forming means for forming first and third phase feedback control signals (Ifu, Ifw) based on the detected values of the first phase and third phase output currents (Iou, Iow) obtained from 14)
The first, second, third and fourth switches (S1, S2) based on the first and third phase feedback control signals (Ifu, Ifw) obtained from the feedback control signal forming means (14). , S3, S4) and switch control pulse forming means (15) for generating switch control pulses (G1, G2, G3, G4) for on / off control.
According to a third aspect of the present invention, the voltage detecting means (5) includes the first and second phase AC terminals (2u, 2v) as the voltages of the first and second filter capacitors (Cu, Cw). Detecting a line voltage (Vuv) between the second and third phase AC terminals (2v, 2w), and a third and first phase AC terminal (2w, Means for detecting the line voltage (Vwu) between 2u),
The capacitor current value creating means (11)
Phase detection means (20) connected to the voltage detection means (5) to obtain a signal indicative of a reference phase angle (ωt);
A lead phase angle signal forming means (21) for forming a signal indicating a lead phase angle (ωt + π / 2) advanced by π / 2 from the reference phase angle (ωt);
The three-phase line voltages (Vuv, Vvw, Vwu) obtained from the voltage detection means (5) are rotated by the advance phase angle (ωt + π / 2) obtained from the advance phase angle signal forming means (21). A first three-phase / dq coordinate conversion means (22) for outputting a d-axis component voltage (Vd) and a q-axis component voltage (Vq) indicated by the dq coordinate axis after coordinate conversion;
The d-axis component voltage (Vd) and the q-axis component voltage (Vq) obtained from the first three-phase / dq coordinate conversion means (22) are converted into the first and second filter capacitors (Cu, Cw). Two-phase axis virtual reactive current signal forming means (23) for forming a d-axis component virtual reactive current (Iad) and a q-axis component virtual reactive current (Iaq) indicating values divided by respective impedances (1 / ωC) When,
The d-axis component virtual reactive current (Iad) and the q-axis component virtual reactive current (Iaq) obtained from the two-phase axis virtual reactive current signal forming means (23) are rotated at the reference phase angle (ωt). The first, second, and third three-phase axis virtual reactive currents (Iau, Iav, Iaw) in the case where it is assumed that a filter capacitor is connected between the first and third phase AC terminals by inverse coordinate transformation. Dq / 3-phase coordinate conversion means (24) for outputting a signal indicating
A first phase indicating a reactive current flowing through the first filter capacitor (Cu) with a signal indicating the first three-phase axis virtual reactive current (Iau) obtained from the dq / 3-phase coordinate conversion means (24). Means (25u) for transmitting as a signal (Icu);
Third phase signal forming means for outputting a third phase signal (Icw) indicating a reactive current flowing through the second filter capacitor (Cw) by inverting the phase of the second three-phase virtual reactive current (Iav). 26)
Means (27) for forming a second phase signal (Icv) corresponding to a phase inverted signal of a composite signal of the first phase signal (Icu) and the third phase signal (Icw);
The first, second and third phase signals (Icu, Icv, Icw) are subjected to rotational coordinate conversion at the reference phase angle (ωt), and d-axis component current (Icd) and q-axis component current ( It is desirable to comprise second three-phase / dq coordinate conversion means (29) for outputting Icq).
Further, as shown in claim 4, the capacitor current value creating means (11a)
Phase detection means (20) connected to the voltage detection means (5) to obtain a signal indicative of a reference phase angle (ωt);
The voltage between the first, second and third phase AC terminals (2u, 2v, 2w), the frequency, and the capacitance of the first and second filter capacitors (Cu, Cw) are fixed values. Filter capacitor predicted current generating means (40) for generating a signal indicating the first and second filter capacitor predicted currents (Icu, Icw) obtained by calculation or actual measurement of the current flowing through the second filter capacitors (Cu, Cw), respectively. )When,
Means (25u) for transmitting a signal indicating the first filter capacitor predicted current (Icu) as a first phase signal;
Means (25w) for transmitting a signal indicating said second filter capacitor predicted current (Icw) as a third phase signal;
Means (27) for forming a second phase signal (Icv) corresponding to a phase inverted signal of a composite signal of the first phase signal (Icu) and the third phase signal (Icw);
The d-axis indicated by the dq coordinate axis by rotationally converting the first, second and third phase signals (Icu, Icv, Icw) at the reference phase angle (ωt) obtained from the phase detecting means (20). It is desirable to comprise three-phase / dq coordinate conversion means (29) for outputting the component current (Icd) and the q-axis component current (Icq).

本発明は次の効果を有する。
（１）力率制御可能な３相Ｖ結線インバータにおいて交流端子に流れる連系電流を直接に検出するための電流検出器が不要になり、この分だけコストの低減を図ることができる。
（２）３相Ｖ結線インバータであるので、３相ブリッジ型インバータに比べて変換用スイッチの個数を減らすことが可能になり、インバータのコストの低減を図ることができる。
請求項２〜４の発明によれば、３相Ｖ結線インバータの制御を容易に達成することが可能になる。 The present invention has the following effects.
(1) In the three-phase V-connection inverter capable of power factor control, a current detector for directly detecting the interconnection current flowing in the AC terminal is not necessary, and the cost can be reduced by this amount.
(2) Since the inverter is a three-phase V-connection inverter, the number of conversion switches can be reduced as compared with a three-phase bridge inverter, and the cost of the inverter can be reduced.
According to the second to fourth aspects of the invention, it is possible to easily achieve control of the three-phase V-connection inverter.

次に、図１〜図５を参照して本発明の実施形態を説明する。 Next, an embodiment of the present invention will be described with reference to FIGS.

図１は本発明の実施例１に従う３相Ｖ結線インバータを含む電力系統を示す。３相Ｖ結線インバータの第１及び第２の直流端子１ａ、１ｂは、燃料電池、太陽電池、蓄電池、整流平滑回路、又は昇圧チョッパ回路等から成る直流電源１に接続されている。直流電源１の電圧Ｖdcを分割するために、第１及び第２の直流端子１ａ、１ｂ間に実質的に同一容量の第１及び第２の電圧分割用コンデンサＣa 、Ｃb の直列回路が接続されている。第１及び第２の電圧分割用コンデンサＣa 、Ｃb の相互接続点に相当する中間端子１ｃの電位は、第１及び第２の直流端子１ａ、１ｂの電位の中間の値を有する。なお、直流電源１を省き、且つ第１及び第２の電圧分割用コンデンサＣa 、Ｃb の代りに実質的に同一電圧の第１及び第２の直流電源を設けることもできる。 FIG. 1 shows an electric power system including a three-phase V-connection inverter according to Embodiment 1 of the present invention. The first and second DC terminals 1a and 1b of the three-phase V-connection inverter are connected to a DC power source 1 composed of a fuel cell, a solar cell, a storage battery, a rectifying / smoothing circuit, a boost chopper circuit, or the like. In order to divide the voltage Vdc of the DC power source 1, a series circuit of first and second voltage dividing capacitors Ca and Cb having substantially the same capacity is connected between the first and second DC terminals 1a and 1b. ing. The potential of the intermediate terminal 1c corresponding to the interconnection point of the first and second voltage dividing capacitors Ca and Cb has an intermediate value between the potentials of the first and second DC terminals 1a and 1b. The DC power supply 1 can be omitted, and the first and second DC power supplies having substantially the same voltage can be provided in place of the first and second voltage dividing capacitors Ca and Cb.

３相Ｖ結線インバータのＤＣ−ＡＣ変換回路を構成するために第１及び第２のスイッチＳ1 、Ｓ2 の直列回路、及び第３及び第４のスイッチＳ3 、Ｓ4 の直列回路が第１及び第２の直流端子１ａ、１ｂ間に接続されている。第１及び第２のスイッチＳ1 、Ｓ2 の直列回路を第１相（Ｕ相）スイッチング回路又は第１相ハーフブリッジスイッチング回路と呼び、また第３及び第４のスイッチＳ3 、Ｓ4 の直列回路を第３相（Ｗ相）スイッチング回路又は第３相ハーフブリッジスイッチング回路と呼ぶこともできる。
なお、第１〜第４のスイッチＳ1 〜Ｓ4 はＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ）で示されているが、これ等をＮＰＮ型又はＰＮＰ型トランジスタ、電界効果トランジスタ等の別のオン・オフ制御可能な半導体スイッチ等とすることができる。 In order to constitute a DC-AC conversion circuit of a three-phase V-connection inverter, a series circuit of first and second switches S1, S2 and a series circuit of third and fourth switches S3, S4 are first and second. DC terminals 1a and 1b. The series circuit of the first and second switches S1, S2 is called a first-phase (U-phase) switching circuit or a first-phase half-bridge switching circuit, and the series circuit of the third and fourth switches S3, S4 is called a first circuit. It can also be called a three-phase (W-phase) switching circuit or a third-phase half-bridge switching circuit.
The first to fourth switches S1 to S4 are IGBTs (insulated gate type bipolar transistors), but these can be controlled on / off differently such as NPN type or PNP type transistors, field effect transistors, etc. A semiconductor switch or the like.

第１〜第４のスイッチＳ1 〜Ｓ4 に逆方向並列に第１〜第４のダイオードＤ1 〜Ｄ4 が接続されている。この第１〜第４のダイオードＤ1 〜Ｄ4 は個別ダイオードであってもよいし、第１〜第４のスイッチＳ1 〜Ｓ4 の半導体基体中に形成される周知の寄生即ち内蔵ダイオードであってもよい。第１〜第４のダイオードＤ1 〜Ｄ4 は第１、第２及び第３相交流端子２ｕ、２ｖ、２ｗ側から直流電源１側に電力を回生する時に導通する方向性を有する。 First to fourth diodes D1 to D4 are connected in reverse parallel to the first to fourth switches S1 to S4. The first to fourth diodes D1 to D4 may be individual diodes, or may be well-known parasitic or built-in diodes formed in the semiconductor substrate of the first to fourth switches S1 to S4. . The first to fourth diodes D1 to D4 have a direction of conduction when power is regenerated from the first, second and third phase AC terminals 2u, 2v and 2w to the DC power source 1 side.

第１、第２及び第３相交流端子２ｕ、２ｖ、２ｗは、互いに１２０度の位相差を有する第１、第２及び第３の線間電圧Ｖuv、Ｖvw、Ｖwuを出力するものであり、３相交流電力系統３又は３相負荷回路に接続される。 The first, second and third phase AC terminals 2u, 2v and 2w output the first, second and third line voltages Vuv, Vvw and Vwu having a phase difference of 120 degrees with respect to each other. It is connected to the three-phase AC power system 3 or the three-phase load circuit.

第１相リアクトルＬu は第１及び第２のスイッチＳ1 、Ｓ2 の相互接続点Ｐ1 と第１相交流端子２ｕとの間に直列に接続されている。第３相リアクトルＬw は第３及び第４のスイッチＳ3 、Ｓ4 の相互接続点Ｐ2 と第３相交流端子２ｗとの間に直列に接続されている。第１相及び第３相リアクトルＬu 、Ｌw は第１〜第４のスイッチＳ1 〜Ｓ4 のオン・オフによる高周波成分を除去するフィルタとして機能する。 The first phase reactor Lu is connected in series between the interconnection point P1 of the first and second switches S1, S2 and the first phase AC terminal 2u. The third phase reactor Lw is connected in series between the interconnection point P2 of the third and fourth switches S3 and S4 and the third phase AC terminal 2w. The first-phase and third-phase reactors Lu and Lw function as filters that remove high-frequency components caused by turning on and off the first to fourth switches S1 to S4.

第１のフィルタコンデンサＣu は第１及び第２相交流端子２ｕ、２ｖ間に接続されている。第２のフィルタコンデンサＣw は第１のフィルタコンデンサＣu と実質的に同一の容量Ｃを有して第２及び第３相交流端子２ｖ、２ｗ間に接続されている。第１及び第２のフィルタコンデンサＣu 、Ｃw は第１〜第４のスイッチＳ1〜Ｓ4 のオン・オフによる高周波成分を除去するものである。 The first filter capacitor Cu is connected between the first and second phase AC terminals 2u, 2v. The second filter capacitor Cw has substantially the same capacitance C as the first filter capacitor Cu and is connected between the second and third phase AC terminals 2v, 2w. The first and second filter capacitors Cu and Cw are for removing high-frequency components due to on / off of the first to fourth switches S1 to S4.

第２相交流端子２ｖは第１及び第２の電圧分割用コンデンサＣa 、Ｃb の相互接続点即ち中間端子１ｃに接続されている。従って、第１及び第２のスイッチＳ1 、Ｓ2 と第１相リアクトルＬu とによって第１相ハーフブリッジ型変換回路が構成され、また、第３及び第４のスイッチＳ3 、Ｓ4 と第３相リアクトルＬw とによって第３相ハーフブリッジ型変換回路が構成されている。 The second-phase AC terminal 2v is connected to the interconnection point of the first and second voltage dividing capacitors Ca and Cb, that is, the intermediate terminal 1c. Accordingly, the first and second switches S1 and S2 and the first phase reactor Lu constitute a first phase half-bridge type conversion circuit, and the third and fourth switches S3 and S4 and the third phase reactor Lw. A third-phase half-bridge conversion circuit is configured by the above.

第１〜第４のスイッチＳ1 〜Ｓ4 を力率制御可能にオン・オフ制御するための制御回路４は、ＣＴ（電流トランス）で例示されている第１相及び第３相電流検出器ＣＴu 、ＣＴw と、電圧検出手段５と、制御部６とから成る。 A control circuit 4 for on / off controlling the first to fourth switches S1 to S4 so as to be capable of power factor control includes a first phase and a third phase current detector CTu exemplified by CT (current transformer), It comprises CTw, voltage detection means 5 and control unit 6.

第１相電流検出器ＣＴu は、第１及び第２のスイッチＳ1 、Ｓ2 の相互接続点Ｐ1 と第１のフィルタコンデンサＣu の一端との間の第１相電流通路７ｕに電磁結合され、第１相電流通路７ｕを流れる第１相出力電流Ｉou（瞬時値）を検出し、これをライン８ｕで制御部６に送る。第２相電流検出器ＣＴw は、第３及び第４のスイッチＳ3 、Ｓ4 の相互接続点Ｐ2 と第２のフィルタコンデンサＣw の一端との間の第３相電流通路７ｗに電磁結合され、第３相電流通路７ｗを流れる第３相出力電流Ｉow（瞬時値）を検出し、これをライン８ｗで制御部６に送る。なお、ここでは説明を簡単にするために第１相及び第３相電流通路７ｕ、７ｗの電流と第１相及び第３相電流検出器ＣＴu 、ＣＴw の電流を同一のＩou、Ｉowで示すことにする。 The first phase current detector CTu is electromagnetically coupled to the first phase current path 7u between the interconnection point P1 of the first and second switches S1, S2 and one end of the first filter capacitor Cu. The first phase output current Iou (instantaneous value) flowing through the phase current path 7u is detected and sent to the control unit 6 via the line 8u. The second phase current detector CTw is electromagnetically coupled to the third phase current path 7w between the interconnection point P2 of the third and fourth switches S3 and S4 and one end of the second filter capacitor Cw. A third phase output current Iow (instantaneous value) flowing through the phase current passage 7w is detected and sent to the control unit 6 via a line 8w. In order to simplify the explanation, the currents of the first and third phase current paths 7u and 7w and the currents of the first and third phase current detectors CTu and CTw are indicated by the same Iou and Iow. To.

この実施例では、第１、第２及び第３相交流端子２ｕ、２ｖ、２ｗにおける力率を所望値（好ましくは１）に制御するにも拘らず、第１、第２及び第３相交流端子２ｕ、２ｖ、２ｗを流れる第１、第２及び第３相連系電流Ｉsu、Ｉsv、Ｉswを検出するための電流検出器が設けられていない。この電流検出器の代りに、図１の実施例では、電圧検出手段５が設けられている。電圧検出手段５は、第１のフィルタコンデンサＣu の電圧即ち第１及び第２相交流端子２ｕ、２ｖ間の線間電圧Ｖuv（瞬時値）を検出する第１の電圧検出回路５ａと、第２のフィルタコンデンサＣw の電圧即ち第２及び第３相交流端子２ｖ、２ｗ間の線間電圧Ｖvw（瞬時値）を検出する第２の電圧検出回路５ｂと、第１及び第２の電圧検出回路５ａ、５ｂの出力を位相反転して加算して第３及び第１相交流端子２ｗ、２ｕ間の線間電圧Ｖwu（瞬時値）を検出する第３の電圧検出回路５ｃとから成る。なお、第３の電圧検出回路５ｃを第１及び第２の電圧検出回路５ａ、５ｂに接続する代りに、第１及び第３の交流端子２ｕ、２ｗに接続して直接的に線間電圧Ｖwuを求めることもできる。本実施例では、説明を容易にするために第１、第２及び第３相交流端子２ｕ、２ｖ、２ｗにおける線間電圧と第１、第２及び第３の電圧検出回路５ａ、５ｂ、５ｃの出力電圧とを同一のＶuv、Ｖvw、Ｖwuで示すことにする。第１、第２及び第３の電圧検出回路５ａ、５ｂ、５ｃの出力ライン９uv、９vw、９wuは制御部６に接続されている。 In this embodiment, the first, second and third phase alternating currents are controlled in spite of controlling the power factor at the first, second and third phase alternating current terminals 2u, 2v and 2w to a desired value (preferably 1). A current detector for detecting the first, second and third phase interconnection currents Isu, Isv and Isw flowing through the terminals 2u, 2v and 2w is not provided. Instead of this current detector, a voltage detecting means 5 is provided in the embodiment of FIG. The voltage detection means 5 includes a first voltage detection circuit 5a for detecting a voltage of the first filter capacitor Cu, that is, a line voltage Vuv (instantaneous value) between the first and second phase AC terminals 2u and 2v, and a second voltage detection circuit 5a. A second voltage detection circuit 5b for detecting the voltage of the filter capacitor Cw, that is, the line voltage Vvw (instantaneous value) between the second and third phase AC terminals 2v and 2w, and the first and second voltage detection circuits 5a. And a third voltage detection circuit 5c for detecting a line voltage Vwu (instantaneous value) between the third and first phase AC terminals 2w and 2u by inverting and adding the outputs of 5b. Instead of connecting the third voltage detection circuit 5c to the first and second voltage detection circuits 5a and 5b, it is connected to the first and third AC terminals 2u and 2w and directly connected to the line voltage Vwu. Can also be requested. In the present embodiment, for ease of explanation, the line voltage at the first, second and third phase AC terminals 2u, 2v and 2w and the first, second and third voltage detection circuits 5a, 5b and 5c are described. Are expressed by the same Vuv, Vvw, and Vwu. Output lines 9uv, 9vw, 9wu of the first, second and third voltage detection circuits 5a, 5b, 5c are connected to the control unit 6.

制御部６は、第１及び第２相電流検出器ＣＴu 、ＣＴw から得られた第１及び第３相出力電流Ｉou、Ｉowと電圧検出手段５から得られた第１及び第２相間の線間電圧Ｖuv、第２及び第３相間の線間電圧Ｖvw、及び第３相及び第１相間の線間電圧Ｖwuとに基づいて第１、第２及び第３相交流端子２ｕ、２ｖ、２ｗを流れる第１、第２及び第３相連系電流Ｉsu、Ｉsv、Ｉswを所望力率（好ましくは１）になるように制御するための第１、第２、第３及び第４のスイッチ制御パルスＧ1 、Ｇ2 、Ｇ3 、Ｇ4 を形成して第１、第２、第３及び第４のスイッチＳ1 、Ｓ2 、Ｓ3 、Ｓ4 の制御端子（ゲート）に送る。 The control unit 6 is configured to connect the first and third phase output currents Iou and Iow obtained from the first and second phase current detectors CTu and CTw and the line between the first and second phases obtained from the voltage detection means 5. Based on the voltage Vuv, the line voltage Vvw between the second and third phases, and the line voltage Vwu between the third phase and the first phase, the first, second and third phase AC terminals 2u, 2v and 2w flow. First, second, third and fourth switch control pulses G1, for controlling the first, second and third phase interconnection currents Isu, Isv, Isw to have a desired power factor (preferably 1), G2, G3 and G4 are formed and sent to the control terminals (gates) of the first, second, third and fourth switches S1, S2, S3 and S4.

図２は図１の制御部６を詳しく示すブロック図である。この制御部６はこの多くの部分をＤＳＰ（ディジタル信号処理装置）又はマイコン等のディジタル回路で形成することができるものであり、大別してコンデンサ電流値作成手段１１と、連系電流指令値発生手段１２と、出力電流指令値作成手段１３と、帰還制御信号形成手段１４と、スイッチ制御パルス形成手段１５とから成る。 FIG. 2 is a block diagram showing in detail the control unit 6 of FIG. The control unit 6 can form many parts by a digital circuit such as a DSP (digital signal processing device) or a microcomputer, and is roughly divided into a capacitor current value creating means 11 and an interconnection current command value generating means. 12, output current command value creating means 13, feedback control signal forming means 14, and switch control pulse forming means 15.

コンデンサ電流値作成手段１１は、図１の電圧検出手段５の出力ライン９ｕv、９vw、９wuに接続され、第１及び第２のフィルタコンデンサＣu 、Ｃw の３相で示される電流Ｉcu、Ｉcｖ、Ｉcwの値を計算で求め、この計算値を２相軸で示す第１及び第２の信号Ｉcd、Ｉcqに変換して出力する。このコンデンサ電流値作成手段１１から出力される第１及び第２の信号Ｉcd、Ｉcqは、周知の３相／ｄｑ座標変換されたｄ軸成分及びｑ軸成分を示している。従って、以下の説明において第１の信号Ｉcdをｄ軸成分電流と呼び、第２の信号Ｉcqをｑ軸成分電流と呼びこともある。このコンデンサ電流値作成手段１１の詳細は後述する。 The capacitor current value creating means 11 is connected to the output lines 9uv, 9vw, 9wu of the voltage detecting means 5 of FIG. 1, and currents Icu, Icv, Icw indicated by the three phases of the first and second filter capacitors Cu, Cw. Is obtained by calculation, and the calculated value is converted into first and second signals Icd and Icq indicated by a two-phase axis and output. The first and second signals Icd and Icq output from the capacitor current value creating unit 11 indicate the d-axis component and the q-axis component which are well-known three-phase / dq coordinate transformed. Therefore, in the following description, the first signal Icd may be referred to as a d-axis component current, and the second signal Icq may be referred to as a q-axis component current. Details of the capacitor current value creating means 11 will be described later.

連系電流指令値発生手段１２は、第１、第２及び第３相交流端子２ｕ、２ｖ、２ｗを流れる第１、第２及び第３相連系電流Ｉsu、Ｉsv、Ｉsw（瞬時値）の目標値を示す第１、第２及び第３相目標連系電流Ｉsu′、Ｉsv′、Ｉsw′を周知の３相／ｄｑ座標変換して得たｄ軸成分目標連系電流及びｑ軸成分目標連系電流に相当する第１及び第２の連系電流指令値Ｉsd^*、Ｉsq^*を発生する。第１及び第２の連系電流指令値Ｉsd^*、Ｉsq^*は任意に設定することができる。また、連系電流指令値発生手段１２を演算回路で構成し、第１及び第２の連系電流指令値Ｉsd^*、Ｉsq^*の値を演算で求めることもできる。第１及び第２の連系電流指令値Ｉsd^*、Ｉsq^*は、連系電流の周波数をω、実効値をＩ、力率をcos θとした時に、次の（１）の行列式で示すことができる。 The interconnection current command value generation means 12 is a target of the first, second and third phase interconnection currents Isu, Isv, Isw (instantaneous values) flowing through the first, second and third phase AC terminals 2u, 2v, 2w. D-axis component target interconnection current and q-axis component target linkage obtained by converting the first, second and third phase target interconnection currents Isu ', Isv' and Isw 'indicating the values by known three-phase / dq coordinate transformation. First and second interconnection current command values Isd ^* and Isq ^* corresponding to the system current are generated. The first and second interconnection current command values Isd ^* and Isq ^* can be arbitrarily set. Further, the interconnection current command value generating means 12 can be constituted by an arithmetic circuit, and the values of the first and second interconnection current command values Isd ^* and Isq ^* can be obtained by calculation. The first and second interconnection current command values Isd ^* and Isq ^* are expressed by the following determinant of (1), where the frequency of the interconnection current is ω, the effective value is I, and the power factor is cos θ. be able to.

図２の出力電流指令値作成手段１３は、連系電流指令値発生手段１２から得られた第１の連系電流指令値Ｉsd^*にコンデンサ電流値作成手段１１から得られたｄ軸成分信号Ｉcdを加算して第１相出力電流指令値Ｉod^* を作成し、且つ第２の連系電流指令値Ｉsq^*にコンデンサ電流作成手段１１から得られたｑ軸成分信号Ｉcqを加算して第３相出力電流指令値Ｉoq^*を作成する。この出力電流指令値作成手段１３の詳細は後述する。 The output current command value creating means 13 shown in FIG. 2 adds the d-axis component signal Icd obtained from the capacitor current value creating means 11 to the first linked current command value Isd ^* obtained from the connected current command value generating means 12. Is added to create the first phase output current command value Iod ^* , and the second phase current command value Isq ^* is added to the q-axis component signal Icq obtained from the capacitor current creating means 11 to add the third phase. Create output current command value Ioq ^* . Details of the output current command value creating means 13 will be described later.

帰還制御信号形成手段１４は、出力電流指令値作成手段１３から得られた第１相及び第３相出力電流指令値Ｉod^*、Ｉoq^*と第１相及び第３相電流検出器ＣＴu 、ＣＴw から得られたライン８ｕ、８ｗの第１相及び第３相出力電流Ｉou、Ｉowとに基づいて第１相及び第３相帰還制御信号Ｉfu、Ｉfwを形成する。この帰還制御信号形成手段１４の詳細は後述する。 The feedback control signal forming means 14 is based on the first and third phase output current command values Iod ^* and Ioq ^* obtained from the output current command value creating means 13 and the first and third phase current detectors CTu and CTw. Based on the obtained first and third phase output currents Iou and Iow of the lines 8u and 8w, first and third phase feedback control signals Ifu and Ifw are formed. Details of the feedback control signal forming means 14 will be described later.

スイッチ制御パルス形成手段１５は、帰還制御信号形成手段１４から得られた第１相及び第３相帰還制御信号Ｉfu、Ｉfwに基づいて第１、第２、第３及び第４のスイッチＳ1 、Ｓ2 、Ｓ3 、Ｓ4 をオン・オフ制御するための周知のスイッチ制御パルスＧ1 、Ｇ2 、Ｇ3 、Ｇ4 を形成する。このスイッチ制御パルス形成手段１５の詳細は後述する。 The switch control pulse forming means 15 includes first, second, third and fourth switches S1, S2 based on the first phase and third phase feedback control signals Ifu, Ifw obtained from the feedback control signal forming means 14. , S3, S4 are formed with known switch control pulses G1, G2, G3, G4 for ON / OFF control. Details of the switch control pulse forming means 15 will be described later.

図３は図２の制御部６を更に詳しく示すブロック図である。この図３から明らかなようにコンデンサ電流値作成手段１１は、位相検出手段２０を有している。この位相検出手段２０は、図１の電圧検出手段５の出力ライン９uv、９vwに接続され、出力電圧Ｖuv、Ｖvwの基準位相角ωｔを示す信号を出力する。 FIG. 3 is a block diagram showing the control unit 6 of FIG. 2 in more detail. As apparent from FIG. 3, the capacitor current value creating means 11 has a phase detecting means 20. The phase detection means 20 is connected to the output lines 9uv and 9vw of the voltage detection means 5 of FIG. 1, and outputs a signal indicating the reference phase angle ωt of the output voltages Vuv and Vvw.

位相検出手段２０に接続された進み位相角信号形成手段２１は、π／２発生器２１ａと加算手段２２ｂとを有する。加算手段２２ｂは、位相検出手段２０から得られた基準位相角ωｔにπ／２発生器２１ａから得られた位相角π／２即ち９０度を加算してωｔ＋π／２から成る進み位相角信号を形成する。 The lead phase angle signal forming means 21 connected to the phase detecting means 20 has a π / 2 generator 21a and an adding means 22b. The adding means 22b adds the phase angle π / 2 obtained from the π / 2 generator 21a to the reference phase angle ωt obtained from the phase detecting means 20, that is, 90 degrees, to obtain a lead phase angle signal composed of ωt + π / 2. Form.

図１の電圧検出手段５の３相の出力ライン９uv、９vw、９wuと進み位相角信号形成手段２１に接続された第１の３相／ｄｑ座標変換手段２２は、電圧検出手段５から得られた３相の各線間電圧Ｖuv、Ｖvw、Ｖwuを進み位相角信号形成手段２１から得られた進み位相角（ωｔ＋π／２）にて回転座標変換してｄｑ座標軸で示すｄ軸成分電圧Ｖd とｑ軸成分電圧Ｖq とを出力する。即ち、第１の３相／ｄｑ座標変換手段２２では、回転座標変換を用いて、３相から２相に変換する。この第１の３相／ｄｑ座標変換手段２２に入力される３相の線間電圧Ｖuv、Ｖvw、Ｖwuは次の（２）式で示すことができ、進み位相角ωｔ＋π／２による座標変換行列Ｔは次の（３）式で示すことができ、第１の３相／ｄｑ座標変換手段２２から得られるｄ軸成分電圧Ｖd 及びｑ軸成分電圧Ｖq は次の（４）式で示すことができ、その結果は次の（５）式で示すことができる。なお、次の（２）〜（５）式において、Ｖは第１、第２及び第３相交流端子２ｕ、２ｖ、２ｗにおける各線間電圧の実効値を示し、Ｖs は瞬時値で示す各線間電圧Ｖuv、Ｖvw、Ｖwuを総括して示し、Ｖdqは瞬時値で示すｄ軸成分電圧Ｖd とｑ軸成分電圧Ｖq とを一括して示す。 The three-phase output lines 9uv, 9vw, 9wu of the voltage detection means 5 of FIG. 1 and the first three-phase / dq coordinate conversion means 22 connected to the advance phase angle signal forming means 21 are obtained from the voltage detection means 5. The three-phase line voltages Vuv, Vvw, and Vwu are converted into rotational coordinates at the advance phase angle (ωt + π / 2) obtained from the advance phase angle signal forming means 21, and d-axis component voltages Vd and q indicated by the dq coordinate axes are used. The shaft component voltage Vq is output. That is, the first three-phase / dq coordinate conversion means 22 converts from three phases to two phases using rotational coordinate conversion. The three-phase line voltages Vuv, Vvw, Vwu input to the first three-phase / dq coordinate conversion means 22 can be expressed by the following equation (2), and a coordinate conversion matrix based on the lead phase angle ωt + π / 2. T can be expressed by the following equation (3), and the d-axis component voltage Vd and the q-axis component voltage Vq obtained from the first three-phase / dq coordinate conversion means 22 can be expressed by the following equation (4). The result can be shown by the following equation (5). In the following equations (2) to (5), V represents the effective value of each line voltage at the first, second and third phase AC terminals 2u, 2v and 2w, and Vs represents the line-to-line value represented by the instantaneous value. The voltages Vuv, Vvw, and Vwu are collectively shown, and Vdq is a d-axis component voltage Vd and a q-axis component voltage Vq that are instantaneous values.

第１の３相／ｄｑ座標変換手段２２に接続された２相軸仮想無効電流信号形成手段２３は、第１及び第２の乗算器２３ａ、２３ｂから成る。第１の３相／ｄｑ座標変換手段２２に接続された第１及び第２の乗算器２３ａ、２３ｂは、第１の３相／ｄｑ座標変換手段２２から得られたｄ軸成分電圧Ｖd 及びｑ軸成分電圧Ｖq にωＣを乗算してｄ軸成分仮想無効電流Ｉad及びｑ軸成分仮想無効電流Ｉaqを形成する。ここで、ωは基本波の角周波数を示し、Ｃは第１及び第２のフィルタコンデンサＣu 、Ｃw の容量を示す。ここでは、第１及び第２の乗算器２３ａ、２３ｂでｄ軸及びｑ軸成分仮想無効電流Ｉad、Ｉaqを求めたが、ｄ軸及びｑ軸成分電圧Ｖd 、Ｖq を第１及び第２のフィルタコンデンサＣu 、Ｃw のインピーダンス１／ωＣで除算してｄ軸及びｑ軸成分仮想無効電流Ｉad、Ｉaqに変換することもできる。ここでのｄ軸及びｑ軸成分仮想無効電流Ｉad、Ｉaqは図１の第１及び第３相交流端子２ｕ、２ｗ間にも第１及び第２のフィルタコンデンサＣu 、Ｃw と同一容量のフィルタコンデンサが接続され、３相平衡なフィルタコンデンサ回路が形成されていると仮定した場合の値を示している。 The two-phase axis virtual reactive current signal forming unit 23 connected to the first three-phase / dq coordinate conversion unit 22 includes first and second multipliers 23a and 23b. The first and second multipliers 23 a and 23 b connected to the first three-phase / dq coordinate conversion means 22 are connected to the d-axis component voltages Vd and q obtained from the first three-phase / dq coordinate conversion means 22. The axial component voltage Vq is multiplied by ωC to form the d-axis component virtual reactive current Iad and the q-axis component virtual reactive current Iaq. Here, ω represents the angular frequency of the fundamental wave, and C represents the capacitance of the first and second filter capacitors Cu and Cw. Here, the d-axis and q-axis component virtual reactive currents Iad and Iaq are obtained by the first and second multipliers 23a and 23b, but the d-axis and q-axis component voltages Vd and Vq are converted into the first and second filters. Dividing by the impedance 1 / ωC of the capacitors Cu and Cw can also be converted into d-axis and q-axis component virtual reactive currents Iad and Iaq. The d-axis and q-axis component virtual reactive currents Iad and Iaq here are filter capacitors having the same capacity as the first and second filter capacitors Cu and Cw between the first and third phase AC terminals 2u and 2w in FIG. Are connected to each other, and a value is shown assuming that a three-phase balanced filter capacitor circuit is formed.

２相軸仮想無効電流信号形成手段２３及び位相検出手段２０に接続された逆座標変換手段即ちｄｑ／３相座標変換手段２４は、２相軸仮想無効電流信号形成手段２３から得られたｄ軸成分仮想無効電流Ｉadとｑ軸成分仮想無効電流Ｉaq とを基準位相角（ωｔ）にて回転逆座標変換し、第１及び第３相交流端子２ｕ、２ｗ間にもフィルタコンデンサが接続されていると仮定した場合における第１、第２及び第３の３相軸仮想無効電流Ｉau、Ｉav、Ｉawを示す信号を出力する。このｄｑ／３相座標変換手段２４の入力を次の（６）式で示し、逆座標変換行列Ｔ2 を次の（７）式で示し、３相出力を次の（８）式で示し、その結果を（９）式で示すことができる。ここで、Ｉadq はｄ軸及びｑ軸成分仮想無効電流Ｉad、Ｉaqを一括して示し、Ｉauvwは３相軸仮想無効電流Ｉau、Ｉav、Ｉawを一括して示す。 The inverse coordinate conversion means connected to the two-phase axis virtual reactive current signal forming means 23 and the phase detection means 20, that is, the dq / 3-phase coordinate conversion means 24 is the d-axis obtained from the two-phase axis virtual reactive current signal forming means 23. The component virtual reactive current Iad and the q-axis component virtual reactive current Iaq are subjected to rotational inverse coordinate conversion at the reference phase angle (ωt), and a filter capacitor is also connected between the first and third phase AC terminals 2u and 2w. Are output signals indicating the first, second, and third three-phase axis virtual reactive currents Iau, Iav, Iaw. The input of the dq / 3-phase coordinate conversion means 24 is expressed by the following equation (6), the inverse coordinate conversion matrix T2 is expressed by the following equation (7), and the three-phase output is expressed by the following equation (8). A result can be shown by (9) Formula. Here, Iadq collectively indicates the d-axis and q-axis component virtual reactive currents Iad and Iaq, and Iauvw collectively indicates the three-phase axial virtual reactive currents Iau, Iav, and Iaw.

ｄｑ／３相座標変換手段２４に接続された無効電流検出部２５は、位相反転手段２６と終端手段２８とで示されている。ｄｑ／３相座標変換手段２４は、フィルタコンデンサが第１及び第３相交流端子２ｕ、２ｗ間にも接続されていると仮定した３相平衡コンデンサ回路の場合における２相入力を３相に変換し且つ逆回転座標変換している。従って、ｄｑ／３相座標変換手段２４の出力から第１及び第２のフィルタコンデンサＣu 、Ｃw の実際の電流を示す信号を形成する必要がある。そこで、無効電流検出部２５は、ｄｑ／３相座標変換手段２４の第１の３相軸仮想無効電流Ｉauを第１のフィルタコンデンサＣu に流れる無効電流を示す第１相信号Ｉcuと見なして伝送する手段としての伝送路２５ｕと、第２の３相軸仮想無効電流Ｉavを位相反転して第２のフィルタコンデンサＣw に流れる無効電流を示す第３相信号Ｉcwと見なして出力する第３相信号形成手段２６と、第３の３相軸仮想無効電流Ｉawを終端する終端手段２８とを有する。なお、終端手段２８は第３の３相軸仮想無効電流Ｉawを使用しないための信号終端手段である。 The reactive current detection unit 25 connected to the dq / 3-phase coordinate conversion unit 24 is indicated by a phase inversion unit 26 and a termination unit 28. The dq / 3-phase coordinate conversion means 24 converts the two-phase input into the three-phase in the case of a three-phase balanced capacitor circuit assuming that the filter capacitor is also connected between the first and third phase AC terminals 2u and 2w. And reverse rotation coordinate conversion. Therefore, it is necessary to form a signal indicating the actual current of the first and second filter capacitors Cu and Cw from the output of the dq / 3-phase coordinate conversion means 24. Therefore, the reactive current detection unit 25 regards the first three-phase virtual virtual reactive current Iau of the dq / 3-phase coordinate conversion means 24 as the first phase signal Icu indicating the reactive current flowing through the first filter capacitor Cu and transmits it. And a third phase signal that is output as a third phase signal Icw indicating a reactive current flowing through the second filter capacitor Cw by inverting the phase of the second three-phase virtual reactive current Iav Forming means 26 and termination means 28 for terminating the third three-phase virtual reactive current Iaw are provided. The termination means 28 is a signal termination means for not using the third three-phase axis virtual reactive current Iaw.

第２の３相／ｄｑ座標変換手段２９に、第１及び第２のフィルタコンデンサＣu 、Ｃw の電流（無効電流）を示す第１相及び第３相信号Ｉcu、Ｉcwの伝送路２５ｕ、２５ｗが接続され、且つ第２相信号Ｉcvを形成するための第２相信号形成手段２７の出力伝送路２５ｖが接続されている。第２相信号形成手段２７は、第１相信号Ｉcuと第３相信号Ｉcwとの合成信号（加算信号）の位相反転信号に相当する第２相信号Ｉcvを形成する。 In the second three-phase / dq coordinate conversion means 29, transmission paths 25u and 25w for the first and third phase signals Icu and Icw indicating the currents (reactive currents) of the first and second filter capacitors Cu and Cw are provided. The output transmission path 25v of the second phase signal forming means 27 is connected to form the second phase signal Icv. The second phase signal forming means 27 forms a second phase signal Icv corresponding to a phase inversion signal of a combined signal (addition signal) of the first phase signal Icu and the third phase signal Icw.

第１、第２及び第３相信号Ｉcu、Ｉcv、Ｉcwの伝送路２５ｕ、２５ｖ、２５ｗ及び位相検出手段２０に接続された第2の３相／ｄｑ座標変換手段２９は、第１、第２及び第３相信号Ｉcu、Ｉcv、Ｉcwを基準位相角ωｔにて回転座標変換してｄｑ座標軸で示すｄ軸成分電流Ｉcdとｑ軸成分電流Ｉcqとから成る２相信号を出力する。この第２の３相／ｄｑ座標変換手段２９の入力、座標変換行列Ｔ3 、及び出力を次の（１０）（１１）（１２）式で示すことができる。これ等の式において、Ｉcuvwは入力する第１、第２及び第３相信号Ｉcu、Ｉcv、Ｉcwを一括して示し、Ｉcdqは２つの出力を一括して示している。 The second three-phase / dq coordinate conversion means 29 connected to the transmission paths 25u, 25v, 25w and the phase detection means 20 for the first, second and third phase signals Icu, Icv, Icw are the first, second, The third phase signals Icu, Icv, and Icw are rotationally transformed at the reference phase angle ωt, and a two-phase signal composed of a d-axis component current Icd and a q-axis component current Icq indicated by the dq coordinate axis is output. The input, coordinate transformation matrix T3, and output of the second three-phase / dq coordinate transformation means 29 can be expressed by the following equations (10), (11), and (12). In these equations, Icuvw collectively indicates the input first, second and third phase signals Icu, Icv and Icw, and Icdq indicates two outputs collectively.

出力電流指令値作成手段１３は、第１及び第２の加算手段３０、３１から成る。第１の加算手段３０は連系電流指令値発生手段１２から供給される第１の連系電流指令値Iｓｄ^*と第２の３相／ｄｑ座標変換手段２９から供給されるｄ軸成分電流Iｃｄとを加算して第１相出力電流指令値Iｏｄ^*を作成する。第２の加算手段３１は、連系電流指令値発生手段１２から供給される第２の連系電流指令値Iｓｑ^*と第２の３相／ｄｑ座標変換手段２９から供給されるｑ軸成分電流Ｉｃｑを加算して第３相出力電流指令値Iｏｑ^*を作成する。なお、Iｓｄ^*、Iｓｑ^*、Iｃｄ、Iｃｑ、Iｏｄ^*、Iｏｑ^*は瞬時値を示している。 The output current command value creating means 13 includes first and second adding means 30 and 31. The first addition means 30 includes a first interconnection current command value Isd ^* supplied from the interconnection current command value generation means 12 and a d-axis component current Icd supplied from the second three-phase / dq coordinate conversion means 29. Are added to create the first phase output current command value Iod ^* . The second addition means 31 includes a second interconnection current command value Isq ^* supplied from the interconnection current command value generation means 12 and a q-axis component current supplied from the second three-phase / dq coordinate conversion means 29. The third phase output current command value Ioq ^* is created by adding Icq. Note that Isd ^* , Isq ^* , Icd, Icq, Iod ^* , and Ioq ^* indicate instantaneous values.

帰還制御信号形成手段１４は、第１及び第２の偏差信号作成手段３２、３３と第１及び第２の増幅回路３４、３５と変換手段４１とから成る。変換手段４１はライン８ｕ，８ｗによって図１の第１及び第３相電流検出器ＣＴｕ、ＣＴｗに接続され、且つ位相検出手段２０にも接続され、３相で示される電流を形成し、この３相で示される電流をｄｑ座標軸で示すｄ軸成分電流Ｉｏｄとｑ軸成分電流Ｉｏｑとから成る２相の信号に変換し、この信号をライン４２，４３で第１及び第２の偏差信号作成手段３２、３３に送る。
更に詳細には、変換手段４１は図４に示すように、第２相信号形成手段４４と第３の３相／ｄｑ座標変換手段４５とを有する。第２相信号形成手段４４はライン８ｕ，８ｗに接続され、ライン８ｕの第１相出力電流Ｉｏｕとライン８ｗの第３相出力電流Ｉｏｗとの合成信号（加算信号）を位相反転した信号に相当する第２相出力電流Ｉｏｖをライン８ｖに送出する。従って、図４の第２相信号形成手段４４は図３の第２相信号形成手段２７と同様な機能を有する。なお、第２相信号形成手段４４を設ける代わりに、図１の中間端子１ｃと第１及び第２のフィルタコンデンサＣｕ、Ｃｗの相互接続点との間の電流通路の第２相出力電流Ｉｏｖを検出する第２相電流検出器を設け、この第２相電流検出器の出力をライン８ｖによって図４の第３の３相／ｄｑ座標変換手段４５に送ることもできる。
ライン８ｕ、８ｖ、８ｗに接続された第３の３相／ｄｑ座標変換手段４５は、位相検出手段２０から出力される基準位相角ωｔにて回転座標変換するものであって、図３の第２の３相／ｄｑ座標変換手段２９と同様な機能を有し、３相で示めされる第１相、第２相及び第３相出力電流Ｉｏｕ、Ｉｏｖ、Ｉｏｗを周知のｄｑ座標軸で示すｄ軸成分電流Ｉｏｄとｑ軸成分電流Ｉｏｑとから成る２相信号に変換してライン４２，４３に送出する。
第１の偏差信号作成手段３２は出力電流指令値作成手段１３の第１の加算手段３０と変換手段４１の出力ライン４２とに接続され、第１相出力電流指令値Ｉoｄ^*とｄ軸成分電流Ｉｏｄとの差を示す信号を出力する。第２の偏差信号作成手段３３は出力電流指令値作成手段１３の第２の加算手段１１と変換手段４１の出力ライン４３とに接続され、第３相出力電流指令値Ｉｏｑ^*とｑ軸成分電流Ｉｏｑとの差を示す信号を出力する。第１及び第２の偏差信号作成手段３２、３３にそれぞれ接続された増幅回路３４、３５はそれぞれの偏差信号を増幅、又は増幅及び調整して第１相及び第３相の帰還制御信号Ｉｆｕ、Ｉｆｗを出力する。 The feedback control signal forming unit 14 includes first and second deviation signal generating units 32 and 33, first and second amplifier circuits 34 and 35, and a converting unit 41. The conversion means 41 is connected to the first and third phase current detectors CTu and CTw of FIG. 1 by lines 8u and 8w, and is also connected to the phase detection means 20 to form a current indicated by three phases. The current indicated by the phase is converted into a two-phase signal composed of the d-axis component current Iod and the q-axis component current Ioq indicated by the dq coordinate axis, and this signal is generated by the first and second deviation signal generating means on the lines 42 and 43. 32 and 33.
More specifically, as shown in FIG. 4, the converting means 41 includes a second phase signal forming means 44 and a third three-phase / dq coordinate converting means 45. The second phase signal forming means 44 is connected to the lines 8u and 8w and corresponds to a signal obtained by inverting the phase of the combined signal (addition signal) of the first phase output current Iou of the line 8u and the third phase output current Iow of the line 8w. The second phase output current Iov is sent to the line 8v. Therefore, the second phase signal forming means 44 in FIG. 4 has the same function as the second phase signal forming means 27 in FIG. Instead of providing the second phase signal forming means 44, the second phase output current Iov of the current path between the intermediate terminal 1c of FIG. 1 and the connection point of the first and second filter capacitors Cu and Cw is changed. It is also possible to provide a second phase current detector for detection and send the output of the second phase current detector to the third three-phase / dq coordinate conversion means 45 in FIG.
The third three-phase / dq coordinate conversion means 45 connected to the lines 8u, 8v, 8w performs rotational coordinate conversion at the reference phase angle ωt output from the phase detection means 20, and The three-phase / dq coordinate conversion means 29 has the same function as that of the second three-phase / dq coordinate conversion means 29, and the first phase, the second phase, and the third phase output currents Iou, Iov, Iow indicated by the three phases are indicated by known dq coordinate axes The signal is converted into a two-phase signal composed of a d-axis component current Iod and a q-axis component current Ioq and sent to lines 42 and 43.
The first deviation signal creation means 32 is connected to the first addition means 30 of the output current command value creation means 13 and the output line 42 of the conversion means 41, and the first phase output current command value Iod ^* and the d-axis component current. A signal indicating the difference from Iod is output. The second deviation signal creating means 33 is connected to the second adding means 11 of the output current command value creating means 13 and the output line 43 of the converting means 41, and the third phase output current command value Ioq ^* and the q-axis component current. A signal indicating a difference from Ioq is output. Amplifying circuits 34 and 35 connected to the first and second deviation signal generating means 32 and 33 respectively amplify or amplify and adjust the deviation signals to provide first-phase and third-phase feedback control signals Ifu, Ifw is output.

スイッチ制御パルス形成手段１５は鋸波発生器３６と、第１及び第２の比較器３７、３８と、駆動回路３９とから成る周知のＰＷＭパルス形成回路である。 The switch control pulse forming means 15 is a known PWM pulse forming circuit comprising a sawtooth wave generator 36, first and second comparators 37 and 38, and a drive circuit 39.

鋸波発生器３６は第１、第２及び第３相交流端子２ｕ、２ｖ、２ｗの交流電圧の周波数（例えば５０Ｈｚ）よりも十分に高い周波数（例えば１０〜１００ｋＨｚ）で鋸波電圧Ｖｔを発生する。なお、鋸波発生器３６の代りに三角波等の別の比較波（キャリア波）を発生する手段を設けることもできる。 The sawtooth generator 36 generates a sawtooth voltage Vt at a frequency (for example, 10 to 100 kHz) sufficiently higher than the frequency (for example, 50 Hz) of the AC voltage of the first, second, and third phase AC terminals 2u, 2v, and 2w. To do. Instead of the sawtooth wave generator 36, means for generating another comparison wave (carrier wave) such as a triangular wave can be provided.

第１の比較器３７は帰還制御信号形成手段１４の第１の増幅回路３４と鋸波発生器３６とに接続され、第１相帰還制御信号Ｉｆuと鋸波電圧Ｖｔとを図５（Ａ）に示すように比較して図５（Ｂ）に示す第１のＰＷＭパルスＶｐ１を出力する。第２の比較器３８は帰還制御信号形成手段１４の第２の増幅回路３５と鋸波発生器３６とに接続され、第３相帰還制御信号Ｉｆｗと鋸波電圧Ｖｔとを図５（Ａ）に示すように比較して図５（Ｃ）に示す第２のＰＷＭパルスＶｐ２を出力する。 The first comparator 37 is connected to the first amplifier circuit 34 of the feedback control signal forming means 14 and the sawtooth generator 36, and the first phase feedback control signal Ifu and the sawtooth voltage Vt are shown in FIG. In comparison, the first PWM pulse Vp1 shown in FIG. 5B is output. The second comparator 38 is connected to the second amplifier circuit 35 and the sawtooth generator 36 of the feedback control signal forming means 14, and the third phase feedback control signal Ifw and the sawtooth voltage Vt are shown in FIG. In comparison, the second PWM pulse Vp2 shown in FIG. 5C is output.

第１及び第２の比較器３７、３８に接続された駆動回路３９は、第１のＰＷＭパルスＶｐ１を増幅して第１の制御パルスＧ１を形成し、これを図１の第１のスイッチＳ１に送り、また、第１のＰＷＭパルスＶｐ１を反転増幅して第２の制御パルスＧ２を形成し、これを第２のスイッチＳ２に送り、また、第２のＰＷＭパルスＶｐ２を増幅して第３の制御パルスＧ３を形成し、これを第３のスイッチＳ３に送り、また、第２のＰＷＭパルスＶｐ２を反転増幅して第４の制御パルスＧ４を形成し、これを第４のスイッチＳ４に送る。 The drive circuit 39 connected to the first and second comparators 37 and 38 amplifies the first PWM pulse Vp1 to form a first control pulse G1, which is represented by the first switch S1 in FIG. And the first PWM pulse Vp1 is inverted and amplified to form the second control pulse G2, which is sent to the second switch S2, and the second PWM pulse Vp2 is amplified and the third PWM pulse Vp2 is amplified. Control pulse G3 is formed and sent to the third switch S3, and the second PWM pulse Vp2 is inverted and amplified to form the fourth control pulse G4, which is sent to the fourth switch S4. .

次に、本実施例の３相Ｖ結線インバータの動作を説明する。連系電流指令値発生手段１２は、３相交流電力系統３の電圧Ｖｓと第１、第２及び第３相連系電流Ｉｓｕ、Ｉｓｖ、Ｉｓｗとによる力率が１又は１に近い値（０．８５以上であることが望ましい。）になることが可能な値を有する第１及び第２の連系電流指令値Ｉｓｄ^*、Ｉｓｑ^*を発生する。第１及び第２の連系電流指令値Ｉｓｄ^*、Ｉｓｑ^*は、コンデンサ電流値作成手段１１の第２の３相／ｄｑ座標変換手段２９から得られるｄ軸成分及びｑ軸成分電流Ｉｃｄ、Ｉｃｑと同一の周知のｄｑ座標軸（直交座標軸）のｄ軸成分とｑ軸成分であるので、両者の合成によって第１及び第３相出力電流指令値Ｉｏｄ^*、Ｉｏｑ^*を容易に決定することができる。第１相及び第３相リアクトルＬｕ、Ｌｗに流れる第１相及び第３相出力電流Ｉｏｕ、Ｉｏｗは、所望力率（好ましくは１）の状態に第１、第２及び第３相連系電流Ｉｓｕ、Ｉｓｖ、Ｉｓｗが流れるように帰還制御される。これにより、インバータの第１及び第３相出力電流Ｉｏｕ、Ｉｏｗの制御によって力率が１となるように第１、第２及び第３相連系電流Ｉｓｕ、Ｉｓｖ、Ｉｓｗを流すことができる。なお、３相Ｖ結線インバータの主回路の動作は周知であるので、その説明を省略する。 Next, the operation of the three-phase V-connection inverter of this embodiment will be described. The interconnection current command value generation means 12 has a power factor of 1 or a value close to 1 (0...) Based on the voltage Vs of the three-phase AC power system 3 and the first, second, and third phase interconnection currents Isu, Isv, Isw. The first and second interconnection current command values Isd ^* and Isq ^* having values that can be greater than or equal to 85. ⁾ are generated. The first and second interconnection current command values Isd ^* and Isq ^* are the d-axis component and q-axis component currents Icd and Icq obtained from the second three-phase / dq coordinate conversion unit 29 of the capacitor current value creation unit 11. Are the same d-axis component and q-axis component of the same known dq coordinate axis (orthogonal coordinate axis), so that the first and third phase output current command values Iod ^* and Ioq ^* can be easily determined by combining them. . The first-phase and third-phase output currents Iou, Iow flowing in the first-phase and third-phase reactors Lu, Lw are in the state of the desired power factor (preferably 1), the first, second, and third-phase interconnection currents Isu. , Isv, Isw are feedback controlled. As a result, the first, second, and third phase interconnection currents Isu, Isv, Isw can be caused to flow so that the power factor becomes 1 by controlling the first and third phase output currents Iou, Iow of the inverter. Since the operation of the main circuit of the three-phase V-connection inverter is well known, the description thereof is omitted.

本実施例は次の効果を有する。
（１）第１相及び第３相連系電流Ｉｓｕ、Ｉｓｗを検出するための２つの電流検出器を設けない回路で力率を１又はほぼ１に制御することができる。従って、３相Ｖ結線インバータの小型化及び低コスト化を図ることができる。
（２）３相Ｖ結線インバータであるので、３相フルブリッジ型インバータに比べてスイッチの数を２個減らすことができ、小型化及び低コスト化が達成される。
（３）コンデンサ電流値作成手段１１によってｄ軸成分電流Ｉｃｄとｑ軸成分電流Ｉｃｑとを形成し、連系電流指令値発生手段１２からｄ軸及びｑ軸成分としての第１及び第２の連系電流指令値Ｉｓｄ^*、Ｉｓｑ^*を発生させるので、３相Ｖ結線インバータの制御を容易に達成できる。 This embodiment has the following effects.
(1) The power factor can be controlled to 1 or almost 1 with a circuit that does not include two current detectors for detecting the first-phase and third-phase interconnection currents Isu and Isw. Therefore, it is possible to reduce the size and cost of the three-phase V-connection inverter.
(2) Since it is a three-phase V-connection inverter, the number of switches can be reduced by two compared to a three-phase full-bridge type inverter, and miniaturization and cost reduction are achieved.
(3) The d-axis component current Icd and the q-axis component current Icq are formed by the capacitor current value creating means 11, and the first and second linkages as the d-axis and q-axis components from the interconnection current command value generating means 12 are formed. Since system current command values Isd ^* and Isq ^* are generated, control of the three-phase V-connection inverter can be easily achieved.

実施例２の３相Ｖ結線インバータは実施例１のコンデンサ電流作成手段１１を図６に示すコンデンサ電流値作成手段１１ａに変形し、この他は実施例１と同一に形成してものである。従って、実施例２の説明においても実施例１を示す図１〜図４を参照し、且つ共通する部分の説明を省略する。 The three-phase V-connection inverter of the second embodiment is the same as the first embodiment except that the capacitor current creating means 11 of the first embodiment is transformed into a capacitor current value creating means 11a shown in FIG. Therefore, also in description of Example 2, FIGS. 1-4 which shows Example 1 is referred, and description of a common part is abbreviate | omitted.

図６の実施例２のコンデンサ電流値作成手段１１ａは、固定電流値発生手段４０と位相検出手段２０と第２相信号形成手段２７と３相／ｄｑ座標変換手段２９とを有する。 6 includes a fixed current value generating means 40, a phase detecting means 20, a second phase signal forming means 27, and a three-phase / dq coordinate converting means 29.

固定電流値発生手段４０は、図３の実施例１のコンデンサ電流値作成手段１１における無効電流検出部２５及びこれよりも前の部分と実質的に同一の機能を有し、図３において第１及び第３相信号Ｉｃｕ、Ｉｃｗと実質的に同一の信号を固定的に発生する。即ち、固定電流値発生手段４０から発生する第１相及び第３相信号Ｉｃｕ、Ｉｃｗは、第１、第２及び第３相交流端子２ｕ、２ｖ、２ｗの線間電圧の実効値Ｖ、周波数ω、第１及び第２のフィルタコンデンサＣｕ、Ｃｗの容量Ｃを固定値として次の（１３）（１４）（１５）式に従う計算で決定される。 The fixed current value generation means 40 has substantially the same function as the reactive current detection unit 25 and the portion before this in the capacitor current value creation means 11 of the first embodiment of FIG. In addition, a signal substantially the same as the third phase signals Icu and Icw is fixedly generated. That is, the first-phase and third-phase signals Icu and Icw generated from the fixed current value generating means 40 are the effective value V and the frequency of the line voltage at the first, second and third-phase AC terminals 2u, 2v and 2w. ω and the capacitance C of the first and second filter capacitors Cu and Cw are fixed values, and are determined by calculations according to the following equations (13), (14), and (15).

図６の位相検出手段２０、第２相信号形成手段２７、３相／ｄｑ座標変換手段２９は図３で同一記号で示すものと同一であるので、その説明を省略する。 The phase detection means 20, the second phase signal formation means 27, and the three-phase / dq coordinate conversion means 29 in FIG. 6 are the same as those indicated by the same symbols in FIG.

この実施例２において、３相交流電力系統３の電圧が安定している場合には、これを固定して第１及び第２のフィルタコンデンサＣｕ、Ｃｗの無効電流を示す第１相及び第３相信号Ｉｃｕ、Ｉｃｗを決定しても、これ等の値は実測値を使用する場合とほぼ同一の値となる。 In the second embodiment, when the voltage of the three-phase AC power system 3 is stable, the first phase and the third phase indicating the reactive currents of the first and second filter capacitors Cu and Cw are fixed. Even if the phase signals Icu and Icw are determined, these values are almost the same as when the actual measurement values are used.

実施例２は実施例１と同一効果を有する他に、固定電流値発生手段４０で第１相及び第３相信号Ｉｃｕ、Ｉｃｗを発生させるので、コンデンサ電流値作成手段１１ａにおける演算回数を実施例１に比べて削減でき、高速な演算処理が可能になるという効果を有する。 The second embodiment has the same effect as the first embodiment. In addition, since the first and third phase signals Icu and Icw are generated by the fixed current value generating means 40, the number of operations in the capacitor current value creating means 11a is determined according to the embodiment. Compared to 1, it has the effect of being able to reduce and enabling high-speed arithmetic processing.

本発明は上述の実施例に限定されるものでなく、例えば次の変形が可能なものである。
（１）図１の第１相及び第３相電流検出器ＣＴｕ、ＣＴｗを第１及び第２のフィルタコンデンサＣｕ、Ｃｗと第１及び第３相交流端子２ｕ、２ｗとの間の電流通路に移動し、第１相及び第３相連系電流Ｉｓｕ，Ｉｓｗを検出するように変形することができる。この変形例の場合には、図２のコンデンサ電流値作成手段１１又は図６のコンデンサ電流値作成手段１１ａと同一のものを設け、また、図２の連系電流指令値発生手段１２の位置に出力電流指令値作成手段を配置し、図２の出力電流指令値作成手段１３の位置に連系電流指令値発生手段を配置し、この連系電流指令値発生手段の出力段に図２と同様に帰還制御信号形成手段１４とスイッチ制御パルス形成手段１５とを配置する。
この変形例の場合の出力電流指令値作成手段は、図１のインバータの第１、第２及び第３相出力電流Iou，Iov，Iowの目標値を２相軸に変換したものに相当する第１及び第２の出力電流指令値Ioｄ^*、Ｉｏq^*を発生するように構成する。また、連系電流指令値発生手段は、出力電流指令値作成手段から得られた第１の出力電流指令値Ioｄ^*とコンデンサ電流値作成手段１１又は１１ａから得られた第１の信号Ｉcdとに基づいて第１相連系電流指令値Ｉｓd^*を作成し、且つ第２の出力電流指令値Ｉｏq^*とコンデンサ電流値作成手段１１又は１１ａから得られた第２の信号Ｉcqとに基づいて第２相連系電流指令値Ｉｓq^*を作成する。また、この変形例の場合の帰還制御信号形成手段には、第１相及び第３相電流検出器ＣＴu 、ＣＴw から得られた第１相及び第３相連系電流Ｉｓu、Ｉｓwの検出値から第２相連系電流Ｉｓｖを形成する手段を設け、更に第１相、第２及び第３相連系電流Ｉｓu、Ｉｓｖ，Ｉｓwを回転座標変換してｄｑ座標軸のｄ軸成分電流Ｉｓｄ及びｑ軸成分電流Ｉｓｄを得る３相／ｄｑ座標変換手段を設ける。図３に示す第１及び第２の偏差信号作成手段３２，３３は連系電流指令値作成手段から得られた第１相及び第３相連系電流指令値Ｉｓd^*、Ｉｓq^*と３相／ｄｑ座標変換手段から得られたｄ軸成分電流Ｉｓｄ及びｑ軸成分電流Ｉｓｄとの偏差を求めて第１相及び第３相帰還制御信号Ｉfu、Ｉfwを形成する。なお、変形例の場合においても、第２連系電流Ｉｓｖを演算で求める代わりに、第２連系電流Ｉｓｖを検出する第２相電流検出器を設けることができる。
（２）同一容量の第１及び第２の電圧分割用コンデンサＣａ、Ｃｂの代りに同一電圧の第１及び第２の蓄電池を接続することができる。
（３）連系電流Ｉｓｕ、Ｉｓｖ、Ｉｓｗに高調波成分又は高周波成分が含まれても差し支えない場合には、これに対応するように連系電流指令値発生手段１２を変形することができる。 The present invention is not limited to the above-described embodiments, and for example, the following modifications are possible.
(1) The first-phase and third-phase current detectors CTu and CTw in FIG. 1 are connected to the current path between the first and second filter capacitors Cu and Cw and the first and third-phase AC terminals 2u and 2w. The first phase and the third phase interconnection currents Isu and Isw can be detected by moving. In the case of this modification, the same capacitor current value creating means 11 of FIG. 2 or the capacitor current value creating means 11a of FIG. 6 is provided, and the position of the interconnecting current command value generating means 12 of FIG. An output current command value creating means is arranged, and a linkage current command value generating means is arranged at the position of the output current command value creating means 13 in FIG. The feedback control signal forming means 14 and the switch control pulse forming means 15 are arranged in the above.
The output current command value creating means in the case of this modification corresponds to the first, second and third phase output currents Iou, Iov, Iow of the inverter of FIG. The first and second output current command values Iod ^* and Ioq ^* are generated. Further, the interconnection current command value generating means generates the first output current command value Iod ^* obtained from the output current command value creating means and the first signal Icd obtained from the capacitor current value creating means 11 or 11a. based create a first phase interconnection current command value Isd ^*, and a second output current command value IOQ ^* a second's eye based on the second signal Icq obtained from the capacitor current value preparation unit 11 or 11a A system current command value Isq ^* is created. Further, the feedback control signal forming means in the case of this modification includes the first and third phase currents obtained from the first and third phase current detectors CTu and CTw based on the detected values of the first and third phase interconnection currents Isu and Isw. Means for forming the two-phase interconnection current Isv is provided, and the first-phase, second- and third-phase interconnection currents Isu, Isv, Isw are rotationally transformed to convert the d-axis component current Isd and the q-axis component current Isd of the dq coordinate axis Three-phase / dq coordinate conversion means for obtaining The first and second deviation signal generating means 32 and 33 shown in FIG. 3 are the first-phase and third-phase connected current command values Isd ^* and Isq ^* obtained from the connected current command value generating means and the three-phase / dq. Deviations between the d-axis component current Isd and the q-axis component current Isd obtained from the coordinate conversion means are obtained to form the first phase and third phase feedback control signals Ifu and Ifw. In the case of the modification, a second phase current detector for detecting the second interconnection current Isv can be provided instead of obtaining the second interconnection current Isv by calculation.
(2) The first and second storage batteries having the same voltage can be connected instead of the first and second voltage dividing capacitors Ca and Cb having the same capacity.
(3) If the harmonic currents or the high-frequency components may be included in the interconnection currents Isu, Isv, Isw, the linkage current command value generation means 12 can be modified to correspond to this.

本発明の実施例１に従う３相Ｖ結線インバータを示す回路図である。It is a circuit diagram which shows the three-phase V connection inverter according to Example 1 of this invention. 図１の制御部を詳しく示すブロック図である。It is a block diagram which shows the control part of FIG. 1 in detail. 図２を制御部を更に詳しく示すブロック図である。FIG. 2 is a block diagram showing the control unit in more detail in FIG. 図３の帰還制御信号形成手段に含まれている変換手段を詳しく示すブロック図である。It is a block diagram which shows in detail the conversion means contained in the feedback control signal formation means of FIG. 図３の各部の状態を示す波形図である。It is a wave form diagram which shows the state of each part of FIG. 実施例２のコンデンサ電流値作成手段を示すブロック図である。It is a block diagram which shows the capacitor electric current value preparation means of Example 2.

Explanation of symbols

１直流電源
１ａ、１ｂ第１及び第２の直流端子
１ｃ中間端子
２ｕ、２ｖ、２ｗ第１、第２及び第３相交流端子
３３相交流電力系統
４制御回路
５電圧検出手段
６制御部
１１コンデンサ電流値作成手段
１２連系電流指令値発生手段
１３出力電流指令値作成手段
Ｃａ、Ｃｂ第１及び第２の電圧分割用コンデンサ
Ｓ１〜Ｓ４スイッチ
Ｄ１〜Ｄ４ダイオード
Ｌｕ、Ｌｗ第１相及び第３相リアクトル
Ｃｕ、Ｃｗ第１及び第２のフィルタコンデンサ
ＣＴｕ、ＣＴｗ第１相及び第３相電流検出器 DESCRIPTION OF SYMBOLS 1 DC power supply 1a, 1b 1st and 2nd DC terminal 1c Intermediate | middle terminal 2u, 2v, 2w 1st, 2nd and 3rd phase alternating current terminal 3 3 phase alternating current power system 4 Control circuit 5 Voltage detection means 6 Control part 11 Capacitor current value creation means 12 Interconnection current command value generation means 13 Output current command value creation means Ca, Cb First and second voltage dividing capacitors S1 to S4 Switches D1 to D4 Diodes Lu and Lw First phase and third Phase reactor Cu, Cw 1st and 2nd filter capacitor CTu, CTw 1st phase and 3rd phase current detector

Claims

First and second DC terminals (1a, 1b) for supplying a DC voltage;
An intermediate terminal (1c) having an intermediate potential between the first and second DC terminals (1a, 1b);
A first phase AC terminal (2u) for outputting a first phase voltage of a three-phase AC voltage;
A second phase AC voltage (2v) that outputs a second phase voltage of the three-phase AC voltage, and is electrically connected to the intermediate terminal (1c);
A third phase AC terminal (2w) for outputting a third phase voltage of the three-phase AC voltage;
A series circuit of first and second switches (S1, S2) connected between the first and second DC terminals (1a, 1b);
A series circuit of third and fourth switches (S3, S4) connected between the first and second DC terminals (1a, 1b);
A first phase reactor (Lu) connected between an interconnection point (P1) of the first and second switches (S1, S2) and the first phase AC terminal (2u);
A third phase reactor (Lw) connected between the interconnection point (P2) of the third and fourth switches (S3, S4) and the third phase AC terminal (2w);
A first filter capacitor (Cu) connected between the first phase AC terminal (2u) and the second phase AC terminal (2v);
A second filter capacitor (Cw) connected between the second phase AC terminal (2v) and the third phase AC terminal (2w);
A first phase current detector (CTu) for detecting a first phase current (Iou or Isu) flowing through the first phase reactor (Lu) or the first phase AC terminal (2u);
A third phase current detector (CTw) for detecting a third phase current (Iow or Isw) flowing through the third phase reactor (Lw) or the third phase AC terminal (2w);
Voltage detecting means (5) for detecting voltages of the first and second filter capacitors (Cu, Cw), respectively;
Based on the output of the first and third phase current detectors (CTu, CTw) and the output of the voltage detection means (5), the first, second and third phase AC terminals (2u, 2v, 2w). A switch control pulse for controlling on / off of the first to fourth switches is formed so as to set the power factor at a desired value, and supplied to the control terminals of the first, second, third and fourth switches. A three-phase V-connection inverter, comprising:

The controller is
The value of the current (Icu, Icv, Icw) indicated by the three phases of the first and second filter capacitors (Cu, Cw) is calculated by using the output of the voltage detection means (5) or on the actual side Capacitor current value creation means for creating first and second signals (Icd, Icq) corresponding to those obtained by converting the values of the currents (Icu, Icv, Icw) indicated by the three phases into the two-phase axes. 11 or 11a)
First and second interconnected current command values (corresponding to a target value of a three-phase current flowing through the first, second and third AC terminals (2u, 2v, 2w) converted to a two-phase axis ( Interconnected current command value generating means (12) for generating Isd ^* , Isq ^* ),
The first interconnect current command value (Isd ^* ) obtained from the interconnect current command value generating means (12) and the first signal (11 or 11a) obtained from the capacitor current value creating means (11 or 11a). The first phase output current command value (Iod ^* ) is created based on Icd) and the third phase based on the second interconnection current command value (Isq ^* ) and the second signal (Icq). Output current command value creation means (13) for creating a phase output current command value (Ioq ^* );
The first and third phase output current command values (Iod ^* , Ioq ^* ) and the first and third phase current detectors (CTu, CTw) obtained from the output current command value creating means (13). Feedback control signal forming means for forming first and third phase feedback control signals (Ifu, Ifw) based on the detected values of the first phase and third phase output currents (Iou, Iow) obtained from 14)
The first, second, third and fourth switches (S1, S2) based on the first and third phase feedback control signals (Ifu, Ifw) obtained from the feedback control signal forming means (14). , S3, S4), and switch control pulse forming means (15) for forming switch control pulses (G1, G2, G3, G4) for on / off control. Phase V connection inverter.

The voltage detection means (5) includes a line voltage (Vuv) between the first and second phase AC terminals (2u, 2v) as a voltage of the first and second filter capacitors (Cu, Cw), and A line voltage (Vvw) between the second and third phase AC terminals (2v, 2w) is detected, and a line voltage (Vwu) between the third and first phase AC terminals (2w, 2u) is detected. Means for detecting
The capacitor current value creating means (11)
Phase detection means (20) connected to the voltage detection means (5) to obtain a signal indicative of a reference phase angle (ωt);
A lead phase angle signal forming means (21) for forming a signal indicating a lead phase angle (ωt + π / 2) advanced by π / 2 from the reference phase angle (ωt);
The three-phase line voltages (Vuv, Vvw, Vwu) obtained from the voltage detection means (5) are rotated by the advance phase angle (ωt + π / 2) obtained from the advance phase angle signal forming means (21). A first three-phase / dq coordinate conversion means (22) for outputting a d-axis component voltage (Vd) and a q-axis component voltage (Vq) indicated by the dq coordinate axis after coordinate conversion;
The d-axis component voltage (Vd) and the q-axis component voltage (Vq) obtained from the first three-phase / dq coordinate conversion means (22) are converted into the first and second filter capacitors (Cu, Cw). Two-phase axis virtual reactive current signal forming means (23) for forming a d-axis component virtual reactive current (Iad) and a q-axis component virtual reactive current (Iaq) indicating values divided by respective impedances (1 / ωC) When,
The d-axis component virtual reactive current (Iad) and the q-axis component virtual reactive current (Iaq) obtained from the two-phase axis virtual reactive current signal forming means (23) are rotated at the reference phase angle (ωt). The first, second, and third three-phase axis virtual reactive currents (Iau, Iav, Iaw) in the case where it is assumed that a filter capacitor is connected between the first and third phase AC terminals by inverse coordinate transformation. Dq / 3-phase coordinate conversion means (24) for outputting a signal indicating
A first phase indicating a reactive current flowing through the first filter capacitor (Cu) with a signal indicating the first three-phase axis virtual reactive current (Iau) obtained from the dq / 3-phase coordinate conversion means (24). Means (25u) for transmitting as a signal (Icu);
Third phase signal forming means for outputting a third phase signal (Icw) indicating a reactive current flowing through the second filter capacitor (Cw) by inverting the phase of the second three-phase virtual reactive current (Iav). 26)
Means (27) for forming a second phase signal (Icv) corresponding to a phase inverted signal of a composite signal of the first phase signal (Icu) and the third phase signal (Icw);
The first, second and third phase signals (Icu, Icv, Icw) are subjected to rotational coordinate conversion at the reference phase angle (ωt), and d-axis component current (Icd) and q-axis component current ( 3. A three-phase V-connection inverter according to claim 2, further comprising second three-phase / dq coordinate conversion means (29) for outputting Icq).

The capacitor current value creating means (11a)
Phase detection means (20) connected to the voltage detection means (5) to obtain a signal indicative of a reference phase angle (ωt);
The voltage between the first, second and third phase AC terminals (2u, 2v, 2w), the frequency, and the capacitance of the first and second filter capacitors (Cu, Cw) are fixed values. Filter capacitor predicted current generating means (40) for generating a signal indicating the first and second filter capacitor predicted currents (Icu, Icw) obtained by calculation or actual measurement of the current flowing through the second filter capacitors (Cu, Cw), respectively. )When,
Means (25u) for transmitting a signal indicating the first filter capacitor predicted current (Icu) as a first phase signal;
Means (25w) for transmitting a signal indicating said second filter capacitor predicted current (Icw) as a third phase signal;
Means (27) for forming a second phase signal (Icv) corresponding to a phase inverted signal of a composite signal of the first phase signal (Icu) and the third phase signal (Icw);
The d-axis indicated by the dq coordinate axis by rotationally converting the first, second and third phase signals (Icu, Icv, Icw) at the reference phase angle (ωt) obtained from the phase detecting means (20). 3. A three-phase V-connected inverter according to claim 2, comprising three-phase / dq coordinate conversion means (29) for outputting a component current (Icd) and a q-axis component current (Icq).