JP2006253952A - Clamp circuit and synchronous separator circuit equipped with the clamp circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clamp circuit which has a small circuit scale and can suppress an occurrence of a V sag. <P>SOLUTION: The clamp circuit comprises a synchronous separation circuit (14) which separates an image signal synchronously, and has a charging circuit (16) and two discharging circuits, wherein one is a discharging circuit (18) which discharges in response to an output result from the synchronous separation circuit (14) and the other is a discharging circuit (17) which discharge a fixed amount at all times. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a clamp circuit that clamps a video signal, and more particularly, to a clamp circuit that is suitable for accurately performing synchronization separation even on a video signal including a V sag.

  In order to detect the vertical and horizontal sync signals included in the analog video signal, it is necessary to align the potential at the tip (bottom) of the reference sync signal to the clamp level. A clamp circuit is used as a circuit for aligning the potential at the tip of the input video signal with the clamp level.

  FIG. 2 is an example of a clamp circuit, and an outline of the operation will be described. A video signal is applied to the input terminal 1 of FIG. The applied video signal is a composite video signal including a vertical synchronization signal, a horizontal synchronization signal, an equivalent pulse, a luminance signal, and the like.

  A video signal from the input terminal 1 in FIG. 2 is input to the clamp circuit 3. In the clamp circuit 3, the potential at the tip of the reference synchronization signal is set to the clamp level. When the potential at the tip of the reference synchronization signal is lower than the clamp level, the clamp circuit 3 charges the capacitor 2 as a clamp capacitor from the variable current source 4 and charges the tip of the reference synchronization signal. Increase the potential.

  Contrary to the above, the clamp circuit 3 discharges from the fixed current source 5 when the potential at the tip of the reference synchronization signal is higher than the clamp level, and the tip of the reference synchronization signal. Is lowered.

  A synchronization signal in which the potential at the tip of the reference synchronization signal is set to the clamp level by the clamp circuit 3 can be taken out from the output terminal 9.

  At the same time, the synchronization signal in which the potential at the tip of the reference synchronization signal is set to the clamp level is applied to the synchronization separation circuit 6. The synchronization separation circuit 6 compares the output signal from the clamp circuit 3 with Vref (slice level).

  If the output signal from the clamp circuit 3 is higher than the slice level, it is determined as “H”, and if it is lower, it is determined as “L”. The synchronization separated signal that has been subjected to synchronization separation is output from the output terminal 8.

In the clamp circuit 3, the potential at the tip of the input video signal is made equal to the clamp level, so that the synchronization separation circuit 6 can easily perform synchronization separation accurately.
JP-A-8-204994 JP-A-9-98042 JP-A-2004-200901

  The capacitor of FIG. 2 can be considered as a DC blocking capacitor. The DC blocking capacitor transmits only the AC component. However, when the capacitance of the capacitor used in the coupling portion is small, if the DC signal varies in the input signal, this variation cannot be absorbed and no DC component is transmitted. In the field of video, it is known by the name of “V sag” in which the potential at the tip of the video signal fluctuates during the vertical synchronization period.

  For example, when a video signal as shown in FIG. 3A is applied, the video signal includes a vertical synchronization signal, a horizontal synchronization signal, an equivalent pulse, a luminance signal, and the like.

  In the composite video signal shown in FIG. 3A, the equivalent pulse period may be switched to the vertical synchronization period. When changing from the equivalent pulse period to the vertical synchronization period, the average potential may fluctuate, leading to a situation of V sag.

  When the V sag is generated, the composite video signal shown in FIG. 3A changes as shown in FIG. In FIG. 3B, when switching from the equivalent pulse period to the vertical synchronization period, the average potential fluctuates and the potential at the tip of the video signal rises.

  When the potential at the tip of the video signal rises, it becomes impossible to slice accurately in the synchronization separation circuit, resulting in a malfunction.

  In FIG. 3B, the potential of the leading end of the composite video signal rises and becomes higher than the slice level due to the occurrence of the V sag, which causes a problem that synchronization separation cannot be performed accurately in the vertical synchronization period.

  Conventionally, there has been a clamp circuit to suppress the occurrence of V sag. Typical clamp circuits include a diode clamp circuit and a keyed clamp circuit. The diode clamp circuit can suppress the occurrence of V sag by simply increasing the discharge current. However, since the diode clamp circuit always discharges current, the video signal is adversely affected. In addition, there are cases where synchronization separation cannot be performed accurately.

  Further, the keyed clamp circuit can discharge a large current only during the SYNC period by on / off control, and can control it accurately, and does not adversely affect the video signal. However, in order to accurately control the discharge period, a large-scale control circuit is required, and there is a problem that the circuit scale increases. For this reason, a clamp circuit that has a small circuit scale and can suppress the occurrence of V sag has been desired.

  A main invention according to the present invention is a clamp circuit that is used in a sync separation circuit that synchronously separates a vertical sync signal and a horizontal sync signal included in a video signal, and that aligns the tips of the vertical sync signal and the horizontal sync signal to a clamp level. A charging circuit that charges when the potentials at the tips of the vertical sync signal and horizontal sync signal are lower than the clamp level, and a potential at the tips of the vertical sync signal and horizontal sync signal relative to the clamp level. A discharge circuit that discharges when it is high, the discharge circuit having a first discharge part and a second discharge part, wherein the first discharge part has a discharge period and a non-discharge period The second discharge part is always discharged.

  Further, other features of the present invention will become apparent from the accompanying drawings and the description of the present specification.

  According to the present invention, even when a signal having a change in average potential and having a relatively large V sag is input as an input signal, synchronization and separation can be accurately performed.

  In addition, a large control circuit for on / off control of the clamp circuit is not required, an increase in circuit scale can be suppressed, and low power consumption can be realized.

  Details of the present invention will be specifically described with reference to the drawings. FIG. 1 is a block diagram showing a clamp circuit of the present invention. In FIG. 1, 10 is an input terminal, 11 is a capacitor, 12 and 13 are constant current sources, 14 is a comparator, 15 is an output terminal, 16 is a charging circuit, 17 and 18 are discharging circuits, 19 is a clamp output terminal, T1, T2, T3, T4, T5, T6, and T7 are transistors, R1, R2, R3, and R4 are resistors, and V1 is a power source.

  In FIG. 1, a video signal is applied from an input terminal 10, passes through a capacitor 11 which is a clamp capacitor, and reaches a point P in FIG. The potential at the point P in FIG. 1 is a clamp level that aligns the potentials at the tips of the synchronization signals. In this embodiment shown in FIG. 1, the clamp level potential is 1.5V.

  In the charging circuit 16 of FIG. 1, a power supply voltage (VCC) is supplied to the collector of the transistor T1, and a power supply of 2.2V from the power supply V1 is supplied to the base of the transistor T1.

  When the potential at the point P in FIG. 1 becomes 1.5V or less of the clamp level potential, the transistor of the transistor T1 is turned on, a collector current flows between the collector and the emitter of the transistor T1, and the collector current is charged in the capacitor 11. And the potential at point P in FIG. 1 is raised.

  On the contrary, when the potential at the point P in FIG. 1 becomes larger than the clamp level potential of 1.5 V, the transistor at T1 is turned off, and the potential at the point P in FIG. 1 is not further increased.

  The collector of the transistor T2 is connected to the power supply voltage (VCC), and the emitter of the transistor T2 is connected to the discharge circuits 17 and 18. That is, when a current flows between the collector and emitter of the transistor T2 by the discharge circuit 17 and the discharge circuit 18, the base current of the transistor T2 also flows and the potential at the point P drops.

  When the current amplification factor of the transistor T2 is β, the capacitor is discharged with a current 1 / β of the amount of current discharged by the discharge circuit 17 and the discharge circuit 18, and the potential at the point P in FIG.

  Further, the video signal that has passed the point P in FIG. 1 is applied to the clamp output terminal 19 from the base of the transistor T2. A signal with a constant potential can be obtained from the clamp output terminal 19. The clamped potential is applied to the input terminal (+) side of the synchronization separation circuit 14, and Vref used as a reference for comparison is connected to the input terminal (−) of the synchronization separation circuit 14. The comparison result is output from the output terminal Vout15.

  Here, the operation of the discharge circuit 17 of FIG. 1 will be described in detail. In the discharge circuit 17 of FIG. 1, the constant current source 12 is connected to VCC, and a constant current is always output from the constant current source 12, and is connected to the bases of the transistors T3 and T4. The transistor T3 and the transistor T4 are current mirror circuits, and the discharge circuit 17 always flows a current corresponding to the collector current of the transistor T3 and is discharged from the capacitor 11 with a current of 1 / β.

  The ratio of the emitter sizes of the transistors T3 and T4 is 1: 5, and the collector current of the transistor T3 is 1/5 of the collector current of the transistor T4.

  Further, in order to accurately set the collector current of the transistor T3 to one fifth of the collector current of the transistor T4, the resistance values of the resistors R1 and R2, which are resistors connected to the transistors T3 and T4, are 5 A one-to-one ratio.

  Assuming that constant current source 12 always flows 20 μA, the collector current of transistor T4 is 20 μA, and the collector current of transistor T3 is 1/5 of 20 μA, which is 4 μA. The discharge circuit 17 is a discharge circuit that always discharges 4 μA.

  Here, the operation of the discharge circuit 18 of FIG. 1 will be described in detail. In the discharge circuit 18 of FIG. 1, the entire discharge circuit 18 is turned on and off by the potential applied to the base of the transistor T7. When the point d in FIG. 1 which is the output from the synchronous separation circuit 14 is “H”, a high voltage is applied to the base of the transistor T7, the transistor T7 is turned on, and the collector current of the transistor T7 flows.

  At this time, the constant current from the constant current source 13 becomes the collector current of the transistor T7 having a low impedance, and no current flows through the base of the transistor T6 having a high impedance. Transistor T6 is turned off, and similarly transistor T5 is turned off. When the transistor T5 is also off, the collector current of the transistor T5 does not flow, and the discharge circuit 18 does not perform the discharge operation.

  On the contrary, when the point d in FIG. 1 is “L”, the transistor T7 is turned off, and the collector current of the transistor T6 flows from the power supply voltage (VCC) through the constant current source 13. When the transistor T6 is turned on, the transistor T5 is also turned on, the collector current of the transistor T5 flows, and the discharge circuit 18 performs a discharge operation. Therefore, when a low voltage is applied to the base of the transistor T7, the transistor T7 is turned off, and the discharge circuit 18 is configured to discharge.

  Assuming that 40 μA is constantly flowing through the constant current source 13, the collector current of the transistor T6 is 40 μA, and the collector current of the transistor T5 is 80 μA, which is twice 40 μA. When a low voltage is applied to the base of the transistor T7, the discharge circuit 18 is a discharge circuit that discharges a large amount of 80 μA compared to 4 μA.

  Here, the discharge current of the discharge circuit 17 that always discharges is 4 μA, and the discharge current of the discharge circuit 18 that discharges according to the comparison result from the synchronization separation circuit 14 is 80 μA. The constant discharge 18 has a discharge amount 20 times that of the discharge circuit 17 that performs constant discharge, and there is a great difference in the discharge amount.

  One of the two discharge circuits shown in FIG. 1 is a diode clamp circuit that always discharges weakly. The capacity of the diode clamp circuit that always discharges is not so large. This is because, since the discharge is always performed, the synchronization separation may not be performed accurately if the discharge amount is increased.

  In consideration of the relatively limited ability of the diode clamp circuit that discharges constantly, a discharge circuit 18 that controls the discharge is provided according to the comparison result of the synchronization separation circuit 14. The discharge circuit 18 has a switch and is a keyed clamp circuit that determines whether to discharge or not to discharge. The switch is connected to an output signal from the synchronization separation circuit 14.

  The discharge circuit 18 has a larger discharge amount than the discharge circuit 17 in the on state, and does not discharge at all in the off state. If the discharge circuit 17 is not installed, but only the discharge circuit 18 is installed, the potential at the point P in FIG. 1 rises due to the influence of the V sag, and if it becomes higher than the slice level, the discharge path is completely absent. Therefore, the output of the synchronous separation circuit 14 does not become “L” even if time passes for a long time, and the potential does not drop due to discharge. The discharge circuit 17 is mounted in order to lower the potential at the front end (bottom) of the synchronization signal that has increased in potential due to the influence of V sag and has become higher than the slice level below the slice level.

  FIG. 4 is a waveform showing the timing at which the discharge circuit 18 discharges. The waveform shown in (1) of FIG. 4 is a waveform in a normal state. In the clamp circuit of the present application, when the composite video signal is lower than the slice level, the discharge circuit 18 discharges, whereby the potential of the front end (bottom) of the synchronization signal serving as a reference for detecting the vertical and horizontal synchronization signals included in the video signal. It works to align the to the clamp level.

  The waveform shown in (2) of FIG. 4 shows a case where the potential increases due to the influence of V sag. Once the tip (bottom) of the sync signal that is a reference for detecting the vertical and horizontal sync signals included in the video signal rises above the slice level, the point d in FIG. 1 remains “H”, and this state continues. The discharge circuit 18 is not discharged and the potential continues to rise.

  The waveform shown in (3) of FIG. 4 shows that when the potential rises due to the influence of V sag, the discharge circuit 17 performs a complementary operation, and the potential at the leading end (bottom) of the sync signal that has risen is set at the slice level. The operation of discharging to a lower potential is shown.

  The waveform shown in (4) of FIG. 4 shows a case where the discharge circuit 18 is deleted and only the discharge circuit 17 is used, and the discharge of the discharge circuit 17 is strengthened. The potential does not increase due to the influence of V sag. However, the portion where the potential at the highest point is flat originally becomes slanted by strong discharge, and it becomes impossible to perform synchronous separation accurately at the slice level.

  As described above, the discharge circuit 17 and the discharge circuit 18 complement each other and operate. By providing the diode clamp circuit and the keyed clamp circuit, it is possible to perform the clamping efficiently. The clamped video signal can be taken out as an output signal from the clamp output terminal 19 of FIG.

  Conventionally, the keyed clamp circuit generally has a narrow discharge period in order to avoid adverse effects on the video signal. The conventional keyed clamp circuit uses the output signal from the synchronization separation circuit as a trigger, and starts to store electric charge in the capacitor. A circuit is provided for quickly inverting the signal after waiting for the electric charge exceeding the preset value to be stored in the capacitor. A keyed clamp circuit that uses this period until inversion as a crank pulse to control discharge has a general configuration.

  The keyed clamp circuit of the present application is intended for synchronous separation, and some adverse effects on the video signal can be ignored.

  FIG. 5 (1) shows the relationship between a general keyed clamp discharge period and a video signal. It can be seen that the discharge period of the keyed clamp is narrow and does not affect the burst signal input thereafter.

  FIG. 5 (2) shows the relationship between the discharge period of the keyed clamp of the present application and the video signal. It can be seen that since the discharge period of the keyed clamp becomes longer, the burst signal inputted thereafter is affected. When the burst signal is affected by the discharge, there is an adverse effect that the color of the image displayed on the television is strange.

  The keyed clamp circuit of the present application is not used to project a video signal on a television. That is, the signal obtained by the synchronization separation is only used for timing adjustment. Therefore, it is possible to switch between discharging and not discharging of the discharge circuit 18 by using the output signal from the synchronization separation circuit 14 as it is. Therefore, it is not necessary to create a special narrow crank pulse.

  In the configuration of the present application, a circuit for generating a crank pulse having a narrow pulse width is not required, and an increase in circuit scale can be suppressed.

  From the above, when the potential at the point P in FIG. 1 is low, the potential is raised by the charging circuit 16, and when the potential at the point P in FIG. The clamp circuit is configured to be lowered and to keep the potential at the point P in FIG. 1 constant.

It is a block diagram which shows the clamp circuit which concerns on one Example of this invention. It is a block diagram which shows the conventional clamp circuit. FIG. 4 is a timing waveform diagram showing a specific operation of a clamp circuit according to an embodiment of the present invention. It is a timing waveform diagram which shows discharge of the discharge circuit 18 which concerns on one Example of this invention. It is a timing waveform diagram showing the relationship between the discharge period of the keyed clamp and the video signal according to one embodiment of the present invention.

Explanation of symbols

10 input terminal, 11 capacitor, 12 constant current source, 13 constant current source, 14 comparator, 15 output terminal, 16 charging circuit, 17 discharging circuit, 18 discharging circuit.

Claims (5)

A clamp circuit that is used in a sync separation circuit that synchronously separates a vertical sync signal and a horizontal sync signal included in a video signal, and that aligns the tips of the vertical sync signal and the horizontal sync signal to a clamp level,
A charging circuit that charges when the potential at the tip of the vertical synchronization signal and the horizontal synchronization signal is lower than the clamp level;
A discharge circuit that discharges when the potential of the tip of the vertical synchronization signal and the horizontal synchronization signal is high with respect to the clamp level, and
The discharge circuit has a first discharge part and a second discharge part, the first discharge part has a period for discharging and a period for not discharging, and the second discharge part is always discharged. A clamp circuit that is characterized.   The clamp circuit according to claim 1, wherein the first discharge unit switches between discharging and not discharging according to an output signal from the synchronization separation circuit.   2. The clamp circuit according to claim 1, further comprising a transistor, wherein the discharge circuit is connected to an emitter of the transistor. A clamp circuit that is used in a synchronization separation circuit that synchronously separates a vertical synchronization signal and a horizontal synchronization signal in a video signal, and that aligns the tips of the vertical synchronization signal and the horizontal synchronization signal to a clamp level,
A first transistor;
A clamp capacitor, one connected to the input terminal and the other connected to the emitter of the first transistor;
A second transistor to which an output signal from the clamp capacitor is applied to a base;
A discharge circuit connected to the emitter of the second transistor;
A comparator in which a base of the second transistor is connected to one input terminal, and a reference voltage used for comparison is applied to the other input terminal;
The discharge circuit has a first discharge part and a second discharge part, the first discharge part has a period of discharging and a period of not discharging, and the second discharge circuit always discharges. A clamp circuit characterized by A synchronous separation circuit comprising the clamp circuit according to claim 1.