JP2006252454A - Method and circuit for controlling memory, semiconductor device and memory device having the same circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory device having a method for controlling a memory of high transfer efficiency, a memory control circuit, a semiconductor storage device having the same circuit, in the memory device having a memory control method which performs control to transfer data outputted from a plurality of masters respectively to required memory of low addresses, the memory control circuit, the semiconductor device having the same circuit. <P>SOLUTION: The method for the high efficient data transfer rate comprises the steps of: outputting a command for activating a second row address memory to be sent in a next sequence and putting the second row address memory into an active state while a data is transferred to a first row address memory; setting an output timing for the command prior to a time required for activating the second row address memory after the data is transferred to the first row address memory; and setting the output timing in accordance with a timing for a memory operating frequency. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a memory control method, a memory control circuit, a semiconductor device having the circuit, and a memory device having the circuit.

  Conventionally, a storage device using a memory such as an SDRAM (Synchronous Dynamic Random Memory) includes a memory control circuit that controls data transfer to the memory, and performs data transfer to the memory based on control by the memory control circuit. (For example, refer to Patent Document 1).

  The memory control circuit includes a multiplexer circuit that generates a required signal based on each signal input from a plurality of masters that respectively output a memory address signal, a transfer number signal, and a data signal. A command generation circuit for generating a required command signal for controlling the memory based on the signal is provided, and the command signal generated by the command generation circuit is input to the memory. The memory address signal is a signal composed of address information of the memory to be accessed. The transfer number signal is a signal composed of remaining amount information of data to be transferred to the memory at the address specified by the memory address signal. It is a signal consisting of the data itself.

  In particular, the multiplexer circuit also receives a priority signal for designating the priority order of a plurality of masters, so that data transfer is executed in the order of masters with the highest priority.

  The memory control circuit also compares the memory address signals output from the respective masters with each other to generate a comparison result signal, and an active command from the command generation circuit based on the comparison result signal generated by the comparison circuit. An ACT determination circuit that generates a first enable signal serving as a timing signal for outputting the ACT is provided, and the first enable signal generated by the ACT determination circuit is input to the multiplexer circuit.

  Here, the generation of the command signal will be described in some detail based on the timing chart of FIG. For convenience of explanation, it is assumed that there are two masters, master A and master B, and that master A has a higher priority than master B.

  The memory address signal A_ADRS output from the master A is composed of bank address information, row address information, and column address (Clum Address) information, and the memory address output from the master B. The signal B_ADRS also includes bank address information, row address information, and column address information.

  The memory address signal A_ADRS, the transfer number signal A_TLEN, and the data signal A_DATA output from the master A are respectively input to the multiplexer circuit, and the memory address signal B_ADRS, the transfer number signal B_TLEN, and the data signal output from the master B are input. B_DATA is also input to the multiplexer circuit, and a priority signal is further input to the multiplexer circuit to generate an arbitration signal arb for designating a master to access the memory.

  The memory address signal A_ADRS output from the master A and the memory address signal B_ADRS output from the master B are respectively input to the comparison circuit to generate a comparison result signal comp, and ACT is determined based on the comparison result signal comp. The circuit generates a first enable signal acten and inputs it to the multiplexer circuit.

  Further, the negative signal reception control signals A_ACK_X and B_ACK_X output from the memory control circuit are input to the master A and the master B, respectively, and the addresses of the master A and the master B are based on the signal reception control signals A_ACK_X and B_ACK_X. Information, remaining amount information, and data can be updated.

  First, based on the signal input from the master A and the master B to the memory control circuit, the memory control circuit uses the arbitration signal arb generated based on the priority signal as the select signal to input from the master A having a higher priority. And the input from the master B is started based on the end of the input from the master A.

  The multiplexer circuit of the memory control circuit receives the memory address signal A_ADRS, transfer number signal A_TLEN, and data signal A_DATA input from the master A, and the memory address signal B_ADRS, transfer number signal B_TLEN, and the data signal B_DATA input from the master B. The knitting memory address signal M_ADRS, the knitting transfer number signal M_TLEN, and the knitting data signal M_DATA that are sequentially knitted are generated and input to the command generation circuit, and the second enable signal is based on the first enable signal acten input from the ACT determination circuit. Acten2 is generated and input to the command generation circuit.

  The command generation circuit first outputs a transcommand (Trans) for transferring data to a memory having a predetermined row address in the bank A of the memory as a command signal SDRAM_COM. Based on the enable signal acten2, an active command (ACT) for activating the row address of the bank B to be transferred next is output as the command signal SDRAM_COM.

  Here, in the memory that has received the active command, a predetermined time must elapse before the memory at the transfer destination row address becomes ready for transfer. A stop command (NOP) for stopping the data transfer operation to the memory at the row address is output as the command signal SDRAM_COM. Here, the command generation circuit outputs a stop command (NOP) for 3 clocks as a command signal SDRAM_COM, with 3 clocks being a predetermined time in the drive clock.

During this time, the command generation circuit outputs the same input address signal SDRAM_ADRS and input bank address signal SDRAM_BA until the memory accepts the required transfer, and the command generation circuit transfers the required row address to the memory. By outputting (Trans) as the command signal SDRAM_COM, the transfer of the input address signal SDRAM_ADRS and the input bank address signal SDRAM_BA to the required memory is resumed.
JP 2002-251320 A

  However, in the memory control by the memory control circuit described above, the active signal (ACT) that activates the next row address to be accessed is output after the transfer processing to the predetermined row address is completed. At the same time, there is a problem that a waiting time is generated before the activated row address becomes transferable, and there is a problem that transfer efficiency is lowered.

  According to a memory control method of the present invention, in a memory control method for performing control for transferring data output from a plurality of masters to a memory having a required row address, the data is transferred to the memory having a first row address. In the middle of the process, a command to activate the memory of the second row address to be transferred next is output. Further, the command output timing may be at least before the time required to activate the memory at the second row address from the time when the data transfer to the memory at the first row address is completed. It is also characterized by the fact that the output timing of the command is the timing that matches the operating frequency of the memory.

  The memory control circuit of the present invention transfers data to the memory at the first row address in the memory control circuit for controlling the data output from the plurality of masters to the memory at the required row address. During the process, command generation means for outputting a command for activating the memory of the second row address to be transferred next is provided. Further, the command output timing is set to a timing at least before the time required for bringing the memory at the second row address into the active state from the time when the data transfer to the memory at the first row address is completed. The adjustment means is also provided, and the command output timing is also set to a timing that matches the operating frequency of the memory.

  Further, in the semiconductor device having the memory control circuit of the present invention, in the semiconductor device having the memory control circuit that performs control for transferring the data output from each of the plurality of masters to the memory of the required row address, While the data is being transferred to the memory at the row address, the memory control circuit is provided with command generation means for outputting a command that activates the memory at the second row address to be transferred next.

  Further, in the storage device having the memory control circuit of the present invention, in the storage device having the memory control circuit that performs control for transferring the data output from each of the plurality of masters to the memory of the required row address, While the data is being transferred to the memory at the row address, the memory control circuit is provided with command generation means for outputting a command that activates the memory at the second row address to be transferred next.

  According to the first aspect of the present invention, in the memory control method for performing control for transferring data output from a plurality of masters to a memory having a required row address, the data is transferred to the memory having the first row address. In the middle of the operation, a command to activate the memory of the second row address to be transferred next is output, so that the second row address memory is activated using the period during which the memory of the second row address is in the active state. Since data can be transferred to the memory of one row address, the transfer efficiency can be improved.

  According to a second aspect of the present invention, in the memory control method according to the first aspect, the output timing of the command is determined from the time when the data transfer to the memory of the first row address is completed, to the memory of the second row address. Since the data transfer to the memory at the first row address is completed, the data to the memory at the second row address is not delayed significantly after the data transfer to the memory at the first row address is completed. Transfer can be started, and transfer efficiency can be further improved.

  According to a third aspect of the present invention, in the memory control method according to the first or second aspect, the memory of the first row address is obtained by setting the command output timing to a timing that matches the operating frequency of the memory. After the data transfer to is completed, the data transfer to the memory of the second row address can be started without causing a delay as much as possible, and the transfer efficiency can be further improved.

  According to the fourth aspect of the present invention, in the memory control circuit that performs control for transferring the data output from each of the plurality of masters to the memory at the required row address, the data is transferred to the memory at the first row address. During the operation, a command generating means for outputting a command for setting the memory of the second row address to be transferred next to the active state is provided, so that a period during which the memory of the second row address is in the active state is used. Since data can be transferred to the memory at the first row address, a memory control circuit with improved transfer efficiency can be provided.

  According to a fifth aspect of the present invention, in the memory control circuit according to the fourth aspect, the output timing of the command is determined from the time when the data transfer to the memory of the first row address is completed, By providing adjustment means for setting the timing at least before the time required to set the active state to the active state, after the data transfer to the memory of the first row address is completed, the first delay is not caused. Data transfer to the memory of the second row address can be started, and a memory control circuit with further improved transfer efficiency can be provided.

  According to a sixth aspect of the present invention, in the memory control circuit according to the fourth or fifth aspect, the command output timing is set to a timing that matches the operating frequency of the memory. After the data transfer to the memory is completed, the data transfer to the memory of the second row address can be started without causing a delay as much as possible, and a memory control circuit with further improved transfer efficiency can be provided.

  According to the seventh aspect of the present invention, in a semiconductor device having a memory control circuit that performs control for transferring data output from a plurality of masters to a memory of a required row address, the memory of the first row address In the middle of transferring data to the memory, the memory control circuit is provided with command generating means for outputting a command to activate the memory of the second row address to be transferred next, so that the memory of the second row address is provided. Since data can be transferred to the memory of the first row address using the period in which the memory cell is in the active state, a semiconductor device having a memory control circuit with improved transfer efficiency can be provided.

  According to the eighth aspect of the present invention, in a storage device having a memory control circuit for performing control for transferring data output from a plurality of masters to a memory of a required row address, the memory of the first row address In the middle of transferring data to the memory, the memory control circuit is provided with command generating means for outputting a command to activate the memory of the second row address to be transferred next, so that the memory of the second row address is provided. Since data can be transferred to the memory of the first row address using the period in which the memory cell is in the active state, a memory device having a memory control circuit with improved transfer efficiency can be provided.

  In a memory control method, a memory control circuit, a semiconductor device having the memory control circuit, and a memory device having the memory control circuit according to the present invention, data output from a plurality of masters is stored in a memory having a required row address. MEMORY CONTROL METHOD FOR CONTROL FOR TRANSFER, MEMORY CONTROL CIRCUIT, SEMICONDUCTOR DEVICE HAVING THE MEMORY CONTROL CIRCUIT, AND STORAGE DEVICE HAVING THE MEMORY CONTROL CIRCUIT, At the time of output, a command to activate the memory of the second row address to be transferred next is output while data is being transferred to the memory of the first row address.

  That is, it has a plurality of banks such as SDRAM (Synchronous Dynamic Random Memory), etc., and each bank can be independently switched between an active state and an inactive state, and only in the memory of the bank in the active state. In an accessible memory, it is necessary to perform memory control for making the memory active before accessing the memory in the inactive bank. The memory control circuit controls the memory to be active. Is going.

  At this time, the memory control circuit activates the memory in the required bank by inputting the required command to the memory, and the required memory is completely activated by the command from the time when the command is input to the memory. Since a predetermined time lag occurs until this time is reached, a command to activate the memory of the second row address to be transferred next is output in advance while data is being transferred to the memory of the first row address. As a result, until the memory at the second row address is completely activated, data is transferred to the memory at the first row address, and the generation of time lag is suppressed to improve transfer efficiency. It is what.

  In particular, when the output timing of the command is at least before the time required to activate the memory at the second row address from the time when the data transfer to the memory at the first row address is completed. After the data transfer to the memory at the first row address is completed, the data transfer to the memory at the second row address can be started without causing a large delay, and the transfer efficiency can be further improved. .

  In addition, when the output timing of the command is the timing that matches the operating frequency of the memory, the second row address is generated without causing a delay as much as possible after the data transfer of the first row address to the memory is completed. The data transfer to the memory can be started, and the transfer efficiency can be further improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of the memory control circuit 10 of the present embodiment. In the following description, for convenience of explanation, the same reference numerals as those used in the above-mentioned section of the prior art refer to the same reference unless otherwise specified, and redundant description is omitted.

  In this embodiment, the memory control circuit 10 is supplied with memory address signals A_ADRS, B_ADRS, transfer number signals A_TLEN, B_TLEN, and data signals A_DATA, B_DATA from two masters A21 and B22, respectively. ing. As shown in the timing chart of FIG. 2, the memory address signals A_ADRS and B_ADRS are composed of bank address information, row address information, and column address information.

  The memory control circuit 10 receives the arbitration circuit 11 that arbitrates the input from the master A21 and the input from the master B22, and the memory address signals A_ADRS and B_ADRS of the memory address signals A_ADRS and B_ADRS, respectively, and generates the comparison result signal comp Multiplexer circuit 13 that receives the signal output from the arbitration circuit 11, the memory address signals A_ADRS, B_ADRS, the transfer number signals A_TLEN, B_TLEN, and the data signals A_DATA, B_DATA to generate the required signals And a command generation circuit 14 that generates a required command signal for controlling the memory 30 based on the signal generated by the multiplexer circuit 13.

  Further, the multiplexer circuit 13 inputs negative signal reception control signals A_ACK_X, B_ACK_X to the master A21 and the master B22, and the master A21 and the master B22 based on the signal reception control signals A_ACK_X, B_ACK_X. Address information, remaining amount information, and data can be updated.

  Hereinafter, the arbitration circuit 11 which is a main part of the present invention will be described in detail.

  The arbitration circuit 11 includes a priority determination circuit 11a and an ACT determination circuit 11b. The priority determination circuit 11a includes a transfer number signal A_TLEN input from the master A21 and a transfer number signal B_TLEN input from the master B22. The transfer processing priority is determined from the priority information signal PR for specifying the priority of the master A21 and the master B22. The ACT determination circuit 11b is a signal output from the priority determination circuit 11a. The first enable signal acten that defines the output timing of the active command input to the memory 30 is generated from the comparison result signal comp output from the comparison circuit 12 and the clock signal CLK having the same frequency as the operating frequency of the memory 30. It is configured as follows.

  The priority order information signal PR is a signal that designates the priority order by using the IDs assigned in advance to the master A21 and the master B22. In this embodiment, the master A21 has a higher priority order than the master B22. And Here, for convenience of explanation, it is assumed that the ID of the master A21 is represented as “masterA_ID” and the ID of the master B22 is represented as “masterB_ID”.

  The priority order determination circuit 11a makes an access request to the memory 30 from the transfer number signal A_TLEN which is the remaining transfer number information of the master A21, the transfer number signal B_TLEN which is the remaining transfer number information of the master B22, and the priority order information signal PR. The first arbitration signal arb1 for outputting the ID information of the master having the highest priority and the access request to the memory 30, and the ID information of the master having the second highest priority are output. 2 An arbitration signal arb2 and a remaining transfer number signal LEN that requests access to the memory 30 and outputs the remaining transfer number information of the master with the highest priority are output, and the respective signals arb1, arb2, LEN Is input to the ACT determination circuit 11b.

  In particular, in the priority order determination circuit 11a, the following four types of output forms are generated from the combination of the transfer number signal A_TLEN input from the master A21 and the transfer number signal B_TLEN input from the master B22. .

(1) When the transfer number signal A_TLEN ≠ 0 and the transfer number signal B_TLEN ≠ 0, the first arbitration signal arb1 = masterA_ID,
Second arbitration signal arb2 = masterB_ID,
Remaining transfer number signal LEN = Master A21 transfer number signal A_TLEN.

(2) When the transfer number signal A_TLEN ≠ 0 and the transfer number signal B_TLEN = 0, the first arbitration signal arb1 = masterA_ID,
Second arbitration signal arb2 = masterB_ID,
Remaining transfer number signal LEN = Master A21 transfer number signal A_TLEN.

(3) When the transfer number signal A_TLEN = 0 and the transfer number signal B_TLEN ≠ 0, the first arbitration signal arb1 = masterB_ID,
Second arbitration signal arb2 = masterA_ID,
Remaining transfer number signal LEN = transfer number signal B_TLEN of master B22.

(4) When the transfer number signal A_TLEN = 0 and the transfer number signal B_TLEN = 0 First arbitration signal arb1 = masterA_ID,
Second arbitration signal arb2 = masterB_ID,
Remaining transfer number signal LEN = transfer number signal A_TLEN of master A21 = 0.

  In the ACT determination circuit 11b, the first arbitration signal arb1, the second arbitration signal arb2, the remaining transfer number signal LEN input from the priority determination circuit 11a, and the comparison result signal comp input from the comparison circuit 12 Therefore, the first enable signal acten and the arbitration signal arb indicating the master to be prioritized at the time of processing are mainly used.

  Here, in the present embodiment, the memory 30 requires a time lapse of 3 clocks with the clock signal of the operating frequency until reaching the state where the next command can be received after the active command is input. And

  When the comparison circuit 12 compares the memory address signal A_ADRS of the master A21 and the memory address signal B_ADRS of the master B22 and detects that the output of the active command is necessary due to the different address, the comparison circuit 12 is positive. A certain comparison result signal comp outputs “1”.

  That is, the ACT determination circuit 11b operates as follows based on the comparison result signal comp.

(1) When the comparison result signal comp = “0” Arbitration signal arb = First arbitration signal arb1,
The first enable signal acten = "0".

(2) When the comparison result signal comp = “1” and the remaining transfer number signal LEN ≧ “4” Arbitration signal arb = First arbitration signal arb1,
The first enable signal acten = "0".

(3) When the comparison result signal comp = “1” and the remaining transfer number signal LEN <“4”, the arbitration signal arb = the second arbitration signal arb2,
The first enable signal acten = "1".

  If the first enable signal acten = “1” is output once in the case of the comparison result signal comp = “1” and the remaining transfer number signal LEN <“4”, the comparison result signal comp = “1” at the next clock. In addition, output is performed when the remaining transfer number signal LEN ≧ “4”.

  Here, the clock signal CLK having the same frequency as the operation frequency of the memory 30 is input to the ACT determination circuit 11b so that the ACT determination circuit 11b operates at the same timing as that of the memory 30, and “1” is output in the arbitration signal arb. The timing can be set so as not to be greatly delayed from the operation timing of the memory 30, and the output timing of the active command to the memory 30 can be optimized.

  In the present embodiment, after an active command is input to the memory 30, it takes 3 clocks of time for the operating frequency clock signal to reach a state where the memory 30 can accept the next command. As a result, the “remaining transfer number signal LEN =“ 4 ”” is used as a determination criterion in the ACT determination circuit 11b, but may be “4” or more. However, in the case of “4” or more, there is a possibility that extra power consumption may occur due to a period in which data transfer is not performed in spite of being in an active state. It is desirable to use “the time required for the memory 30 to be in an active state after an active command is input” as a reference.

  The operation of the memory control circuit 10 will be briefly described below based on the timing chart of FIG.

  First, based on the signal input from the master A21 and the master B22 to the memory control circuit, the memory control circuit 10 uses the arbitration circuit 11 generated by the arbitration circuit 11 based on the priority order signal PR as a select signal for the priority order. The input from the high master A21 is given priority, and the input from the master B22 is started based on the end of the input from the master A21.

  The multiplexer circuit 13 of the memory control circuit 10 includes a memory address signal A_ADRS, a transfer number signal A_TLEN, and a data signal A_DATA input from the master A21, and a memory address signal B_ADRS, a transfer number signal B_TLEN, and a data signal B_DATA input from the master B22. Knitting memory address signal M_ADRS, knitting transfer number signal M_TLEN, and knitting data signal M_DATA are generated and input to the command generation circuit 14 and the first enable signal acten input from the arbitration circuit 11 is used. 2 enable signal acten2 is generated and input to the command generation circuit 14.

  The command generation circuit 14 first outputs a trans command (Trans) for transferring data to a memory at a predetermined row address in the bank A of the memory as a command signal SDRAM_COM, and inputs the input address signal SDRAM_ADRS and the input bank to the memory at the required address. Output of address signal SDRAM_BA is started.

  When the transfer number signal A_TLEN of the master A21 becomes “3”, the arbitration circuit 11 outputs the first enable signal acten = “1”, thereby outputting the second enable output based on the first enable signal acten. In response to the signal acten2, the command generation circuit 14 outputs an active command (ACT) as the command signal SDRAM_COM, and activates the row address of the bank B.

  Thereafter, the arbitration circuit 11 outputs the first enable signal acten = “0”, whereby the input address signal SDRAM_ADRS and the input bank to the memory of the predetermined row address in the bank A preferentially designated in the arbitration signal arb Resumes output of address signal SDRAM_BA.

  When the transfer to the bank A is completed, since the bank B is already in the active state, the command generation circuit 14 sends a transcommand (Trans) for transferring the required row address of the bank B to the memory. By outputting as SDRAM_COM, the input address signal SDRAM_ADRS and the input bank address signal SDRAM_BA are immediately transferred to the memory of the bank B.

  By configuring such a memory control circuit 10 on a semiconductor substrate as a semiconductor device, it is possible to provide a memory control semiconductor device with high transfer efficiency, and configure a memory device including this semiconductor device. By doing so, it is possible to provide a storage device with high transfer efficiency.

It is a block diagram of a memory control circuit according to the present invention. 3 is a timing chart showing the operation of the memory control circuit according to the present invention. 6 is a timing chart showing the operation of a conventional memory control circuit.

Explanation of symbols

10 Memory control circuit
11 Arbitration circuit
11a Priority decision circuit
11b ACT decision circuit
12 Comparison circuit
13 Multiplexer circuit
14 Command generation circuit
21 Master A
22 Master B
30 memory

Claims (8)

In a memory control method for performing control for transferring data output from a plurality of masters to a memory having a required row address,
A memory control method, comprising: outputting a command to activate a memory of a second row address to be transferred next while data is being transferred to a memory of a first row address.   The output timing of the command should be at least before the time required to activate the memory at the second row address from the time when the data transfer to the memory at the first row address is completed. The memory control method according to claim 1, wherein:   The memory control method according to claim 1, wherein the output timing of the command is set to a timing in accordance with an operating frequency of the memory. In a memory control circuit that performs control for transferring data output from a plurality of masters to a memory at a required row address,
A memory comprising the command generation means for outputting a command for activating a memory at a second row address to be transferred next while data is being transferred to a memory at a first row address. Control circuit.   The output timing of the command is set to a timing at least before the time required for bringing the memory at the second row address into the active state from the time when the data transfer to the memory at the first row address is completed. A memory control circuit, characterized in that an adjustment means is provided.   6. The memory control circuit according to claim 5, wherein the output timing of the command is set to a timing that matches the operating frequency of the memory. In a semiconductor device having a memory control circuit that performs control for transferring data output from a plurality of masters to a memory having a required row address,
The memory control circuit is provided with the command generation means for outputting a command for activating the memory at the second row address to be transferred next while data is being transferred to the memory at the first row address. A semiconductor device having a memory control circuit. In a storage device having a memory control circuit that performs control for transferring data output from a plurality of masters to a memory of a required row address,
The memory control circuit is provided with the command generation means for outputting a command for activating the memory at the second row address to be transferred next while data is being transferred to the memory at the first row address. A memory device having a memory control circuit.

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