JP2006245358A - Insulating gate type semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an insulating gate type semiconductor device which has a floating region in its drift region, and can exhibit the performance of the device at a maximum. <P>SOLUTION: In the semiconductor device 100, each gate trench 21 piercing a p<SP>-</SP>body region 41 in the thickness direction of a semiconductor substrate is formed. In the bottom of each gate trench 21, each deposited insulating layer 23 is generated by the deposition of an insulator. Further, a gate electrode 22 is formed on the deposited insulating layer 23. In the semiconductor device 100, the thickness of an n<SP>-</SP>drift region 12 is so designed that it is made nearly equal to the thickness of the necessary depletion layer present in the n<SP>-</SP>drift region 12. Moreover, in the semiconductor device 100, each p floating region 51 surrounded by the n<SP>-</SP>region 12 is so formed that it locates in the middle position of the distance between the lower end of the gate electrode 22 and the bottom surface of the n<SP>-</SP>drift region 12. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an insulated gate semiconductor device having a trench gate structure. More specifically, the present invention relates to an insulated gate semiconductor device having a floating region in a drift region and capable of maximizing device performance.

  Conventionally, a trench gate type semiconductor device having a trench gate structure has been proposed as an insulated gate type semiconductor device for power devices. In a trench gate type semiconductor device, an electric field is generally concentrated at the bottom of a gate electrode built in a gate trench, and a decrease in breakdown voltage due to the concentration of the electric field becomes a problem.

As a trench gate type semiconductor device paying attention to this problem, for example, there is one disclosed in Patent Document 1. This trench gate type semiconductor device is schematically configured as shown in FIG. That is, in the semiconductor device 900 in FIG. 11, the N ⁺ source region 31 is provided on the upper surface side, and the N ⁺ drain region 11 is provided on the lower surface side. Between them, a P ⁻ body region 41 and an N ⁻ drift region 12 are provided from the upper surface side. Furthermore, a gate trench 21 formed by digging a part of the upper surface side of the semiconductor device is provided. A gate electrode 22 is built in the gate trench 21. A P floating region 51 is provided immediately below the gate trench 21. Gate electrode 22 is insulated from P ⁻ body region 41 by a gate insulating film 24 formed on the wall surface and bottom surface of trench 21.

In the semiconductor device 900, a depletion layer extends from the PN junction between the P ⁻ body region 41 and the N ⁻ drift region 12 toward the N ⁺ drain region 11 by applying a drain-source voltage (hereinafter referred to as “P ^- "Depletion layer from the body region 41"). When the depletion layer from the P ⁻ body region 41 reaches the P floating region 51, the P floating region 51 enters a punch-through state and the potential is fixed. Further, a depletion layer extends from the lower end of the P floating region 51 toward the N ⁺ drain region 11 (hereinafter referred to as “depletion layer from the P floating region 50”). As a result, the electric field concentration portion is divided into two portions, the electric field concentration at the bottom of the gate electrode 22 is alleviated, and a high breakdown voltage between the drain and the source can be achieved.

In addition, Patent Document 1 discloses a semiconductor device 910 in which the film thickness on the bottom side of the gate insulating film 24 is thicker than that on the side surface as shown in FIG. Specifically, the film thickness on the bottom side is in the range of 5 to 20 times the film thickness on the side surface (the film thickness on the side surface is 0.1 μm, and the film thickness on the bottom side is 0.5 μm to 2.0 μm. Within the range of As described above, increasing the thickness of the gate insulating film 24 alleviates the electric field concentration and can increase the breakdown voltage between the drain and the source.
Japanese Patent Laid-Open No. 10-98188 (FIG. 1, FIG. 9 etc.)

  However, the conventional trench gate type semiconductor device described above has the following problems. That is, as shown in FIG. 11, even if the P floating region 51 is provided immediately below the gate electrode 22, it does not reach the maximum performance of the device.

That is, in order to maximize the performance of the device, as shown in FIG. 13, the peak value of the electric field strength (A) supported by the depletion layer from the P ⁻ body region 41 in the N ⁻ drift region 12 , It is necessary to make the peak values of the electric field strength (B) supported by the depletion layer from the P floating region 51 uniform and bring these peak values close to the critical electric field.

However, in the semiconductor device 900 shown in FIG. 11, the peak value of the electric field strength (A) is smaller than the peak value of the electric field strength (B) as shown in FIG. That is, the peak value of the electric field strength (A) is small because the depletion layer from the P ⁻ body region 41 reaches the P floating region 51 without being fully extended. Accordingly, the breakdown voltage of the entire semiconductor device 900 is reduced.

  Even if the film thickness on the bottom surface side of the gate insulating film 24 is increased to 20 times the film thickness on the side surface as in the semiconductor device 910 shown in FIG. The thickness of the depletion layer from the P body region 41 is not sufficiently secured. Therefore, even the semiconductor device 910 does not reach the maximum performance of the device.

  The present invention has been made to solve the problems of the conventional insulated gate semiconductor device described above. That is, an object of the present invention is to provide an insulated gate semiconductor device that has a floating region in the drift region and can maximize the performance of the device.

  An insulated gate semiconductor device for solving this problem is an insulated gate semiconductor device having a trench gate structure, and is located on the upper surface side in a semiconductor substrate and includes a body region which is a first conductivity type semiconductor. , In contact with the lower surface of the body region, the drift region which is the second conductivity type semiconductor, the floating region which is surrounded by the drift region and is the first conductivity type semiconductor, and penetrates the body region in the thickness direction, and its bottom portion is floating A trench portion located in the region, and a deposit insulating material located in the trench portion, the upper surface of which is located above the upper end of the floating region, and the body region in the thickness direction. A gate region facing the body region across the insulating film, the distance from the lower end of the gate region to the upper end of the floating region, I am characterized in that the distance from the lower end of the ring area to the lower surface of the drift region is substantially uniform.

  The insulated gate semiconductor device of the present invention is an insulated gate semiconductor device having a trench gate structure, and has a higher breakdown voltage due to a floating region in the drift region. The floating region is disposed in the drift region so that the distance from the lower end of the gate region to the upper end of the floating region is equal to the distance from the lower end of the floating region to the lower surface of the drift region. That is, the floating region is located approximately at the center in the thickness direction of the drift region.

  In general, a semiconductor device is designed so that the thickness of the drift region is equal to the necessary depletion layer thickness in the drift region. In the semiconductor device of the present invention, since the floating region is located at the center of the drift region in the thickness direction, the thickness of the depletion layer from the body region is equal to the thickness of the depletion layer from the floating region. That is, the peak value of the electric field strength supported by the depletion layer from the body region is equal to the peak value of the electric field strength supported by the depletion layer from the floating region. Therefore, the device performance can be maximized.

  Note that “substantially equal” in the present invention does not mean only strict equality. In general, an epitaxial growth method, which is a film forming technique used for forming a semiconductor layer, or a trench etching technique, causes an error within a range of about 10%. Therefore, in this specification, an error within a range of ± 10% is included in the “substantially equal” range.

  The semiconductor device of the present invention includes a trench portion that penetrates the body region in the thickness direction. A floating region can be formed by performing ion implantation from the bottom of the trench. For this reason, it is easy to form a floating region.

  In addition, when the floating region is provided with n layers (n is a natural number) in the thickness direction of the drift region, and the floating region group is configured, the center of each floating region is from the lower end of the gate region to the lower surface of the drift region. It is good to be located in each part which divided | segmented the space | interval into n + 1 equally.

  That is, when forming n layers of floating regions, the floating regions of each layer are arranged at equal intervals in the thickness direction of the drift region. Further, a floating region is provided at each of the locations where the space between the lower end of the gate region and the lower surface of the drift region is equally divided into n + 1 so that the interval is maximized. Thereby, the thickness of the depletion layer from the body region and the thickness of the depletion layer from each floating region become substantially equal. That is, the peak values of the electric field strength supported by each depletion layer are substantially equal. As the number of floating region groups increases, the peak value of the electric field strength supported by each depletion layer decreases. Therefore, further higher breakdown voltage and lower on-resistance can be achieved.

  In the present invention, “n + 1 equal division” does not mean a strict equal interval. That is, in this specification, if it is within ± 10%, it is included in the range of “n + 1 equal”.

  In the semiconductor device of the present invention, a deposited insulating layer is provided in the trench portion. It is better if the gate electrode is located on the deposited insulating layer. In other words, the trench portion serves both as a floating region manufacturing purpose and a gate region holding purpose. Thereby, the semiconductor device can be made compact. Further, there is no need to separate the trench formation process, and a semiconductor device can be formed easily.

Specifically, when the deposited insulating layer is formed under the gate region, the thickness of the deposited insulating layer is
W0 = n × (required depletion layer thickness / (n + 1)) − within a range of ± 10% or less with respect to W0 calculated by the equation of the range during ion implantation. Note that n is a natural number and means the number of layers in the thickness direction of the drift region of the floating region group. The required depletion layer thickness is a required thickness of the depletion layer extending downward from the lower end of the gate electrode, and is determined by the required breakdown voltage and the impurity concentration of the drift region. By forming a deposited insulating layer with a thickness that satisfies the above conditions in the trench, the necessary depletion layer thickness for maximizing device performance is secured.

  According to the present invention, by defining the position of the floating region or the thickness of the deposited insulating layer, the necessary depletion layer thickness for maximizing the performance of the device is ensured. Therefore, an insulated gate semiconductor device having a floating region in the drift region and capable of maximizing device performance has been realized.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments embodying the present invention will be described below in detail with reference to the accompanying drawings. In the present embodiment, the present invention is applied to an insulated gate semiconductor device that controls conduction between a drain and a source (hereinafter, “between DS”) by applying a voltage to a gate electrode.

  An insulated gate semiconductor device 100 (hereinafter referred to as “semiconductor device 100”) according to the present embodiment has a structure shown in the cross-sectional view of FIG. Note that in this specification, the whole of the starting substrate and the single crystal silicon portion formed by epitaxial growth on the starting substrate is referred to as a semiconductor substrate.

In the semiconductor device 100, an N ⁺ source region 31 and a P ⁺ contact region 32 formed at a high concentration for lowering contact resistance are provided on the upper surface side in FIG. On the other hand, an N ⁺ drain region 11 is provided on the lower surface side. Between them, a P ⁻ body region 41 and an N ⁻ drift region 12 are provided from the upper surface side. In the semiconductor device 100, N ^- thickness of the drift region 12 and the N ^- require depletion layer Prefecture in the drift region 12 is designed so as to be substantially equal. Here, “substantially equal” does not mean strict equality, but is designed with some errors in consideration of manufacturing variations. The required depletion layer thickness in the N ⁻ drift region 12 will be described later.

Further, a part of the upper surface side of the semiconductor substrate is dug to form a gate trench 21 that penetrates the P ⁻ body region 41 in the thickness direction of the semiconductor substrate. A deposited insulating layer 23 is formed on the bottom of the gate trench 21 by depositing an insulator (for example, silicon oxide). Further, a gate electrode 22 is formed on the deposited insulating layer 23 by depositing a conductor (for example, polysilicon containing phosphorus at a high concentration). The lower end of the gate electrode 22 has a height position substantially equal to the lower surface of the P ⁻ body region 41. The gate electrode 22 faces the N ⁺ source region 31 and the P ⁻ body region 41 of the semiconductor substrate via the gate insulating film 24 formed on the wall surface of the trench 21. That is, the gate electrode 22 is insulated from the N ⁺ source region 31 and the P ⁻ body region 41 by the gate insulating film 24.

In the semiconductor device 100 having such a structure, a channel effect is generated in the P ⁻ body region 41 by applying a voltage to the gate electrode 22, thereby controlling conduction between the N ⁺ source region 31 and the N ⁺ drain region 11. is doing.

Further, in the semiconductor device 100, a P floating region 51 surrounded by the N ⁻ drift region 12 is formed. The center of the P floating region 51 is located approximately at the midpoint between the lower end of the gate electrode 22 and the lower surface of the N ⁻ drift region 12. The cross section of the P floating region 51 has a substantially circular shape centered on the bottom of the trench 21 as shown in the cross sectional view of FIG. There is sufficient space between the adjacent P floating regions 51 and 51. Therefore, in the ON state, the presence of the P floating region 51 does not hinder the drain current.

  Further, the upper end of the deposited insulating layer 23 is located above the upper end of the P floating region 51. Therefore, the gate electrode 22 deposited on the deposited insulating layer 23 and the P floating region 51 do not face each other. Details of the thickness of the deposited insulating layer 23 will be described later.

  Next, characteristics of the semiconductor device 100 of this embodiment will be described. Since the P floating region 51 is provided below the gate trench 21, the semiconductor device 100 has the following characteristics as compared with a trench gate type semiconductor device that does not have the P floating region 51.

That is, in the N ⁻ drift region 12, the depletion layer extends from the PN junction portion with the P ⁻ body region 41 toward the drain electrode by the applied voltage between the DSs. And the vicinity of the PN junction location becomes a peak of electric field strength. When the tip of the depletion layer reaches the P floating region 51, the P floating region 51 enters a punch-through state and its potential is fixed. Further, when the applied voltage between the DSs is high, the depletion layer spreads from the PN junction with the P floating region 51 toward the drain electrode. In addition to the PN junction between the P ⁻ body region 41 and the vicinity of the lower end of the P floating region 51, the electric field strength peaks. That is, electric field peaks are formed at two locations, and the maximum peak value can be reduced. Therefore, high breakdown voltage can be achieved.

In general, the breakdown voltage, the impurity concentration of the N drift region, and the thickness of the depletion layer extending in the N drift region have a relationship as shown in FIG. For example, in a normal MOSFET having a withstand voltage of 100 V class (MOSFET having no P floating region), it can be seen that a required depletion layer thickness of about 13 μm is required to obtain a withstand voltage of 100 V. Further, it can be seen that the impurity concentration in the N drift region is limited to about 3 × 10 ¹⁵ cm ⁻³ . In order to reduce the on-resistance, it is used at a concentration close to this limit value.

The relationship between breakdown voltage and depletion layer thickness is expressed by the following equation. That is, in the case of one-sided step junction (acceptor concentration> donor concentration), the critical electric field εcrit [Vcm ⁻¹ ] in which avalanche breakdown occurs is expressed by the following equation (1) or equation (2).
εcrit = 4 × 10 ⁵ / {1- (1/3) log (Nb / 10 ¹⁶ )} (1)
εcrit = 2 × Vb / Wd (2)
In the formula (1), Nb means the junction concentration, Wd means the depletion layer thickness, and Vb means the breakdown voltage. Therefore, by obtaining εcrit by equation (1), a relational expression between the breakdown voltage Vb and the depletion layer thickness Wd can be obtained. The depletion layer thickness Wd can also be expressed by the following equation (3).
Wd = (2Kε0Vb / qNd) ^1/2 (3)
In equation (3), K is the relative dielectric constant of the semiconductor, ε0 is the vacuum dielectric constant, q is the charge, and Nd is the donor concentration of the N drift layer.

In addition, the semiconductor device 100 has the following characteristics because the deposited insulating layer 23 is provided in the gate trench 21. That is, since the P floating region 51 is formed by ion implantation or the like from the bottom of the gate trench 21 as will be described later, the bottom of the gate trench 21 is damaged to some extent. Therefore, the presence of the deposited insulating layer 23 avoids the influence of damage to the bottom of the gate trench 21 and prevents inconveniences such as deterioration of device characteristics and deterioration of reliability. In addition, the deposited insulating layer 23 reduces the influence of the facing of the gate electrode 22 and the P floating region 51, and reduces the on-resistance in the P ⁻ body region 41. In addition, since the gate electrode 22 is small compared to the case where the deposited insulating layer 23 is not provided, the gate-drain capacitance Cgd is small and the switching speed is fast.

In addition, the semiconductor device 100 has the following characteristics by disposing the P floating region 51 in the central portion in the thickness direction in the N ⁻ drift region 12. In other words, the performance of the semiconductor device can be maximized.

That is, in order to maximize the performance of the device, as shown in FIG. 13, the peak value of the electric field strength (A) supported by the depletion layer from the P ⁻ body region 41 and the P floating region 51 The peak value of the electric field strength (B) supported by the depletion layer must be made equal. The relationship between the critical electric field and the breakdown voltage is obtained by the following equation (4).
E = qNbW / ε (4)
In Equation (4), E means electric field strength, q means elementary charge, Nb means impurity concentration, W means depletion layer thickness, and ε means dielectric constant. As shown in Equation (4), the electric field strength E is proportional to the depletion layer thickness W. In other words, it is understood that the depletion layer thickness W should be equalized in order to make the electric field strength E equal.

In the semiconductor device 100 of the present embodiment, the P floating region 51 is disposed in the central portion in the thickness direction in the N ⁻ drift region 12. As a result, the thickness of the depletion layer from the P ⁻ body region 41 is equal to the thickness of the depletion layer from the P floating region 51. Therefore, the electric field intensity distribution as shown in FIG. 13 is obtained, and the device performance can be maximized.

In the semiconductor device 100, the gate trench 21 is deepened so that the P floating region 51 can be disposed in the central portion in the thickness direction in the N ⁻ drift region 12, and the deposited insulating layer 23 is not deteriorated so as not to deteriorate the device characteristics. Is forming. Specifically, the thickness W0 of the deposited insulating layer 23 is obtained as follows.

First, the necessary depletion layer thickness W in the N ⁻ drift region 12 in the semiconductor device 100 is according to the following equation (5). For simplification of description, the positions of the lower end of gate electrode 22 and the lower surface of P ⁻ body region 41 are made equal (see FIG. 3).
W = A + B + 2r + 2p (5)
In equation (5), A is the distance until the depletion layer from the P ⁻ body region 41 reaches the P floating region 51, B is the distance that the depletion layer extends from the P floating region 51, and r is the bias between DS When P is not applied, the thickness of the depletion layer formed around the P floating region 51, and p means the radius of the P floating region 51, respectively.

Then, the thickness W0 of the deposited insulating layer 23 is obtained by the following equation (6).
W0 = A + r + p- (ra) (6)
In formula (6), ra means the range at the time of ion implantation.

Further, the distance A and the distance B must be equal in order to maximize the performance of the device. Substituting this condition into equation (7) establishes the following equation (7).
A + r + p = (W / 2) (7)
By substituting this equation (7) into equation (6), the thickness W0 of the deposited insulating layer 23 is obtained by the following equation (8).
W0 = (W / 2) -ra (8)

When the position of the lower end of the gate electrode 22 is significantly below the lower surface of the P ⁻ body region 41, the required depletion layer thickness is obtained as the distance from the lower end of the gate electrode 22. Accordingly, the necessary depletion layer thickness in that case is increased by the distance from the P ⁻ body region 41 to the lower end of the gate electrode 22.

Further, the thickness r of the depletion layer when the bias between the DSs is 0V is obtained by the following equation (9).
r = √2εVbi / qNd (9)
In equation (9), Vbi means the built-in potential, and Nd means the impurity concentration (donor concentration) in the drift region.

  Next, the actual thickness of the deposited insulating layer 23 in the withstand voltage band of 60 V to 1500 V that is widely used for in-vehicle semiconductor devices will be described. In the following description, the range ra during ion implantation is 0.1 μm.

First, the case where the required withstand voltage is 60V will be described. In the 60V breakdown voltage zone, a depletion layer having a thickness of about 4 μm is required (see FIG. 2). In this breakdown voltage zone, the N ⁻ drift region 12 can be used in a high concentration region of 1.0 × 10 ¹⁶ cm ⁻³ or more, so the thickness of the epitaxial layer (N ⁻ drift region 12, P ⁻ body region 41, etc.) It becomes difficult to control the height. Therefore, it is desirable to design for the necessary depletion layer thickness. Therefore, the necessary depletion layer thickness W is set to 4.4 μm with a margin of about 0.4 μm. By substituting this necessary depletion layer thickness into equation (5), the thickness W0 of the deposited insulating layer 23 at the required breakdown voltage of 60V is obtained.
2.1 μm = (4.4 μm / 2) −0.1 μm
That is, it can be seen that the thickness of the deposited insulating layer 23 at the required withstand voltage of 60 V may be 2.1 μm.

Next, the case where the required withstand voltage is 1500 V will be described. In the 1500 V breakdown voltage zone, a depletion layer having a thickness of about 100 μm is required (see FIG. 2). In the high breakdown voltage zone, it is desirable to have a design that reliably avoids breakdown. Therefore, the necessary depletion layer thickness W is set to 200 μm. By substituting this necessary depletion layer thickness into equation (8), the thickness W0 of the deposited insulating layer 23 at the required 1500 V can be obtained.
100 μm≈ (200 μm / 2) −0.1 μm
That is, it can be seen that the thickness of the deposited insulating layer 23 at the required breakdown voltage of 1500 V may be 100 μm.

  From the above, it can be seen that in a semiconductor device (withstand voltage band of 60 V to 1500 V) widely used for an in-vehicle semiconductor device, the thickness of the deposited insulating layer 23 should be in the range of 2.1 μm to 100 μm.

Subsequently, a manufacturing process of the semiconductor device 100 shown in FIG. 1 will be described. First, an N ⁻ type silicon layer is formed on the N ⁺ substrate to be the N ⁺ drain region 11 by epitaxial growth. This N ⁻ -type silicon layer (epitaxial layer) is a portion that becomes each of the N ⁻ drift region 12, the P ⁻ body region 41, and the N ⁺ source region 31. Then, a P ⁻ body region 41, an N ⁺ source region 31 and a P ⁺ contact region 32 are formed by subsequent ion implantation or the like. The thickness of the N ⁻ drift region 12 is designed to be equal to the necessary depletion layer thickness.

Next, a gate trench 21 that penetrates through the P ⁻ body region 41 and reaches the bottom of the N ⁻ drift region 12 is formed. Specifically, the bottom portion of the gate trench 21 is positioned above the center portion in the thickness direction of the N ⁻ drift region 12 by the range.

  Next, ion implantation is performed from the bottom surface of the gate trench 21. Next, an insulator (silicon oxide or the like) 23 is deposited in the gate trench 21 by the CVD method. Thereafter, a thermal diffusion process is performed for both the baking of the insulator and the formation of the P floating region 51. Thereby, the P floating region 51 is formed. Next, a part of the insulator is removed by etching the semiconductor substrate on which the insulator is deposited. Thereby, a space for forming the gate electrode 22 is secured.

  Next, an oxide film 24 is formed on the upper surface of the semiconductor substrate and the wall surface of the trench 21 by thermal oxidation. This becomes the gate oxide film 24. Then, a gate electrode 22 is formed by depositing a conductor (such as polysilicon containing phosphorus at a high concentration) in the space secured in the previous step. Finally, the source electrode and the drain electrode are formed, whereby the semiconductor device 100 as shown in FIG. 1 is manufactured.

As described above in detail, in the semiconductor device 100 according to the present embodiment, the high breakdown voltage is achieved by providing the P floating region 51 in the N ⁻ drift region 12. Furthermore, the thickness of the N ⁻ drift region 12 is designed to be equal to the required depletion layer thickness, and the P floating region is arranged at the center in the thickness direction of the N ⁻ drift region 12. That is, the distance from the lower end of the gate electrode 22 to the upper end of the P floating region 51 is made equal to the distance from the lower end of the P floating region 51 to the lower surface of the N ⁻ drift region 12. Thereby, the peak value of the electric field intensity near the lower end of the gate electrode and the peak value of the electric field intensity near the lower end of the P floating region 51 are substantially equal, and the breakdown voltage of the semiconductor device having the P floating region is maximized. In addition, the on-resistance can be reduced by increasing the breakdown voltage. Therefore, an insulated gate semiconductor device having a floating region in the drift region and capable of maximizing device performance has been realized.

  In particular, the withstand voltage band of in-vehicle power devices is a wide range of 60V to 1500V. The semiconductor device 100 according to this embodiment defines the thickness of the deposited insulating layer 23, in other words, by defining the position of the P floating region 51, so that such an in-vehicle power device (especially a low withstand voltage of 60V to 100V). Bandwidth devices) can be maximized.

[Application example]
As shown in FIG. 4, the semiconductor device 110 of this application example has a two-layer P floating region 51 (the upper P floating region 51 is a P floating region 511 and the lower P floating region 51 is a P floating region 512). It has a structure with. This is different from the semiconductor device 100 (FIG. 1) configured only by the single-layer P floating region 51. Specifically, the center of each P floating region is arranged at each of the three portions from the lower end of the gate region 22 to the lower surface of the N ⁻ drift region 12.

  In this semiconductor device 110, electric field peaks are formed at three locations (the lower end of the gate electrode 22, the lower end of the P floating region 511, and the lower end of the P floating region 512). Therefore, there are three places for supporting the withstand voltage, and the withstand voltage supported at each place can be smaller than that of the semiconductor device 100. Therefore, a higher breakdown voltage can be achieved.

  The number of electric field peak points can be increased as the number of layers of the P floating region 51 is increased. Therefore, the higher the number of layers of the P floating region 51, the higher the breakdown voltage and the lower on-resistance can be achieved.

The required layer thickness W0 of the deposited insulating layer 23 of the semiconductor device 110 shown in FIG. 4 can be calculated by the same method as the semiconductor device 100 shown in FIG. That is, it can be shown by the following equation (10).
W0 = 2 × (necessary depletion layer thickness / 3) −r0 (10)

The required layer thickness W0 of the deposited insulating layer 23 when the number of layers of the P floating region 51 is n can be expressed by the following equation (11).
W0 = n × (necessary depletion layer thickness / (n + 1)) − r0 (11)

The semiconductor device 110 of this application example is manufactured by the following manufacturing process. That is, after the P ⁻ body region 41 is formed, the gate trench 21 is formed to a depth where the upper P floating region 511 can be formed. Thereafter, ion implantation and thermal diffusion treatment are performed to form a P floating region 511.

  Next, the gate trench 21 is dug down to a depth where the lower P floating region 512 can be formed. Next, ion implantation is performed again. Thereafter, an insulator is deposited in the gate trench 21 by CVD. Thereafter, a thermal diffusion process is performed for both the baking of the insulator and the formation of the P floating region 512. As a result, a two-layer P floating region 51 is formed.

[Other application examples]
In addition, as shown in FIGS. 5 to 7, a semiconductor device in which the gate electrode 22 is not incorporated, the inside is filled with the deposited insulating layer 23, and the trench 25 whose bottom is located in the P floating region 51 is formed. Even so, the present invention can be applied. Of course, the P floating region 51 may have a single layer structure (FIG. 5) or a multilayer structure (FIGS. 6 and 7).

  In addition, as shown in FIGS. 8 to 10, a gate trench 21 containing the gate electrode 22 and a trench 25 filled with an insulator are mixed, and the bottom of these trenches is surrounded by a P floating region 51. The present invention can be applied even to a semiconductor device. Of course, the P floating region 51 may have a single layer structure (FIG. 8) or a multilayer structure (FIGS. 9 and 10).

  Further, when the P floating region 51 is formed in the trench 25, the thickness of the oxide film (the lower end of the gate electrode 22) is closer to the necessary depletion layer thickness because the trench 25 is entirely filled with an insulator. Become.

  Note that this embodiment is merely an example, and does not limit the present invention. Therefore, the present invention can naturally be improved and modified in various ways without departing from the gist thereof. For example, for each semiconductor region, P-type and N-type may be interchanged. Further, the gate insulating film 24 is not limited to an oxide film, and may be another type of insulating film such as a nitride film or a composite film. Also, the semiconductor is not limited to silicon, but may be other types of semiconductors (SiC, GaN, GaAs, etc.).

  The insulated gate semiconductor device of the embodiment can also be applied to a conductivity modulation type power MOS using a P type substrate.

  Further, the shape of the gate trench 21 of the semiconductor device 100 may be a long groove shape long in the depth direction of the paper, or a cylindrical shape arranged in a lattice shape or a staggered shape. Further, the P floating region 51 may be provided not only in the cell area of the semiconductor device but also in the termination area.

It is sectional drawing which shows the structure of the insulated gate semiconductor device which concerns on embodiment. It is a graph which shows the relationship between a proof pressure and a drift layer density | concentration. It is a figure which shows the outline of each variable required for the calculation conditions of the thickness of a deposited insulating layer. It is sectional drawing which shows the structure of the insulated gate semiconductor device which concerns on an application example. It is sectional drawing which shows the structure (the 1) of the insulated gate semiconductor device which concerns on another application example. It is sectional drawing which shows the structure (the 2) of the insulated gate semiconductor device which concerns on another application example. It is sectional drawing which shows the structure (the 3) of the insulated gate semiconductor device which concerns on another application example. It is sectional drawing which shows the structure (the 4) of the insulated gate semiconductor device which concerns on the other application example. It is sectional drawing which shows the structure (the 5) of the insulated gate semiconductor device which concerns on another application example. It is sectional drawing which shows the structure (the 6) of the insulated gate semiconductor device which concerns on another application example. It is sectional drawing which shows the structure (the 1) of the conventional trench gate type semiconductor device. It is sectional drawing which shows the structure (the 2) of the conventional trench gate type semiconductor device. 2 is a graph showing an electric field strength distribution of an XX cross section of the semiconductor device shown in FIG. 1. 12 is a graph showing an electric field intensity distribution of an XX cross section of the semiconductor device shown in FIG.

Explanation of symbols

11 N ⁺ drain region 12 N ⁻ drift region (drift region)
21 Gate trench (trench part)
22 Gate electrode (gate region)
23 Deposition insulation layer (Deposition insulation layer)
24 Gate insulating film 31 N ⁺ source region 41 P ^- body region (body region)
51 P floating area (floating area)
100 Insulated gate semiconductor device (Insulated gate semiconductor device)

Claims (4)

In an insulated gate semiconductor device having a trench gate structure,
A body region located on the upper surface side in the semiconductor substrate and being a first conductivity type semiconductor;
A drift region that is in contact with the lower surface of the body region and is a second conductivity type semiconductor;
A floating region surrounded by the drift region and being a first conductivity type semiconductor;
A trench portion penetrating the body region in a thickness direction, a bottom portion of which is located in the floating region;
A deposited insulating layer located in the trench portion and deposited with an insulator, the upper surface of which is located above the upper end of the floating region;
A gate region that penetrates the body region in the thickness direction and faces the body region with an insulating film interposed therebetween;
2. The insulated gate semiconductor device according to claim 1, wherein a distance from the lower end of the gate region to the upper end of the floating region is substantially equal to a distance from the lower end of the floating region to the lower surface of the drift region. In an insulated gate semiconductor device having a trench gate structure,
A body region located on the upper surface side in the semiconductor substrate and being a first conductivity type semiconductor;
A drift region that is in contact with the lower surface of the body region and is a second conductivity type semiconductor;
A floating region group which is surrounded by the drift region and is provided with n layers (n is a natural number) in the thickness direction of the drift region and is a first conductivity type semiconductor;
A trench portion that penetrates the body region in the thickness direction, and a bottom portion of which is located in the floating region of the lowest layer of the floating region group;
A deposited insulating layer located in the trench portion and deposited with an insulator, the upper surface of which is located above the upper end of the uppermost layer of the floating region group;
A gate region that penetrates the body region in the thickness direction and faces the body region across an insulating film;
The insulated gate semiconductor device, wherein the center of each floating region of the floating region group is located at each of n + 1 equally divided from the lower end of the gate region to the lower surface of the drift region. In the insulated gate semiconductor device according to claim 1 or 2,
The insulated gate semiconductor device, wherein the gate region is located in the trench portion and on the deposited insulating layer. In an insulated gate semiconductor device having a trench gate structure,
A body region located on the upper surface side in the semiconductor substrate and being a first conductivity type semiconductor;
A drift region that is in contact with the lower surface of the body region and is a second conductivity type semiconductor;
A floating region group which is surrounded by the drift region and is provided with n layers (n is a natural number) at substantially equal intervals in the thickness direction of the drift region, and is a first conductivity type semiconductor;
A trench portion penetrating the body region in a thickness direction, a bottom portion of which is located in the floating region;
A deposited insulating layer located in the trench portion and deposited with an insulator, the upper surface of which is located above the upper end of the uppermost layer of the floating region group;
A gate region located in the trench portion and on the deposited insulating layer, and facing the body region with an insulating film interposed therebetween;
The thickness of the deposited insulating layer is
W0 = n × (necessary depletion layer thickness / (n + 1)) − insulated gate type semiconductor device, which is within a range of ± 10% with respect to W0 calculated by the equation of the range during ion implantation .

Images