JP2006229732A - Reflection type phase shifter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a miniaturized and low-loss reflection type phase shifter to be used for radio communication. <P>SOLUTION: The reflection type phase shifter has an input terminal 11 where an inputted signal is reflected, one or more phase shifting circuits 15, and one or more field effect transistors 12, 14 and 16 for phase switching for switching the phase of the signal inputted from the input terminal by using the phase shifting circuits, wherein the input terminal, the phase shifting circuits and the transistors are formed on the same substrate, the field effect transistors are controlled to switch the phase shifting circuits, and low-loss reflected waves with a prescribed phase delayed are obtained. The reflection type phase shifter is a MMIC (monolithic microwave integrated circuit) configuration and its miniaturization is realized. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a phase shifter that is used in, for example, wireless communication and requires low voltage driving and excellent characteristics. More specifically, the present invention relates to a phase shifter that uses a phase shift circuit and a switch, switches the switch, and arbitrarily switches the phase of an input carrier wave (carrier).

  In wireless communication, when digital data is transmitted / received, a signal obtained by modulating a carrier wave is transmitted on the transmission side, and the signal is demodulated on the reception side to extract digital data. Among the modulation methods, the one that changes the phase of the carrier wave is phase modulation.

For example, a conventional example of the phase shifter 200 is shown in FIG. In the phase shifter 200 of FIG. 6, an input terminal T1 is connected to an input terminal of an SPDT (Single Pole Double Throw) switch 201, one output terminal a of the SPDT switch 201 is connected to the transmission line 202, and the other output terminal b is Each is connected to a transmission line 203. The output terminal of the transmission line 202 is connected to one input terminal c of the SPDT switch 204, and the output terminal of the transmission line 203 is connected to the other input terminal d. Then, a signal is output from the output terminal (T2) of the SPDT switch 204.
In addition, the phase delay amount can be arbitrarily set by changing the line lengths of the transmission lines 202 and 203. In the example of FIG. 6, the phase delay amount of the transmission line 202 is θ1, and the phase delay amount of the transmission line 203 is θ2.

Next, the operation of the phase shifter 200 will be described.
When an input signal, for example, a carrier wave is supplied from the input terminal T1 to the SPDT switch 201 and the SPDT switch 201 is switched and connected to the output terminal a, the phase is changed (delayed) by θ1 in the transmission line 202 and the SPDT switch of the next stage A signal is derived from the output terminal T2 via the input terminal c 204.
On the other hand, when the SPDT switch 201 is switched to the input terminal b, the signal input from the input terminal T1 is transmitted through the transmission line 203, where the phase is delayed by θ2, and the signal is delayed via the input terminal d of the SPDT switch 204 in the next stage. Thus, a signal is derived from the output terminal T2.
As a result, the difference (θ2−θ1) between the phase delay amount θ1 of the signal on the transmission line 202 and the phase delay amount θ2 of the transmission line 203 obtained by switching the SPD switches 201 and 204 is the total phase shift amount.
As described above, it is necessary to use two SPDT switches to delay a signal, and there is a disadvantage that the number of switches used for delaying the phase shift of one signal is large.

A configuration example of another phase shifter is shown in FIG. The phase shifter 220 shown in FIG. 7 has two phase shifters 200 shown in FIG. 6, and the phase delay amount is changed by changing the transmission line length of the subsequent phase shifter.
In the phase shifter 220 of FIG. 7, the input terminal T1a is connected to the input terminal of the SPDT switch 221, one output terminal a1 of the SPDT switch 221 is connected to the transmission line 222 of the phase delay amount θ1, and the other output terminal b1 is phase. Each is connected to a transmission line 223 having a delay amount θ2. The output terminal of the transmission line 222 is connected to one input terminal c1 of the SPDT switch 224, and the output terminal of the transmission line 223 is connected to the other input terminal d1. The output of the SPDT switch 224 is connected to the subsequent phase shifter via the connection line 230.
The configuration of the latter-stage phase shifter is the same as that of the preceding-stage phase shifter, but the transmission line 233 has a different line length, and its phase delay amount is θ3.
That is, the connection line 230 is connected to the input terminal of the SPDT switch 231, one output terminal a of the SPDT switch 231 is the transmission line 232 having the phase delay amount θ1, and the other output terminal b2 is the transmission line 233 having the phase delay amount θ3. Are connected to each. The output terminal of the transmission line 232 is connected to one input terminal c2 of the SPDT switch 234, and the output terminal of the transmission line 233 is connected to the other input terminal d2. Then, a phase-modulated signal is derived from the output terminal T2a of the SPDT switch 234.

Next, the operation of the phase shifter 220 will be described.
In a state where the SPDT switch 221 is switched and connected to the output terminal a1 and the SPDT switch 224 is connected to the input terminal c1, the SPDT switch 231 is connected to the output terminal a2 and connected to the input terminal c2 of the SPDT switch 234. Since the phase delay amount from the input terminal T1a to the connection line 230 is θ1 due to the transmission line 232, and the phase delay amount from the SPDT switch 231 to the output terminal T2a is θ1 due to the transmission line 232, the total is 2 × θ1. .
Next, when the SPDT switches 221 and 224 of the previous phase shifter are maintained as they are and the SPDT switches 231 and 234 of the subsequent phase shifter are switched, the output terminal b2 of the SPDT switch 231 is connected to the transmission line 233, Its output terminal is connected to the input terminal d2 of the SPDT, and the phase delay amount of the signal in the subsequent stage is θ3.
As a result, a value obtained by adding the phase shift delay amount θ1 of the preceding phase shifter and the delay amount θ3 of the subsequent phase shifter is a total phase delay amount, and the phase delay amount is θ1 + θ3.
Next, in a state where the SPDT switch 221 of the preceding phase shifter is switched and connected to the output terminal b1 and the SPDT switch 224 is connected to the input terminal d1, the SPDT switch 231 is connected to the output terminal a2, and the SPDT switch 221 is connected. When connected to the input terminal c2 of the switch 234, the phase delay amount from the input terminal T1a to the connection line 230 is θ2 by the transmission line 232, and the phase delay amount from the SPDT switch 231 to the output terminal T2a is θ1 by the transmission line 232. Therefore, the sum is θ2 + θ1.
Finally, when the SPDT switch of the previous phase shifter is maintained as it is and the SPDT switch of the subsequent phase shifter is switched, the output terminal b2 of the SPDT switch 231 is connected to the transmission line 233, and its output (side) is The phase delay amount of the signal in the subsequent stage is connected to the input terminal d2 of the SPDT and is θ3.
As a result, the total phase delay amount is θ2 + θ3.

  As described above, in the configuration using two stages of the phase shifter in FIG. 7, the four phase modes (2 × θ1, θ1 + θ3, 2 × θ1, θ1 + θ3) are obtained by changing the transmission line length by switching the SPDT switches 221, 224, 231 and 234. θ2 + θ1, θ2 + θ3) can be realized. However, one SPDT switch requires at least two FETs, and the two SPDT switches must be controlled for one phase, which is inefficient.

FIG. 8 shows an example of a phase shifter 240 using a divider which is another conventional example.
In the phase shifter 240 of FIG. 8, the input terminal T <b> 1 b is connected to the input terminal of the divider 241, and one output terminal of the divider 241 is connected to the SPST switch 245 via the connection line 243. The output terminal a of the SPST (Single Pole Single Throw) switch is connected to the input terminal of the microstrip line 247 of λ / 4 (where λ represents the wavelength of the signal; or λ / 4 phase shift circuit), and the other end Is open.
The other output terminal of the divider 241 is connected to one terminal of a λ / 8 microstrip line (λ / 8 phase shift circuit) 242, and the other terminal of the microstrip line 242 is connected to the SPST switch 244. . The output terminal b of the SPST switch 244 is connected to one terminal of a λ / 4 microstrip line 246, and the other end is open (open).

Next, the operation of the phase shifter 240 using a divider will be described.
When the SPST switches 244 and 245 are open, the signal reflected by the connection line 244 at the input terminal Tb1 (0 degree) and the signal reciprocated by the microstrip line 242 having a phase delay of λ / 8 are combined. The amount will be about 90/2 = 45 degrees.
Next, when the SPST switch 245 connects the switch to the terminal a and the terminal b is in the open state, the phase amount delayed by the connection line 243 and the microstrip line 247 is 180 degrees. As a result, the total phase delay amount is a sum of the phase delay amount of the microstrip line 247 and the phase delay amount of the microstrip line 242, and is approximately (180 + 90) / 2 degrees = 135 degrees.
When two SPST switches are switched together and connected to terminals a and b, the total phase delay amount is 180 degrees generated in the microstrip line 247 and 270 degrees generated in the microstrip lines 242 and 246. The value is about 225 degrees.
Although this conventional phase shifter 240 can apply phase modulation to the reflected wave, the number of switches can be reduced to one for one phase, but since the loss of the divider 241 is at least 3 dB, the phase shift is performed. The loss of the entire vessel will increase.
JP-A-6-104603

As described above, in a configuration using two stages of phase shifters, four phase modes can be realized by changing the transmission line length. However, at least two FETs are required for one SPDT switch, The two SPDT switches must be controlled for phase, which is inefficient.
Further, in the phase shifter using a divider, the number of switches can be reduced to one for one phase, but the loss of the divider is at least 3 dB, so that the loss of the entire phase shifter becomes large.
Furthermore, miniaturization and low loss of phase shifters are becoming strict in wireless communications, and as the phase shifters are integrated into ICs, miniaturization and low loss must be similarly achieved.

  The reflection type phase shifter of the present invention switches an input terminal for reflecting an input signal, one or more phase shift circuits, and a phase of the signal input from the input terminal using the phase shift circuit. One or more phase switching field effect transistors are included, and the input terminal, the phase shift circuit, and the transistor are formed on the same substrate.

  The reflection type phase shifter according to the present invention includes an input terminal provided on the same substrate, on which an input signal is reflected, and one or more phase switching electric fields for switching the phase of the signal input from the input terminal. An effect transistor; and a phase shift circuit provided outside the substrate and capable of switching a phase by the field effect transistor.

  The reflection type phase shifter of the present invention includes an input terminal for reflecting an input signal, a phase shift circuit having an input terminal and an output terminal, and a drain or a source connected to the input terminal. A first switching field effect transistor electrically connected to a first reference potential; a second switching transistor having a drain or source connected to the input terminal of the phase shift circuit and a drain or source connected to the input terminal; And a third field effect transistor for switching, in which the drain or source is connected to the output terminal of the phase shift circuit, and the drain or source is electrically connected to the second reference potential.

  The reflection type phase shifter of the present invention has an input terminal for reflecting an input signal, a phase shift circuit, a drain or a source connected to the phase shift circuit, and is connected to an input terminal of the phase shift circuit. A switching field effect transistor having a drain or a source not connected to the input terminal, and two or more series connection portions of the phase shift circuit and the field effect transistor are connected in parallel.

The reflection type phase shifter of the present invention can reduce the number of phase switching switches, and since no divider is used, loss due to the divider is eliminated, and loss of the entire phase shifter can be reduced.
The phase can be adjusted by inserting a passive element such as a capacitor between the phase switching field effect transistor and the GND.
In addition, by using the above-described phase shifter for wireless communication, downsizing and low loss can be realized as the phase shifter is integrated into an IC.

Hereinafter, embodiments of the phase shifter will be described with reference to the drawings.
FIG. 1 shows a circuit configuration of a phase shifter 10 as an embodiment. The antenna (Ant) 11 is connected to one terminal of FET (field effect transistor) 1 and FET 2, for example, in the case of an N channel, to the drain, and the other terminal, for example, source of FET 1 is connected to one terminal of the capacitor 13. The other terminal of the capacitor 13 is connected to the ground (GND1). The other terminal, for example, the source of the FET 2 is connected to one terminal of the microstrip line 15, the other terminal (b) is connected to the drain of the FET 3, and the source of the FET 3 is connected to one terminal of the capacitor 17. The other terminal is connected to the ground (GND2).
Here, the line length of the phase shift circuit (for example, microstrip line) 15 is λ / 8, the phase of the incident signal (carrier wave) is delayed by 45 degrees, and when the signal reciprocates, the phase is delayed by 90 degrees.

The operation of the phase shifter 10 in FIG. 1 will be described.
In the phase shifter 10, the phase is delayed by 45 degrees one way, 90 degrees reciprocation, and 180 degrees at the end of GND, so that the reflected wave can be modulated in four ways by 90 degrees by switching the switch. This will be described in detail below.
For example, when the gate G1 of the FET1 and the gate G2 of the FET2 are set to control voltages equal to or lower than the threshold value, the FET1 and FET2 are turned off (off; open), and the input carrier wave is reflected at the point a. The phase delay amount at this time is 0 degree.
Next, when a control voltage higher than the threshold value is supplied to the gate G2 of the FET2, and the gate G1 of the FET1 and the gate G3 of the FET3 are set to voltages lower than the threshold value, the FET1 is turned off and the FET2 is turned on. The FET 3 is turned OFF, and the carrier wave is reflected at the point b. However, the phase is delayed by 90 degrees because the carrier wave reciprocates through the phase shift circuit 15 as compared with the phase of the reflected wave at the point a.
If a control voltage higher than the threshold value is supplied to the gate G1 of the FET1 and the gate G2 of the FET2 is set to a voltage lower than the threshold value, the voltage FET1 is turned on and the FET2 is turned off, and the carrier wave is terminated at the GND1. , The phase is delayed by 180 degrees compared to the phase of the reflected wave at point a.
When the gate G1 of the FET 1 is set to a voltage lower than the threshold value and a voltage higher than the threshold value is supplied to the gate G2 of the FET 2 and the gate G3 of the FET 3, the FET 1 is turned off and the FET 2 and the FET 3 are turned on. Considering the round trip of the phase shift circuit 15 and the end of the GND 2, the phase of the reflected wave is delayed by 270 degrees compared to the phase of the reflected wave at point a. Therefore, by switching the switches FET1, FET2, and FET3, four phases can be set by 90 degrees.

  In the example of FIG. 1, since no divider is used unlike the phase shifter 240 of the conventional example of FIG. 8, the loss can be kept low, and the number of switching FETs may be one for each path. The entire circuit can be downsized. Further, the phase can be adjusted by inserting a passive element such as a capacitor or an inductor between the FET 1 and FET 3 and GND.

FIG. 2 shows a phase shifter 30 as another embodiment.
FIG. 2 is a circuit configuration example of the phase shift circuit 35a in which the phase shift circuit 15 in FIG. 1 is realized by a π-type circuit of a passive element CLC (C: capacitor, L: inductor). FIG. 2 basically includes only four FETs and a phase shift circuit 35a.
The antenna (Ant) 31 is connected to one terminal of the FET 1A (field effect transistor) 32, FET 2A (34), FET 4A (38), for example, when the FETs 1A to 4A are N-channel, respectively, and the other of the FET 1A (32). The terminal, for example, the source of the capacitor 33 is connected to the capacitor 33, and the other terminal of the capacitor 33 is connected to the ground (GND1). The source of the other terminal of the FET 4A (38) is connected to the receiving terminal Rx. The source of the other terminal of the FET 2A (34) is connected to one terminal of the phase shift circuit 35a, the other terminal (b) is connected to the drain of the FET 3A (36), and the source of the FET 3A (36) is The capacitor 37 is connected to one terminal, and the other terminal is connected to the ground (GND2).

Here, the phase shift circuit 35a corresponds to the microstrip line 15 of the line length λ / 8 in FIG. 1, and functions to delay the phase of the signal by 45 degrees. When the signal reciprocates, the phase is delayed by 90 degrees.
The circuit configuration of the phase shift circuit 35a is, for example, a lumped constant. One terminal of the capacitor C35b and the inductor L35d are connected to the source of the FET 2A, and the other terminal of the capacitor C35b is connected to GND2.
The other terminal of the inductor L35d is connected to the drain of the FET 3A and one terminal of the capacitor C35c, and the other terminal of the capacitor C35c is connected to GND2.

In the phase shifter 30 of FIG. 2, the FET 4A (38) supplies a control voltage equal to or higher than the threshold value to the gate G4A, and is turned on only when receiving a signal, and when the carrier wave is input from Ant31 and reflected, the gate G4A Is set to OFF below the threshold voltage.
Since the amount of phase shift of the phase shift circuit 35a constituting a part of the phase shifter 30 is 45 degrees one way and 90 degrees reciprocation, four phase modes can be realized by 90 degrees as described above.

Next, the operation of the phase shifter 30 will be described.
As described above, when the carrier wave is reflected, the gate G4A of the FET 4A (38) is set to a voltage equal to or lower than the threshold value to be in the OFF state. In this state, for example, when the gate G1A of the FET 1A and the gate G2A of the FET 2A are set to voltages below the threshold value, the FET 1A (32) and FET 2A (34) are turned off, and the input carrier wave is reflected at the point a. . The phase delay amount at this time is 0 degree.
Next, when the gate G1A of the FET 1A and the gate G3A of the FET 3A are set to a voltage lower than the threshold, and a control voltage higher than the threshold is supplied to the gate G2A of the FET 2A, the FET 1A (32) is turned OFF and the FET 2A (34). Is turned on and FET 3A (36) is turned off, and the carrier wave is reflected at the point b. However, the phase is delayed by 90 degrees because the carrier wave reciprocates through the phase shift circuit 35a as compared with the phase of the reflected wave at the point a.
When a control voltage equal to or higher than the threshold value is supplied to the gate G1A of the FET 1A and the gate G2A of the FET 2A is set to a voltage equal to or lower than the threshold value, the FET 1A (32) is turned on and the FET 2A (34) is turned off. Therefore, the phase is delayed by 180 degrees compared to the phase of the reflected wave at point a.
When the gate G1A of the FET 1A is set to a voltage equal to or lower than the threshold value and a control voltage higher than the threshold value is supplied to the gate G1A of the FET 1A and the gate G3A of the FET 3A, the FET 1A (32) is turned off and the FET 2A (34) When the FET 3A (36) is turned on and considering the round trip of the phase shift circuit 35a and the end of the GND 2, the phase of the reflected wave is delayed by 270 degrees compared to the phase of the reflected wave at point a.
Therefore, four phases can be switched by 90 degrees by switching the switches FET1A (32), FET2A (34), and FET3A (36).

  Thus, the phase shifter 30 can realize four phase modes by 90 degrees by switching the FET 1A (32), the FET 2A (34), and the FET 3A (36). Further, since the number of switching FETs may be one for each path, the entire circuit can be reduced in size. Further, by inserting a passive element such as a capacitor or an inductor between the FET 1A and the FET 3A and GND, the phase delay due to parasitic components such as stray capacitance can be adjusted.

FIG. 3 shows a phase shifter 50 according to another embodiment.
In the phase shifter 50 of FIG. 3, the three phase shift circuits are delayed in phase by 45 degrees, 90 degrees, and 135 degrees one way, respectively, and the phases are delayed by 90 degrees, 180 degrees, and 270 degrees, respectively.
In the phase shifter 50, the ANT 51 is connected to the contact a, and this contact a is connected to one terminal of the FET 1B (52), FET 2B (54), and FET 3B (56), for example, the drain in the case of an N-channel FET. .
The other terminal, for example, the source of the FET 1B (52) is connected to one terminal of the microstrip line 53 having a line length of λ / 8. The other terminal of the microstrip line 53 is open. As a result, the 90-degree reciprocal phase is delayed in the microstrip line 53.
Similarly, the other terminal, for example, the source of the FET 2B (54) is connected to one terminal of the microstrip line 55 having a line length of λ / 4. The other terminal of the microstrip line 55 is open. As a result, the phase of the reciprocating 180 degrees is delayed in the microstrip line 55.
The other terminal, for example, the source of the FET 3B (56) is connected to one terminal of the microstrip line 57 having a line length of 3λ / 8. The other terminal of the microstrip line 57 is open. As a result, the reciprocating phase of 270 degrees is delayed in the microstrip line 53.

Next, the operation of the phase shifter 50 will be described.
For example, when the gate G1B of the FET 1B, the gate G2B of the FET 2B, and the gate G3B of the FET 3B are set to voltages below the threshold value, the FET FET 1B (52) is turned off, the FET 2B (54) is turned off, and the FET 3B (56) is turned off. The carrier wave is reflected at point a and the phase delay amount is 0 degree.
When a control voltage equal to or higher than the threshold is supplied to the gate G1B of the FET 1B and the gate G2B of the FET 2B and the gate G3B of the FET 3B are set to voltages lower than the threshold, the FET 1B (52) is turned on and the FET 2B (54) Is OFF and the FET 3B (56) is OFF, and the carrier wave is reflected by the phase shift circuit 53 having a line length of λ / 8 and reciprocates through the phase shift circuit 53 as compared with the phase of the reflected wave at the point a. The phase is delayed by 90 degrees.
Further, when the gate G1B of the FET 1B and the gate G3B of the FET 3B are set to a voltage lower than the threshold value and a control voltage higher than the threshold value is supplied to the gate G2B of the FET 2B, the FET 1B (52) is turned OFF and the FET 2B (54) Is turned on and FET 3B (56) is turned off, the carrier wave is reflected by the λ / 4 phase shift circuit 55, and the phase is delayed by 180 degrees compared to the phase of the reflected wave at point a.
Further, when the gate G1B of the FET 1B and the gate G2B of the FET 2B are set to a voltage lower than the threshold value and a control voltage higher than the threshold value is supplied to the gate G3B of the FET 3B, the FET 1B (52) is turned OFF and the FET 2B (54) Is turned OFF and the FET 3B (56) is turned ON, and is reflected by the 3λ / 8 phase shift circuit 57, and the phase of the reflected wave is delayed by 270 degrees compared to the phase of the reflected wave at the point a.
Therefore, four phases can be switched by 90 degrees by switching the switches FET1B (52), FET2B (54), and FET3B (56).

FIG. 4 shows an embodiment in which the phase shifter 30 of FIG. 2 is formed on an MMIC (Monolithic Microwave Integrated Circuit).
4 (a) and 4 (b) are diagrams when the phase shifter 30 is built in the MMIC, FIG. 4 (a) is a view of the MMIC from the side, and FIG. 4 (b) is a diagram of the MMIC from the top. FIG. FIG. 4C is a diagram when the phase shift circuit 117 is realized by a π-type circuit of CLC (C: capacitor, L: inductor) in addition to the MMIC.
The phase shift amount of the phase shift circuit 117 of FIG. 4C is 45 degrees one way and 90 degrees reciprocation, and the phase shift method is the same as FIG. MMIC is a circuit element formed on a GaAs substrate with FETs, capacitors, inductors, and the like.
In general, the frequency band used in MMIC or the like is a high frequency wave such as a microwave, and therefore phase delay occurs due to parasitic components such as the inductance of the wire 114 and stray capacitance between the GaAs substrate 113 and the FET (112). Therefore, the phase can be adjusted by inserting the capacitor 116 in front of the GND terminal of the MMIC 110 as shown in FIG. An inductor such as a wire can be used depending on the rotation of the phase.

FIG. 5 shows the measurement results of the electrical characteristics of the MMIC 110 shown in FIG. The MMIC used for the measurement in FIG. 5 was manufactured for the purpose of use at 2.4 GHz. FIG. 5A shows the phase of the reflected wave, and FIG. 5B shows the loss of the reflected wave.
The electrical characteristics of FIG. 5A will be described using the phase shifter 30 of FIG. FIG. 5A shows the reflection coefficient (S parameter S11) viewed from the contact point a side from Ant 31 when the measurement frequency is scanned from 2.0 GHz to 3.0 GHz, and the mark indicates the value at 2.4 GHz. Yes.
In FIG. 2, when FET1A (32) and FET2A (34) are OFF, the input carrier wave is reflected at point a. The phase delay amount at this time is represented by a point m17 in the S11 chart of FIG. S11 of the S parameter is (amplitude) 0.930 / (phase) −35.517 degrees. Based on the phase rotation amount at this time, the switching phase of each FET is shifted. Further, the loss (loss) at this time is about 0.63 dB as indicated by a point m21 in FIG. 5B, and this loss includes a loss due to the substrate (about 0.35 dB at 2.4 GHz).
Next, when the FET 1A (32) is OFF, the FET 2A (34) is ON, and the FET 3A (36) is OFF, the phase is 90 degrees because the phase shift circuit 35a reciprocates compared to the phase of the reflected wave at the point a. Is delayed and becomes a point m18 in the S11 chart of FIG. This S11 is (amplitude) 0.821 / (phase) -126.627 degrees. The loss is about 1.7 dB as indicated by a point m22 in FIG.
When FET1A (32) is ON and FET2A (34) is OFF, the phase is delayed by 180 degrees compared to the phase of the reflected wave at point a, which becomes point m19 in the S11 chart of FIG. 5A, and S11 is (amplitude) 0.814 / (phase) -144.909 degrees. Further, the loss at this time is about 1.78 dB as indicated by m23 in FIG.
When FET1A (32) is OFF and FET2A (34) and FET3A (36) are ON, the phase of the reflected wave is 270 degrees behind the phase of the reflected wave at point a. m20, and S11 is (amplitude) 0.734 / (phase) −54.150 degrees. Further, the loss at this time is about 2.683 dB, as indicated by m24 in FIG.

In this way, it can be seen from FIG. 5 (a) that four phase modes can be realized at a phase of 90 degrees at 2.4 GHz. Also, when using a phase shifter at another frequency, the line length of the phase shift circuit or the value of C or L is changed, and the amount of phase shift is 45 degrees at that frequency, as in the case of using 2.4 GHz. Therefore, a 90 degree shift can be realized.
Further, the measurement data in FIG. 5 includes a loss of the measurement board of about 0.35 dB at 2.4 GHz. However, the loss is 3 dB or less from the measurement data in FIG. It can be seen that the loss of the circuit of the present invention can be made lower than when it is used.

  In the example described above, the FET is a general example, but specifically, it is configured on a compound (GaAs) semiconductor substrate, so that a junction FET, HEMT, junction HEMT, or the like can be used. Moreover, although the example of N channel FET was shown, it can also comprise by P channel FET.

As described above, the reflection type phase shifter of the present invention can reduce the number of phase switching switches, and since no divider is used, loss due to the divider is eliminated, and loss of the entire phase shifter can be reduced. it can.
The phase can be adjusted by inserting a passive element such as a capacitor between the phase switching field effect transistor and the GND.
In addition, by using the above-described phase shifter for wireless communication, downsizing and low loss can be realized as the phase shifter is integrated into an IC.

It is a circuit diagram which shows the circuit structure of the phase shifter which is the embodiment of this invention. It is a circuit diagram which shows the circuit structure of the other phase shifter which is the embodiment of this invention. It is a circuit diagram which shows the circuit structure of the other phase shifter which is the embodiment of this invention. It is the figure which showed the block diagram when the phase shifter shown in FIG. 2 is comprised by MMIC. FIG. 5 is a characteristic diagram showing a result of measuring electrical characteristics of the phase shifter shown in FIGS. 2 and 4. It is the circuit diagram which showed the circuit structure of the phase shifter of a prior art example. It is the circuit diagram which showed the circuit structure of the other phase shifter of a prior art example. It is the circuit diagram which showed the circuit structure of the other phase shifter of a prior art example.

Explanation of symbols

10, 30, 50, 200, 220, 240 ... phase shifter, 11, 31, 51 ... antenna (Ant), 12, 14, 16, 32, 36, 3852, 54, 56 ... FET (field effect transistor), 13, 17, 33, 37, 116, 117b, 117c ... capacitors, 15, 53, 55, 57, 242, 246, 247 ... microstrip lines, 70, 90, 110 ... MMIC (Monolithic Microwave Integrated Circuit), 74, 94, 114 ... bonding wire, 75, 95, 115 ... lead frame, 201, 204, 221, 224, 231, 234 ... SPDT (Single Pole Double Throw) switch, 202, 203, 222, 223, 232, 233 ... delay Track, 241 ... Divider (Divider), 245 ... SPST (Single Pole Single Throw) switch.

Claims (17)

An input terminal that reflects the input signal; and
One or more phase shift circuits;
One or more phase switching field effect transistors that switch the phase of the signal input from the input terminal using the phase shift circuit;
The input terminal, the phase shift circuit and the transistor are formed on the same substrate;
Reflective phase shifter. The reflection type phase shifter includes a receiving terminal, and a field effect transistor for switching that is formed on the substrate, has a drain or a source connected to the receiving terminal, and a drain or a source connected to the input terminal. The reflective phase shifter according to claim 1. The reflection type phase shifter according to claim 1, wherein the phase shift circuit includes a passive element. The reflection type phase shifter according to claim 1, wherein the phase shifter includes a phase adjustment element for phase adjustment between the field effect transistor and the reference potential or in the vicinity of the phase shift circuit. The reflection type phase shifter according to claim 1, wherein the field effect transistor is a junction gate type HEMT. The reflection type phase shifter according to claim 1, wherein the substrate is a compound semiconductor substrate, and the compound semiconductor substrate is sealed with a resin. An input terminal provided on the same substrate for reflecting an input signal; one or more phase switching field effect transistors for switching the phase of the signal input from the input terminal;
A reflection type phase shifter having a phase shift circuit provided outside the substrate and whose phase is switched by the field effect transistor. The reflective phase shifter according to claim 7, wherein the phase shift circuit includes a passive element. The reflection type phase shifter according to claim 7, wherein the phase shifter includes a phase adjustment element for phase adjustment between the field effect transistor and the reference potential or in the vicinity of the phase shift circuit. The reflection type phase shifter according to claim 7, wherein the field effect transistor is a junction gate type HEMT. The reflective phase shifter according to claim 7, wherein the substrate is a compound semiconductor substrate, and the compound semiconductor substrate is resin-sealed. An input terminal that reflects the input signal; and
A phase shift circuit having an input terminal and an output terminal;
A first field effect transistor for a switch having a drain or a source connected to the input terminal and the drain or source electrically connected to a first reference potential;
A second field effect transistor for a switch having a drain or a source connected to an input terminal of the phase shift circuit, and a drain or a source connected to the input terminal;
A reflection type phase shifter comprising: a third field effect transistor for switch having a drain or a source connected to an output terminal of the phase shift circuit and a drain or a source electrically connected to a second reference potential. The reflection type phase shifter according to claim 12, wherein the phase shift circuit includes a passive element. The reflection type phase shifter according to claim 12, wherein the phase shifter includes a phase adjustment element for phase adjustment between the field effect transistor and the reference potential or in the vicinity of the phase shift circuit. The reflection type phase shifter according to claim 12, wherein the field effect transistor is a junction gate type HEMT. The reflective phase shifter according to claim 12, wherein the substrate is a compound semiconductor substrate, and the compound semiconductor substrate is sealed with a resin. An input terminal;
A phase shift circuit;
A field effect transistor for a switch having a drain or source connected to the phase shift circuit and a drain or source not connected to an input terminal of the phase shift circuit connected to the input terminal;
A reflection type phase shifter, wherein two or more series connection portions of the phase shift circuit and the field effect transistor are connected in parallel.

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