JPH0370380B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic switch that uses field effect transistors (FETs) to switch signal paths from DC to several GHz. The present invention relates to a configuration that is easy to perform and has excellent insertion loss and isolation characteristics over a wide band.

In the field of wireless communications, high frequency switches using electronic devices are used to quickly select or switch between multiple high frequency signals. Conventionally, high frequency switches without gain include (1) those using PIN diodes or shot key diodes, (2)
One that uses a FET analog switch is being considered. Among these, according to (1), it is possible to obtain good characteristics in terms of insertion loss, isolation, etc., which are important characteristics of a high-frequency switch. high power consumption. In addition, since a diode is a two-terminal element, a circuit is required to separate the high-frequency signal and the control signal. Conventionally, the high-frequency signal is AC coupled, and the bias current is supplied via a coil to separate the two signals in terms of frequency. They were separated. Therefore, the band of the high frequency signal is limited to a certain lower limit frequency. Furthermore, since the band of the control signal is also limited, there is a limit to increasing the switching speed. Furthermore, since it requires a coil, it is difficult to make it into a monolithic IC, which poses a problem in mass production.

On the other hand, according to configuration (2), since the FET is a voltage controlled element, it can be easily controlled on and off by simply changing the gate voltage, but since the FET is used as a passive element, no drain bias is required. Therefore, power consumption can be reduced to almost zero. Also,
Since the FET is a three-terminal element, the high frequency signal and the control signal are separated in advance, and there is no need to limit the bands of both signals. Therefore, it is possible to widen the band of high-frequency signals and improve switching speed. Furthermore, since the bias circuit does not require a coil, it is easy to make it into a monolithic IC, and it is also possible to configure many switches on one chip. The FET used for this is required to have low on-resistance and low interelectrode capacitance, but in particular gallium
Arsenic FETs (GaAs FETs) have an advantage in this respect,
A broadband high frequency switch can be realized.

However, switches using FETs had the disadvantage that isolation and insertion loss at high frequencies were slightly inferior to configuration (1). This point will be explained below. Figure 1a is GaAs
A conventional configuration example of a high frequency switch using FET,
Figure b shows the equivalent circuit. In the figure, 1 is the first high frequency signal input/output terminal (port 1), 2 is the second high frequency signal input terminal (port 2), 3 is the control voltage input terminal, and 4 is the normal
This is a switch FET using an on-type GaAs FET.
The drain D of the switch FET 4 is connected to the terminal 1, the source S is connected to the terminal 2, and the gate G is connected to the control voltage input terminal 3 via a bias resistor _RG . Note that D _DS is the drain-source capacitance of the FET, C _DG is the drain-gate capacitance, C _GS is the gate-source capacitance, and on-resistance R _ON is the drain-source resistance (channel resistance) when the FET is on. It is. Also, the gate width of switch FET4
W _g is 500μm when line impedance is 50Ω
~2000μm is selected. Furthermore, terminals 1 and 2
The DC potential of is assumed to be zero. In this configuration, when the terminal 3 is grounded, the FET 4 becomes zero bias, the drain and source become conductive, and the switch is turned on. Furthermore, when a voltage lower than the threshold voltage of the FET (reverse bias) is applied to terminal 3, the FET is turned off. When the switch is off, it is represented by the equivalent circuit shown in figure b. In terms of direct current, ports 1 and 2 are cut off, but in terms of alternating current, the series capacitances of _CDS , _CDG , and _CGS are connected. It is tied together. That is, the apparent capacitance C _T between port 1 and port 2 is C _T = C _DS + C _DG ·C _GS / (C _DG + C _GS ) (1). As the frequency increases, the impedance of C _T decreases, so isolation between ports deteriorates. For this reason, there was a drawback that the usable band was narrow.

In order to improve isolation, _CT can be made smaller. Therefore, the FET gate width W _g
A conceivable configuration is to reduce the interelectrode capacitance by narrowing C _T . However, if W _g is narrowed, the channel resistance R _ON increases, so insertion loss increases. The gate width required to reduce insertion loss to 1 dB or less is the transmission line impedance.
When R ₀ is 50Ω, it is about 500 μm to 2000 μm, and below this value, the loss increases rapidly. Therefore, there is a limit to the configuration in which C _T is reduced by narrowing W _g .

Next, in the high frequency switch shown in FIG. 1, since ports 1 and 2 are open when in the off state, input waves may be reflected, which may be inconvenient. Conventionally,
In such cases, a terminal type switch as shown in FIG. 2a has been used. This configuration has two terminating resistors R ₀ , terminating control FETs 6 and 7,
It has an additional termination control voltage input terminal 5 and bias resistor R _G2 . When turning off this switch, a reverse bias is applied to terminal 3, terminal 5 is grounded, and FETs 6 and 7 are turned on. As a result, port 1 and port 2 are terminated with an impedance of R ₀ and reflection can be suppressed. Furthermore, when turning on the switch, terminal 3 is grounded and reverse bias is applied to terminal 5. At this time,
FET4 is turned on, and FETs 6 and 7 are turned off, as shown in the equivalent circuit shown in FIG. However, the capacity C _T ,
C _T2 and C _T3 are the apparent capacitances between the sources and drains of FET4, FET6, and FET7, respectively. The gate width of each of these FETs is selected to be approximately 500 μm to 2000 μm in order to make the on-resistance R _ON sufficiently smaller than the line impedance R ₀ . Therefore,
In this configuration, C _T , C _T2 , and C _T3 are quite large;
The disadvantage is that the insertion loss increases as the frequency increases due to the π-shaped network consisting of three parts: the parallel impedance of R _ON and _CT , the series impedance of _CT2 and R _O , and the series impedance of _CT3 and _R 0. It was hot.

The present invention solves these drawbacks by (1) providing a circuit that grounds the gate at high frequency only when the switch FET is off, thereby achieving isolation without increasing insertion loss when the switch FET is on; (2) In the termination type switch, instead of the termination resistor and termination control FET, a termination FET whose on-resistance is equal to the termination resistance is used to suppress the increase in insertion loss at high frequencies. It provides a switch.

The present invention will be explained in detail below.

FIG. 3a shows a first embodiment of the present invention, in which
1, 2, 3, and 4 are the same as in FIG. 1a. Further, 8 is a gate switch control voltage input terminal, 9 is a gate switch FET, and the drain D of FET9 is connected to the gate G of FET4 via a capacitor C _G.
The source S is grounded, and the gate G is connected to the terminal 8. Furthermore, it is assumed that C _G ≫C _DG and C _GS .

This circuit is obtained by adding a circuit to the circuit shown in FIG. 1A to ground the gate at high _frequency only when the switch FET 4 is off. When turning off this switch, use terminal 3.
A reverse bias is applied to the terminal 8 and the terminal 8 is grounded. At this time, FET4 is turned off and FET9 is turned on, and the equivalent circuit of the switch becomes as shown in FIG. In addition, C _G
The impedance of is omitted because it is sufficiently small. Further, the on-resistance of FET9 is also omitted because it can be made sufficiently smaller than the impedance of C _DG and C _GS by making the gate width of FET9 about one-tenth of the gate width of FET4. From this equivalent circuit, the apparent capacitance C _T ′ between ports 1 and 2 is calculated as C _T ′=
C _DS , and compared to C _T in the circuit of Figure 1a, C _DG and
It becomes smaller because there is no series capacitance of C _GS . Therefore, this configuration reduces isolation by several dB to 10 dB.
It can be improved to some extent. On the other hand, when turning on this switch, terminal 3 is grounded and reverse bias is applied to terminal 8. At this time, FET4 is turned on and FET9 is turned off, and the equivalent circuit of the switch can be written as shown in figure c. However, C _T4 is FET9
is the apparent capacitance between the drain and source of
Now, set the gate width of FET9 to 10 of the gate width of FET4.
Even if it is reduced to about one-fold, there is a sufficient effect of improving isolation, so C _T4 can be made about one-tenth of C _DG and C _GS of FET4. Therefore, the influence of CT4 is small,
When it is on, the configuration is almost equivalent to that of FIG. 1a, and equivalent characteristics can be obtained. In this way, the configuration of FIG. 3a makes it possible to provide a high frequency switch with good isolation even at high frequencies.

FIG. 4a shows a second embodiment of the present invention, showing the construction of a terminal type switch. 1, 2, in the diagram
3, 4, and 5 are the same as in Figure 2 a, and 1
0 and 11 are termination FETs whose on-resistance is equal to the termination resistance R ₀ . Generally, the on-resistance of a FET is inversely proportional to the gate width, so any desired on-resistance can be obtained by changing the gate width. As an example, a GaAs FET with R _ON = R ₀ = 50Ω
The gate width is about 50 μm to 200 μm.

When turning off this termination type switch, reverse bias is applied to terminal 3 and terminal 5 is grounded. As a result, FET4 is turned off and FET10 and 11 are turned on, so port 1 and port 2 are
It is terminated by on-resistances R ₀ of 6 and 7, and reflection can be suppressed. Further, when turning on this switch, terminal 3 is grounded and terminal 5 is applied with a reverse bias. At this time, FET4 is on, FET
10 and 11 are turned off, which can be expressed by the equivalent circuit shown in FIG. However, capacitances C _T , C _T2 ′, and C _T3 ′ are the apparent capacitances between the sources and drains of FET4, FET10, and FET11, respectively, and C _T is calculated from the above equation (1).
It can be expressed as From this equivalent circuit, when the termination type switch is on, the parallel impedance of R _ON and C _T , C _T2 ′, and C _T3 ′ form a π-type network, and as the frequency increases, the insertion loss increases. I understand that. However, C _T2 ′ and C _T3 ′ are
Letting the gate widths of FET4, FET10, and FET11 be W _g1 , W _g2 , and W _g2 respectively, it can be expressed as C _T2 ′=C _T3 ′=(W _g2 /W _g1 )・C _T (2), and now W _g1 is 500 μm~ 2000μm, W _g2
C _T2 ′ and
C _T3 ′ is about 1/10 of C _T. On the other hand, Fig. 2b
As mentioned above, C _T2 and C _T3 in the equivalent circuit of
Since they were almost the same value as C _T , C _T2 ′ and C _T3 ′ are C _T2 ,
It is about one-tenth of C _T3 , and it is possible to suppress the increase in insertion loss caused by the π-type network.

In this way, the configuration shown in FIG. 4a makes it possible to provide a terminated switch with low insertion loss even at high frequencies.

The above two embodiments are examples in which the characteristics of the high frequency switch are improved by using different configurations, but it is also possible to modify the two configurations so that they are used in combination. FIG. 5a shows an embodiment in which two configurations according to the present invention are applied to a single-pole, double-throw termination type changeover switch. In the same figure, 1 indicates ports 1 and 2.
Ports 2, 4 and 15 are switch FETs, 9 and 16 are gate switch FETs, 10 and 17 are termination FETs, 12 is the third high frequency signal input/output terminal (port 3), and 13 and 14 are control voltage input terminals. be. In addition, the gate width of switch FETs 4 and 15 is about 500 μm to 2000 μm,
The gate widths of FETs 9 and 16 are selected to be approximately 50 μm to 200 μm, and the gate widths of termination FETs 10 and 17 are selected to be approximately 50 μm to 200 μm so that the on-resistance is equal to the value of the termination resistance.

This changeover switch has the function of selecting either port 1 or port 3, connecting it to port 2, and terminating the remaining ports. First, when connecting port 1 and port 2, terminal 13 is grounded and reverse bias is applied to terminal 14. As a result, FET4, FET16, and FET17 are turned on, and FET9, FET10, and FET15 are turned off, so that ports 1 and 2 are electrically connected by FET4, and ports 3 and 2 are opened. Furthermore, the gate G of FET15 is C _G and FET
16 to ground, and port 3 is terminated by FET 17. The equivalent circuit at this time can be expressed as shown in FIG. 5b. However, the gate switch
Regarding the apparent capacitance between the drain and source of FETs 9 and 16 and termination FETs 10 and 17, as explained above, switch FETs 4 and 1
It is omitted because it is sufficiently small compared to the capacity of 5. From this equivalent circuit, port 1 and port 2 are of FET4.
Since they are connected at low impedance through R _ON and C _DS , C _DG , and C _GS , insertion loss is low up to high frequencies, and ports 3 and 2 are connected to C _DS of FET15.
It can be seen that high isolation can be obtained because the bond is made only by

In this way, with the configuration shown in FIG. 5a, it is possible to provide a single-pole, double-throw termination type changeover switch with low insertion loss and good isolation up to high frequencies.

Furthermore, even when increasing the number of input/output ports and generally configuring a changeover switch of n ports x m ports, the two configurations according to the present invention and the above modification are effective, and even in that case, even high frequencies can be inserted. A high frequency switch with low loss and good isolation can be provided.

As described above, the present invention provides a high frequency switch with low insertion loss and excellent isolation characteristics over a wide band with extremely low power consumption.
Since it can be realized with a GaAs monolithic IC, it can be used especially for diversity switching in mobile communications and SS-TDMA (Satellite-TDMA) in satellite communications.
Switched Time-Division-Multiple-Access)
By applying it to a wide range of wireless communication equipment, including switching switches for
It can greatly contribute to economicization.

[Brief explanation of drawings]

Figure 1a is a circuit diagram showing a conventional configuration example of a high frequency switch using GaAs FET, Figure 1b is its equivalent circuit diagram, and Figure 2a is a circuit diagram showing a conventional configuration example of a termination type switch. FIG. 3a is a circuit diagram showing the first embodiment of the present invention, FIG. 4b is an equivalent circuit diagram thereof, and FIG. 4a is a circuit diagram showing the second embodiment of the present invention.
Fig. 5b is an equivalent circuit diagram; Fig. 5a is a circuit diagram showing a configuration example in which the present invention is implemented in a single-pole double-throw termination type changeover switch; Fig. 5b is an equivalent circuit diagram thereof. It is a circuit diagram. 1...first high frequency signal input/output terminal (port 1),
2...Second high frequency signal input/output terminal (port 2),
3...Control voltage input terminal, 4 and 15...Switch
FET, 5... Termination control voltage input terminal, 6 and 7...
Termination control FET, 8...Gate switch control voltage input terminal, 9 and 16...Gate switch FET, 1
0, 11 and 17... Termination FET, 12... Third high frequency signal input/output terminal (port 3), 13 and 14
...Control voltage input terminal.

Claims (1)

[Claims] 1. Switching connections between a plurality of input/output ports using one or more gallium arsenide field effect transistors by utilizing the fact that the channel resistance of a gallium arsenide field effect transistor changes depending on the voltage applied to the gate. The method is configured to use a field effect transistor, and
A high frequency switch comprising circuit means for high frequency grounding of a gate of the gallium arsenide field effect transistor only when the gallium arsenide field effect transistor is in an off state. 2 Using the fact that the channel resistance of a gallium arsenide field effect transistor changes depending on the voltage applied to the gate, connection switching between multiple input/output ports can be performed using one or more gallium arsenide field effect transistors. and configure it to do so.
An open port that is not connected to other ports uses a gallium arsenide field effect transistor whose drain electrode is connected to the open port, whose source electrode is grounded, and whose channel resistance is approximately equal to the impedance of the transmission line on the open port side. High frequency switch terminated with