JP2006228065A5 - - Google Patents

Download PDF

Info

Publication number
JP2006228065A5
JP2006228065A5 JP2005043143A JP2005043143A JP2006228065A5 JP 2006228065 A5 JP2006228065 A5 JP 2006228065A5 JP 2005043143 A JP2005043143 A JP 2005043143A JP 2005043143 A JP2005043143 A JP 2005043143A JP 2006228065 A5 JP2006228065 A5 JP 2006228065A5
Authority
JP
Japan
Prior art keywords
property
logical system
list
verification
generating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2005043143A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006228065A (ja
JP4498167B2 (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP2005043143A priority Critical patent/JP4498167B2/ja
Priority claimed from JP2005043143A external-priority patent/JP4498167B2/ja
Priority to US11/354,474 priority patent/US20060190234A1/en
Publication of JP2006228065A publication Critical patent/JP2006228065A/ja
Publication of JP2006228065A5 publication Critical patent/JP2006228065A5/ja
Application granted granted Critical
Publication of JP4498167B2 publication Critical patent/JP4498167B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP2005043143A 2005-02-18 2005-02-18 プロパティ生成方法、検証方法及び検証装置 Expired - Fee Related JP4498167B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2005043143A JP4498167B2 (ja) 2005-02-18 2005-02-18 プロパティ生成方法、検証方法及び検証装置
US11/354,474 US20060190234A1 (en) 2005-02-18 2006-02-14 Property generating method, verification method and verification apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005043143A JP4498167B2 (ja) 2005-02-18 2005-02-18 プロパティ生成方法、検証方法及び検証装置

Publications (3)

Publication Number Publication Date
JP2006228065A JP2006228065A (ja) 2006-08-31
JP2006228065A5 true JP2006228065A5 (enExample) 2008-04-03
JP4498167B2 JP4498167B2 (ja) 2010-07-07

Family

ID=36913900

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005043143A Expired - Fee Related JP4498167B2 (ja) 2005-02-18 2005-02-18 プロパティ生成方法、検証方法及び検証装置

Country Status (2)

Country Link
US (1) US20060190234A1 (enExample)
JP (1) JP4498167B2 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5233354B2 (ja) * 2008-03-25 2013-07-10 日本電気株式会社 プロパティ検証システム、プロパティ検証方法、及びプログラム
JP5233355B2 (ja) * 2008-03-25 2013-07-10 日本電気株式会社 プロパティ生成システムおよびプロパティ検証システム
JP5228794B2 (ja) * 2008-10-27 2013-07-03 富士通株式会社 モデル検査実施のための環境生成支援装置、環境生成支援方法、環境生成支援プログラム
US20100235803A1 (en) * 2009-03-16 2010-09-16 Lara Gramark Method and Apparatus for Automatically Connecting Component Interfaces in a Model Description
JP5212264B2 (ja) * 2009-06-02 2013-06-19 富士通株式会社 プロパティ修正プログラム、プロパティ修正装置、およびプロパティ修正方法
JP5304470B2 (ja) * 2009-06-22 2013-10-02 富士通株式会社 モデル検査プログラム、モデル検査方法、モデル検査装置
JP2011186817A (ja) * 2010-03-09 2011-09-22 Toshiba Corp 論理検証装置及び論理検証方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5633813A (en) * 1994-05-04 1997-05-27 Srinivasan; Seshan R. Apparatus and method for automatic test generation and fault simulation of electronic circuits, based on programmable logic circuits
US5913023A (en) * 1997-06-30 1999-06-15 Siemens Corporate Research, Inc. Method for automated generation of tests for software
JPH1185828A (ja) * 1997-09-11 1999-03-30 Toshiba Corp 順序回路機能検証方法および順序回路機能検証システム
US5999717A (en) * 1997-12-31 1999-12-07 Motorola, Inc. Method for performing model checking in integrated circuit design
JP3663067B2 (ja) * 1998-12-17 2005-06-22 富士通株式会社 論理装置の検証方法、検証装置及び記録媒体
JP3941336B2 (ja) * 2000-05-11 2007-07-04 富士通株式会社 論理回路検証装置
US7272752B2 (en) * 2001-09-05 2007-09-18 International Business Machines Corporation Method and system for integrating test coverage measurements with model based test generation

Similar Documents

Publication Publication Date Title
WO2009110725A3 (ko) 3차원 응용프로그램 프레임워크 구조 및 이를 기반으로 하는 응용프로그램 구현 방법과, 3차원 응용소프트웨어 프레임워크 기반의 자동 테스트 시스템 및 그 방법
DE602007001443D1 (de) Herstellerdiagrammorientierter programmierungsrahmen mit szenariounterstützung
JP2012518837A5 (enExample)
WO2010045569A3 (en) Interactive design environments to visually model, debug and execute resource oriented programs
WO2008049035A3 (en) Method and system for delivering and executing best practices in oilfield development projects
WO2007120845A3 (en) Method and system for simulating state retention of an rtl design
WO2007084760A3 (en) Identifying design issues in electronic forms
WO2009021100A3 (en) Rcs signature generation for closely spaced multiple objects using n-point models
WO2008093224A3 (en) A system, method and software application for the generation of verification programs
WO2008021777A3 (en) Formal verification of graphical programs
JP2014510967A5 (enExample)
WO2007112162A3 (en) Selective instruction breakpoint generation
Salamah et al. Validated templates for specification of complex LTL formulas
JP2006228065A5 (enExample)
JP2006323500A5 (enExample)
Croes Virtual sensing in mechatronic systems. state estimation using system level models
TW200706220A (en) Data structure, data structure generation program, data structure generation method for image object expression, image software development device, image processing program, image processing method, image processing device, and recording medium
TW200634904A (en) Model-based pre-assembly testing of multi-component production devices
Zhu et al. Development of omni-directional correlation functions for nonlinear model validation
Guo et al. Response surface method and its experimental design for deterministic computer simulation
Hu et al. Checking component-based designs for scenario-based specifications
JP2007012053A5 (enExample)
Salehi et al. Modeling of turbojet fuel control unit using NARX-neural network
LEI Model-driven timing analysis of embedded software
Suzuki et al. Identification technique for nonlinear boundary conditions of a circular plate