JP2006216811A - Multilayer circuit wiring board and bga-type semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer circuit wiring board having a small stress to an interlayer connection via in that via holes for the interlayer connection are formed on the both sides of an insulating layer through the insulating layer, and to provide a BGA-type semiconductor device. <P>SOLUTION: The multilayer circuit wiring board comprises the via holes 41, 51 for the interlayer connection formed on the both sides of the insulating layer 10 through the insulating layers 20, 30. When a film thickness of the layer 10 is assumed as t, and the diameters of the via holes 41, 51 for interlayer connection are assumes as V<SB>D</SB>, there is a relationship of t<V<SB>D</SB>. When the diameters of the via holes 41, 51 are assumes as V<SB>D</SB>, and a distance between a central axis of the via hole 41 and a central axis of the via hole 51 is assumed as V<SB>C</SB>, there is a relationship of V<SB>C</SB>>2V<SB>D</SB>. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a BGA type semiconductor device in which a multilayer circuit wiring board, a semiconductor chip, and the like on which an indirect layer via and a wiring layer are formed on both surfaces of an insulating layer are mounted.

  In recent years, semiconductor devices such as semiconductor large-scale integrated circuits (LSIs) whose operating speed reaches 1 GHz in clock frequency have appeared. In such a high-speed semiconductor device, the degree of integration of transistors is high, and as a result, the number of input / output terminals may exceed several thousand.

In order to mount such a multi-terminal semiconductor element on a printed wiring board, a multilayer circuit wiring board is disposed between the semiconductor element and the printed board, and serves as a bridge for electrical connection between them.
The multilayer circuit wiring board has a wiring pattern having a very thin layer structure and fine lines and spaces than the printed wiring board in order to cope with bonding with terminals of highly dense semiconductor elements.
Examples of multilayer circuit wiring boards that are currently in wide use include BGA (Ball Grid Array) and CSP (Chip Size Package).

  Recently, in order to respond to the demand for higher density mounting and higher operating frequency, a multilayer circuit wiring board is manufactured by forming a wiring pattern and a layer indirect group via on a polyimide resin film, etc. In addition to reducing the thickness of the entire circuit wiring board, the one corresponding to the high frequency has also been developed by shortening the connection length of the indirect layer via.

  In order to produce such a thin multilayer circuit wiring board, the wiring layer and the insulating layer are made thin, and as one of the problems of such a multilayer circuit wiring board, the overall thickness is Since it is thin, warping may occur easily. Therefore, an auxiliary board called a stiffener is attached to the multilayer circuit wiring board to prevent warping of the multilayer circuit wiring board.

FIG. 2 shows an example of a BGA type semiconductor device in which a semiconductor chip or the like is mounted on a multilayer circuit wiring board.
In general, a semiconductor chip 110, a stiffener 131, and a lid 141 are mounted on the upper surface of the multilayer circuit wiring board 100, and a large number of solder balls 121 are mounted in an array on the lower surface.
In this state, it is finally mounted on a printed wiring board (not shown) via a solder ball.
The upper side of the multilayer circuit wiring board 100 is connected to metal and silicon parts, while the lower side is connected to resin parts. There is always a difference in coefficient of thermal expansion between the upper and lower sides, and the shape differs between when the semiconductor chip is operating and when it is stopped.

That is, the multilayer circuit wiring board is subjected to deformation such as compression, tension, and shear according to the temperature change. It is known that stress is generated in the wiring pattern inside the multilayer circuit wiring board due to such deformation (see, for example, Patent Document 1).
In this case, stress tends to concentrate on the layer indirect belonging vias that are responsible for the electrical connection between the layers of the wiring pattern. This is a problem in terms of circuit connection reliability. In particular, in a multilayer circuit wiring board, there is no problem in a via in which layer indirect genus vias are sufficiently separated from each other, and there may be a problem in a location where layer indirect genus vias are close to each other.
Japanese Patent Laid-Open No. 09-819579

The number of terminals of a semiconductor chip depends on the chip size, but usually reaches several thousand. Therefore, the same number of indirect layer vias exists in each layer. The presence of adjacent layer indirect genus vias is a problem that cannot be ignored. This seems to become more prominent as the connection length of the layer indirect genus via becomes shorter.
The present invention has been devised in view of the above problems, and in a multilayer circuit wiring board in which an indirect layer via is formed on both sides of an insulating layer via an insulating layer, stress on the layer indirect group via is provided. An object of the present invention is to provide a multilayer circuit wiring board and a BGA type semiconductor device with low concentration.

In order to achieve the above object in the present invention, first, in claim 1, layer indirect metal vias 41 and 51 are formed on both surfaces of the insulating layer 10 via the insulating layer 20 and the insulating layer 30. A multilayer circuit wiring board, wherein the thickness of the insulating layer 10 is t, and the diameters of the layer indirect genus vias 41 and 51 are V _D.
The multilayer circuit wiring board is characterized in that the relationship t <V _D is satisfied.

Further, in claim 2, when the diameter of the layer indirect genus vias 41 and 51 is V _D , and the distance between the central axes of the layer indirect genus via 41 and the layer indirect genus via 51 is V _C ,
2. The multilayer circuit wiring board according to claim 1, wherein a relationship of V _C > 2V _D is satisfied.

  Furthermore, a third aspect of the present invention is a BGA type semiconductor device characterized in that a semiconductor device is manufactured by mounting a semiconductor chip or the like using the multilayer circuit wiring board according to the first or second aspect. .

In the multilayer circuit wiring board of the present invention, the thickness t of the insulating layer 10 and the diameter V _{D of} the layer indirect attribute vias 41 and 51 satisfy the relationship of t <V _D , and the layer indirect attribute is used. the diameter of the V _D of the via 41 and 51, a layer of indirect genus vias 21 and the layer indirectly genus vias 31 between the centers axes distance and V _C V _C> 2V _D the relationship is satisfied, so that the insulating layer 10 Since the film thickness t and the center axis distance V _C between the layer indirect genus via 21 and the layer indirect genus via 31 are set, even if a thermal shock such as a temperature cycle is applied, the adjacent layer indirect genus Via interaction is reduced and stress in the wiring layer is relaxed.
Furthermore, a reliable BGA type semiconductor device can be provided by mounting a semiconductor chip or the like on the multilayer circuit wiring board of the present invention.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a schematic partial sectional view showing an embodiment of a multilayer circuit wiring board according to the present invention.
The multilayer circuit wiring board 100 of the present invention comprises a resin film 21 and an adhesive layer 22 on a double-sided wiring board in which wiring layers 11a and 12a and ground layers 11b and 12b are formed on both sides of an insulating layer 10 made of polyimide film or the like. The IC pad 42 is formed through the insulating layer 20, and the BGA pad 52 is formed through the insulating layer 30 composed of the resin film 31 and the adhesive layer 32. The IC pad 42 and the wiring layer 11 a are connected to the layer indirect group via 41. Thus, the BGA pad 52 and the wiring layer 12a are electrically connected to each other through the layer-indirectly assigned via 51, and are four-layer circuit wiring boards in which solder resist layers 61 and 62 are formed on the outermost layer.
Here, the insulating layer 10 is a polyimide film, a liquid crystal polymer film, a glass epoxy film, the resin films 21 and 31 are a polyimide film, a liquid crystal polymer film, etc., and the adhesive layer 21 and the layer 32 are an epoxy resin and a polyimide. Examples thereof include resins.

In the invention according to claim 1, in the multilayer circuit wiring board 100, when the film thickness of the insulating layer 10 is t and the diameters of the layer indirect metal vias 41 and 51 are V _D , there is a relationship of t <V _D. It is intended to be satisfied.
In response to recent increases in speed, density, and thickness, the insulating layer 20 and the insulating layer 30 take into consideration the reduction in the thickness of the conductor layer, the shortening of the connection length of the indirect layer vias 41 and 51, and the insulation. Thus, the thickness is set appropriately, but the thickness t of the insulating layer 10 is made smaller than the diameter V _D of the layer indirect metal vias 41 and 51.
One is to shorten the connection length. The other is that if the insulating layer 10 is thick, the stress generated in the via is determined by the positional relationship between the via and the insulating layer, and is not related to the position of the opposing via.

In the invention according to claim 2, in the multilayer circuit wiring board 100, the diameter of the layer indirect genus vias 41 and 51 is V _D , and the distance between the central axes of the layer indirect genus via 41 and the layer indirect genus via 51 is set. When V _C is set, the distance between the central axes of the adjacent layer indirect metal vias is limited so that the relationship of V _C > 2V _D is satisfied.
By separating the center axis distance V _C between the layer indirect genus via 41 and the layer indirect genus via 51 by at least twice the diameter V _D of the layer indirect genus vias 41 and 51, a thermal shock such as a temperature cycle is generated in the multilayer circuit. This is because even if it is added to the wiring board 100, the interaction between the adjacent layer indirect genus via 41 and the layer indirect genus via 51 decreases, and the stress of the wiring layer is relieved.

FIG. 2 is a schematic partial sectional view showing an embodiment of the BGA type semiconductor device of the present invention.
The BGA type semiconductor device 200 of the present invention is obtained by mounting the semiconductor chip 110, the stiffener 131 and the lid 141 on one surface of the multilayer circuit wiring board 100 of the present invention, and the solder ball 121 on the other surface.

Embodiments of the multilayer circuit wiring board of the present invention will be described below with reference to the drawings.
FIGS. 3A to 3E and FIGS. 4F to 4H are schematic configuration cross-sectional views illustrating an example of a method for manufacturing a multilayer circuit wiring board according to the present invention in the order of steps.
First, a laminated base material in which conductor layers 11 and 12 were formed by laminating a copper foil having a thickness of 12 μm on both surfaces of an insulating layer 10 made of a polyimide film having a thickness of 25.4 μm was prepared (see FIG. 3A). .

  Next, a photosensitive layer is formed by laminating a photosensitive dry film on the conductor layers 11 and 12, and a series of patterning processes such as pattern exposure and development are performed to form a resist pattern. The conductor layers 11 and 12 are etched using the mask, the resist pattern is peeled off, the wiring layer 11a and the ground layer 12b are formed on one surface of the insulating layer 10, and the wiring layer 12a and the ground layer are formed on the other surface. 12b was formed (see FIG. 3B).

  Next, a 5 μm thick adhesive layer 22 made of an epoxy resin is applied to a 13 μm thick resin film 21 made of a polyimide film, and a 5 μm thick epoxy resin is made to a 13 μm thick resin film 31 made of a polyimide film. The resin film with an adhesive layer on which the adhesive layer 32 is formed is laminated on both surfaces of the insulating layer 10 on which the wiring layers 11a and 12a and the ground layers 11b and 12b are formed (see FIG. 3C). An insulating layer 20 and an insulating layer 30 were formed on the substrate (see FIG. 3D).

Next, the via holes 23 and the via holes 33 were formed by drilling predetermined positions of the insulating layer 20 and the insulating layer 30 by laser processing using a UV laser. Further, the via hole 23 and the via hole 33 are subjected to desmear treatment, and electroless copper plating is performed on the insulating layer 20 and the insulating layer 30 in the via hole 23 and the via hole 33 to form a plating base conductive layer (particularly, (Not shown) was formed (see FIG. 3E).

  Next, a photosensitive layer is formed by a method such as laminating a photosensitive dry film, and a series of patterning processes such as pattern exposure and development are performed to form a resist pattern 71 for pattern plating on the insulating layer 20. A resist pattern 72 for pattern plating was formed on 30 (see FIG. 4F).

  Next, electrolytic copper plating is performed using the plating base conductive layer as a power feeding layer, a conductor layer is formed in the via holes 23 and 33 and on the insulating layers 20 and 30, and the resist patterns 71 and 72 are formed with a dedicated stripping solution. The plating underlying conductive layer under the resist patterns 71 and 72 is removed by quick etching, and a layer indirect metal via 41 and an IC pad 42 having a diameter of 50 μmφ are formed at predetermined positions of the insulating layer 20. A layer indirect genus via 51 and a BGA pad 52 having a diameter of 50 μmφ were formed at the positions (see FIG. 4G).

Finally, the solder resist layers 61 and 62 are formed by screen printing, and the indirect layer vias 42 and 51 are formed on both surfaces of the insulating layer 10 via the insulating layers 20 and 30. A wiring board 100 was obtained.
Here, the center axis distance V _C between the layer indirect genus via 41 and the layer indirect genus via 51 was 120 μm.

A multilayer circuit wiring board is manufactured in the same process as in the first embodiment, and the multilayer circuit wiring board 300 of Comparative Example 1 is obtained in which the center axis distance V _C between the layer indirect genus via 41 and the layer indirect genus via 51 is 40 μm. It was.

A multilayer circuit wiring board is produced in the same process as in the first embodiment, and the multilayer circuit wiring board 400 of Comparative Example 2 is obtained in which the center axis distance V _C between the layer indirect genus via 41 and the layer indirect genus via 51 is 80 μm. It was.

  Temperature cycle tests of the multilayer circuit wiring board 100, the multilayer circuit wiring board 300, and the multilayer circuit wiring board 400 obtained in Examples 1 to 3 were performed, and the number of cycles until disconnection was recorded. The temperature change to be applied was a low temperature of −40 ° C. and a high temperature of 125 ° C., each temperature being maintained for 30 minutes, and the time required for the temperature change from the low temperature to the high temperature and from the high temperature to the low temperature was 5 minutes. The temperature cycle test was conducted up to 1200 times. The results are shown in Table 1.

表１に示すように、層間接属用ビア４１と層間接属用ビア５１の中心軸間距離Ｖ_Cが層間接属用ビアの直径の二倍（１００μｍ）以上離れれば温度サイクル１０００回を上回ることが確認された。

As shown in Table 1, if the center axis distance V _C between the layer indirect genus via 41 and the layer indirect genus via 51 is more than twice the diameter of the layer indirect genus via (100 μm), the temperature cycle exceeds 1000 times. It was confirmed.

1 is a schematic cross-sectional view showing an embodiment of a multilayer circuit wiring board according to the present invention. 1 is a schematic cross-sectional view showing an embodiment of a semiconductor device of the present invention. (A)-(e) is typical structure sectional drawing which shows a part of process in the manufacturing method of the multilayer circuit wiring board of this invention. (F)-(h) is typical structure sectional drawing which shows a part of process in the manufacturing method of the multilayer circuit wiring board of this invention.

Explanation of symbols

10, 20, 30 ... Insulating layers 11, 12 ... Conductor layers 11a, 12a ... Wiring layers 11b, 12b ... Ground layers 21, 31 ... Resin films 22, 32 ... Adhesive layers 23, 33 ... Vias Hole 41, 51 ... interlayer connection via 42 ... IC pad 52 ... BGA pad 61, 62 ... solder resist layer 71, 72 ... resist pattern 100, 300, 400 ... multilayer circuit wiring board 110 ... Semiconductor chip 121 …… Solder ball 131 …… Stiffener 141 …… Lid 200 …… Semiconductor device

Claims (3)

A multilayer circuit wiring board in which vias (41) and (51) for indirectly connecting layers are formed on both surfaces of an insulating layer (10) via an insulating layer (20) and an insulating layer (30), the insulating layer When the thickness of (10) is t and the diameter of the layer indirect genus vias (41) and (51) is V _D ,
A multilayer circuit wiring board characterized by satisfying a relationship of t <V _D. When the diameter of the layer indirect genus vias (41) and (51) is V _D , and the distance between the central axes of the layer indirect genus via (41) and the layer indirect genus via (51) is V _C ,
2. The multilayer circuit wiring board according to claim 1, wherein a relationship of V _C > 2V _D is satisfied.   A BGA type semiconductor device, wherein a semiconductor device or the like is mounted by using the multilayer circuit wiring board according to claim 1 or 2 to produce a semiconductor device.

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