JP2006216688A - Solid-state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a sufficient image characteristic in a CMOS sensor that uses an n-type substrate. <P>SOLUTION: An embedded photodiode 14 and a p-type well region 15 are formed in the surface region of a surface part 11b of the n-type substrate 11. Respective gates 17, 18 and 19 of a scanning transistor are installed on the surface of the p-type well region 15. N-type diffusion layers 20a, 20b, 20c and 20d are formed in the surface region of the p-type well region 15, other than the respective gates 17, 18 and 19. A reading gate 21 is installed on the n-type substrate 11 between the embedded photodiode 14 and the p-type well region 15. A p-type diffusion layer 22 is formed in the surface 11b of the n-type substrate 11, which corresponds to a detector 31 between the p-type well region 15 and the reading gate 21. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device, and in particular, a CMOS (Complementary Metal Oxide Semiconductor) in which a plurality of unit cells including a photoelectric conversion unit and a signal scanning unit are two-dimensionally arranged on an N-type semiconductor substrate. ) Regarding the sensor.

  In recent years, a solid-state imaging device using an N-type substrate characterized by the use of a single power source and low-voltage driving has been proposed (see, for example, Patent Document 1). When an N-type substrate is employed, there is an advantage that an image characteristic can be improved by suppressing a phenomenon called blooming in which electric charge leaks into peripheral pixels (unit cells).

  However, when an N-type substrate is employed in the CMOS sensor, there are the following problems.

  (1) The formation of a pixel region on an N-type substrate may cause charge leakage when storing signals in the case of a CMOS sensor such as a CCD (Charge Coupled Device) that is difficult to use with a high voltage drive and multiple power sources. Alternatively, charge may be left behind when signals are read out, causing an afterimage.

(2) A P-type well such as a peripheral circuit must be formed in the pixel region, and the area of the signal storage region (photoelectric conversion unit) decreases as the pixel becomes finer, and the saturation signal decreases. Then, noise such as optical shot noise becomes larger than the signal, and S / N (Signal to Noise) is deteriorated.
JP 2000-150848 A

  The present invention has been made to solve the above-described problems, and even when an N-type substrate is used, signal leakage and afterimage can be prevented and deterioration of S / N due to miniaturization can be reduced. An object of the present invention is to provide a solid-state imaging device capable of improving image characteristics.

  According to one aspect of the present invention, an N-type semiconductor substrate, a P-type semiconductor region that separates a bottom portion and a surface portion of the N-type semiconductor substrate, and a surface portion of the N-type semiconductor substrate, A photoelectric conversion unit selectively formed in a surface region; and a signal scanning unit provided on the surface region of the surface portion of the N-type semiconductor substrate and spaced apart from the photoelectric conversion unit by a predetermined distance; A readout electrode formed on the surface portion of the N-type semiconductor substrate between the signal scanning unit and the photoelectric conversion unit, and for reading out a signal photoelectrically converted by the photoelectric conversion unit to the signal scanning unit; And a P-type diffusion layer region selectively provided on the surface portion of the N-type semiconductor substrate between the readout electrode and the signal scanning unit. Is done.

  With the above configuration, leakage of signals and afterimages can be prevented even when an N-type substrate is used, such as leakage of charges during signal accumulation and elimination of charges remaining during signal readout. Therefore, it is possible to provide a solid-state imaging device capable of reducing the deterioration of S / N due to the increase in image quality and improving the image characteristics.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
1 and 2 show a basic configuration of a CMOS sensor (solid-state imaging device) according to the first embodiment of the present invention. 1 is a plan view, and FIG. 2 is a cross-sectional view taken along the line IIB-IIB in FIG. 1, showing one pixel (unit cell) as an example.

  As shown in the figure, an N-type substrate (N-type semiconductor substrate) 11 is separated into a bottom portion 11a and a surface portion 11b by a P layer (P-type semiconductor region) 12. An element isolation region 13 is selectively formed in the surface region of the surface portion 11 b of the N-type substrate 11.

  An activation region defined by the element isolation region 13, that is, a surface region of the surface portion 11 b of the N-type substrate 11 excluding the element isolation region 13, is a buried photodiode (signal storage region) serving as a photoelectric conversion unit. 14 and a P-type well region 15 for forming a scanning transistor to be a signal scanning portion. A surface shield layer 16 is formed on the surface of the embedded photodiode 14.

  The P-type well region 15 is provided a predetermined distance away from the embedded photodiode 14. Further, on the surface of the P-type well region 15 (the surface portion 11b of the N-type substrate 11 corresponding to the P-type well region 15), for example, a gate 17 of a reset transistor, an amplifying transistor, which are scanning transistors. The gate 18 and the gate 19 of the selection transistor are provided via an insulating film (both not shown). N-type diffusion layers 20a, 20b, 20c, and 20d serving as source / drains are formed in the surface region of the P-type well region 15 excluding the gates 17, 18, and 19, respectively.

  On the surface portion 11b of the N-type substrate 11 corresponding to the space between the embedded photodiode 14 and the P-type well region 15, a read-out signal for reading out signal charges photoelectrically converted by the embedded photodiode 14 is provided. A gate (readout electrode) 21 is provided. The read gate 21 is formed so that one end thereof substantially coincides with one end surface of the embedded photodiode 14 or extends on one end of the embedded photodiode 14.

A P-type diffusion layer (P-type diffusion region) 22 is formed on the surface portion 11 b of the N-type substrate 11 corresponding to the space between the P-type well region 15 and the readout gate 21. . The impurity concentration of the P-type diffusion layer 22 is set to, for example, 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ . The P-type diffusion layer 22 functions as a punch-through stopper for preventing signal off-leakage.

  In the present embodiment, among the plurality of N-type diffusion layers 20a, 20b, 20c, and 20d, an N-type diffusion layer 20a provided between the gate 17 of the reset transistor and the read gate 21 is, for example, The N-type substrate 11 is formed so as to extend to the surface region of the surface portion 11 b and to be close to the read gate 21. That is, between the gate 17 of the reset transistor and the read gate 21, the N region relative to the surface region of the P-type well region 15 and the surface region of the surface portion 11 b of the N-type substrate 11. A mold diffusion layer 20a is formed. Thus, a detection unit 31 for detecting the signal charge read by the read gate 21 is configured. The P-type diffusion layer 22 is formed to correspond to at least the lower surface portion of the N-type diffusion layer 20 a corresponding to the surface portion 11 b of the N-type substrate 11.

  The N-type diffusion layer 20a has a wiring 23 connected to the gate 18 of the amplifying transistor, the N-type diffusion layer 20b has a drain line 24, the N-type diffusion layer 20d has a signal line 25, respectively. It is connected.

  In practice, the unit cells having such a configuration are two-dimensionally arranged to realize a pixel region of the CMOS sensor.

  According to the configuration of the present embodiment, the P-type diffusion layer 22 covering the source (N-type diffusion layer 20a) of the resetting transistor is formed on the drain side of the read gate 21, so that the embedded photodiode 14 is stored during signal accumulation. Therefore, it is possible to prevent the signal charge from leaking to the detection unit 31. Moreover, the P-type diffusion layer 22 does not completely cover the N-type diffusion layer 20a. That is, the P-type diffusion layer 22 is formed on the lower surface of the N-type diffusion layer 20a so that the channel-side surface of the N-type diffusion layer 20a is exposed. Since the diffusion layer 22 is formed, good image characteristics can be obtained even when the N-type substrate 11 is employed in a CMOS sensor characterized by the use of a single power supply and low-voltage driving. Become.

  The P-type diffusion layer 22 is not limited to being formed only on the lower surface portion of the N-type diffusion layer 20 a corresponding to the surface portion 11 b of the N-type substrate 11, but the surface portion 11 b of the N-type substrate 11. It is also possible to form it on the entire bottom surface of the N-type diffusion layer 20a corresponding to the P-type well region 15, respectively.

[Second Embodiment]
3 and 4 show the basic configuration of a CMOS sensor (solid-state imaging device) according to the second embodiment of the present invention. 3 is a plan view, and FIG. 4 is a cross-sectional view taken along line IVB-IVB in FIG. 3. The same parts as those in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof is omitted.

In the case of the second embodiment, the P-type diffusion layer 22 ′ applied to the detection unit 31 extends to just below the read gate 21 so as to cover the channel side surface of the N-type diffusion layer 20 a. It is to be formed. However, the impurity concentration of the P-type diffusion layer 22 ′ is thinner than that of the P-type diffusion layer 22 in the first embodiment, and is, for example, half of 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ . Set to degree.

  Even in such a configuration, since the impurity concentration of the P-type diffusion layer 22 ′ is reduced, the signal can be transferred without leaving the charge of the embedded photodiode 14 at the time of signal reading. As a result, no afterimage is generated. In addition, it is possible to prevent the S / N from deteriorating due to pixel miniaturization. Therefore, good image characteristics can be obtained in a CMOS sensor characterized by the use of a single power supply and low-voltage driving.

[Third Embodiment]
5 and 6 show the basic configuration of a CMOS sensor (solid-state imaging device) according to the third embodiment of the present invention. 5 is a plan view, and FIG. 6 is a sectional view taken along the line VIB-VIB in FIG. 5. The same parts as those in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof is omitted.

In the case of the third embodiment, the P-type diffusion layer (22) relating to the detection unit 31 is formed integrally with the P-type well region 15 ′. That is, the P-type well region 15 ′ is formed so that one end thereof is close to the read gate 21. However, the impurity concentration of the P-type well region 15 ′ is set to a condition that does not generate an afterimage when reading a signal, for example, 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ .

  Even with such a configuration, as in the case of the first and second embodiments described above, it is possible to obtain good image characteristics in a CMOS sensor characterized by the use of a single power source and low-voltage driving. Become. In addition, the process steps for forming the P-type diffusion layers (22, 22 ') as in the first and second embodiments are not required.

  In addition, the present invention is not limited to the above (each) embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage. Further, the above (each) embodiment includes various stages of the invention, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if several constituent requirements are deleted from all the constituent requirements shown in the (each) embodiment, the problem (at least one) described in the column of the problem to be solved by the invention can be solved. When the effect (at least one of the effects) described in the “Effect” column is obtained, a configuration from which the constituent requirements are deleted can be extracted as an invention.

1 is a plan view showing a basic configuration of a CMOS sensor according to a first embodiment of the present invention. Sectional drawing of the CMOS sensor shown in FIG. The top view which shows the basic composition of a CMOS sensor according to the 2nd Embodiment of this invention. Sectional drawing of the CMOS sensor shown in FIG. The top view which shows the basic composition of a CMOS sensor according to the 3rd Embodiment of this invention. Sectional drawing of the CMOS sensor shown in FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... N type board | substrate, 11a ... Bottom part, 11b ... Surface part, 12 ... P layer, 13 ... Element isolation region, 14 ... Embedded photodiode, 15, 15 '... P type well region, 16 ... Surface shield layer, 17 ... Reset transistor gate, 18 ... amplification transistor gate, 19 ... selection transistor gate, 20a, 20b, 20c, 20d ... N-type diffusion layer, 21 ... readout gate, 22,22 '... P-type diffusion layer , 23... Wiring, 24... Drain line, 25... Signal line, 31.

Claims (5)

An N-type semiconductor substrate;
A P-type semiconductor region that separates a bottom portion and a surface portion of the N-type semiconductor substrate;
A photoelectric conversion part selectively formed in the surface region of the surface part of the N-type semiconductor substrate;
A signal scanning unit provided on a surface region of the surface portion of the N-type semiconductor substrate at a predetermined distance from the photoelectric conversion unit;
A readout electrode formed on the surface portion of the N-type semiconductor substrate between the signal scanning unit and the photoelectric conversion unit, and for reading out a signal photoelectrically converted by the photoelectric conversion unit to the signal scanning unit; ,
A solid-state imaging device, comprising: a P-type diffusion layer region selectively provided on a surface portion of the N-type semiconductor substrate between the readout electrode and the signal scanning unit. 2. The solid-state imaging device according to claim 1, wherein an impurity concentration of the P-type diffusion layer region is set to 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ . The P-type diffusion layer region is further provided so as to extend below the readout electrode, and its impurity concentration is set to about half of 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁷ cm ^−3. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is provided.   The solid-state imaging device according to claim 1, wherein the P-type diffusion layer region is formed integrally with a well region constituting the signal scanning unit. 5. The solid-state imaging device according to claim 4, wherein an impurity concentration of the well region is set to 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ .

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