JP2005317875A - Solid-state image sensing device - Google Patents

Solid-state image sensing device Download PDF

Info

Publication number
JP2005317875A
JP2005317875A JP2004136584A JP2004136584A JP2005317875A JP 2005317875 A JP2005317875 A JP 2005317875A JP 2004136584 A JP2004136584 A JP 2004136584A JP 2004136584 A JP2004136584 A JP 2004136584A JP 2005317875 A JP2005317875 A JP 2005317875A
Authority
JP
Japan
Prior art keywords
signal storage
well
drain region
gate electrode
storage unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004136584A
Other languages
Japanese (ja)
Inventor
Tetsuya Yamaguchi
鉄也 山口
Hiroshige Goto
浩成 後藤
Masayuki Ayabe
昌之 綾部
Hisanori Ihara
久典 井原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2004136584A priority Critical patent/JP2005317875A/en
Priority to US11/095,592 priority patent/US7259412B2/en
Priority to CNB200510066870XA priority patent/CN100438055C/en
Publication of JP2005317875A publication Critical patent/JP2005317875A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Light Receiving Elements (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To make an improvement in the sensibility of a photo-diode and the stable operation of an element compatible. <P>SOLUTION: A first storage 41 and a second storage 42 constituting the photo-diode and being composed of n-type diffusion layers converting a light into charges and storing them are formed in a p-type substrate/well 20. The first storage 41 is separated and arranged at one end on the reverse side to the gate electrode 34 of a drain region 35 and formed near the surface of the p-type substrate/well 20. The second storage 42 is connected and formed to the p-type substrate/well 20 in the lower section of the drain region 35 of an adjacent first picture element 30 and to the first storage 41 for its own picture element 40. A gate electrode 44 is formed through a gate insulating film 43 on the p-type substrate/well 20 while being adjoined at one end different from the drain region 35 side of the first storage 41. The drain region 45 composed of the n-type diffusion layer is formed to the surface section of the p-type substrate/well 20 on the reverse side to the first storage 41 side of the gate electrode 44. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、固体撮像装置に係わり、特に感度の向上を図った固体撮像装置に関する。   The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device with improved sensitivity.

撮像装置として所謂ＣＭＯＳセンサが有る。ＣＭＯＳセンサは、光電変換部（フォトダイオード）、光電変換部の信号を読み出す読出しトランジスタ、信号電荷をリセットするリセットトランジスタ、信号を増幅する増幅トランジスタ、ラインを選択する選択トランジスタからなる単位セルが配列されている。   There is a so-called CMOS sensor as an imaging device. The CMOS sensor has a unit cell composed of a photoelectric conversion unit (photodiode), a readout transistor that reads out signals from the photoelectric conversion unit, a reset transistor that resets signal charges, an amplification transistor that amplifies signals, and a selection transistor that selects a line. ing.

フォトダイオードの感度を上げるために、フォトダイオードを自画素（光が入射し、フォトダイオードで光電変換を行いその信号電荷を信号処理するＴｒを形成している画素領域）の検出部下部にまで拡げて形成する構造が、既に特許文献１に提案されている。   In order to increase the sensitivity of the photodiode, the photodiode is extended to the lower part of the detection part of the own pixel (the pixel area where light is incident and photoelectric conversion is performed by the photodiode to form a signal processing transistor for the signal charge). The structure formed in this way has already been proposed in Patent Document 1.

この場合、読み出しＴｒの下にフォトダイオードが形成されているため、読み出しトランジスタの動作を安定に行わせるためには、通常読み出しトランジスタの下にフォトダイオードと逆の導電型の半導体層を形成することが必要となる。もし、読み出しトランジスタの下にフォトダイオード（この場合は、Ｎ型半導体層）と逆の導電型半導体層（Ｐ型）を形成しないとフォトダイオードと検出部（フォトダイオードと同じ導電型半導体層：この場合Ｎ型層）が電気的に繋がる恐れが生じるためである。   In this case, since the photodiode is formed under the readout transistor, in order to stably operate the readout transistor, a semiconductor layer having a conductivity type opposite to that of the photodiode is usually formed under the readout transistor. Is required. If a conductive semiconductor layer (P-type) opposite to the photodiode (in this case, the N-type semiconductor layer) is not formed under the readout transistor, the photodiode and the detector (the same conductive semiconductor layer as the photodiode: this This is because the N-type layer in this case may be electrically connected.

しかしながら、前記の理由のため、読み出しトランジスタの下にフォトダイオードと逆の導電型半導体層（Ｐ型層：ＰＴＳ）を形成すると読み出しトランジスタの閾値を調整する必要が生じ、読み出しＴｒの動作マージンを狭くし、素子動作を不安定にする要因の一つになる。
特開２００３−２８２８５７ However, if the conductive semiconductor layer (P-type layer: PTS) opposite to the photodiode is formed under the read transistor for the above-described reason, it is necessary to adjust the threshold value of the read transistor, and the operation margin of the read Tr is narrowed. However, it becomes one of the factors that make the device operation unstable.
JP 2003-282857 A

上述したように、フォトダイオードの感度を上げるために、フォトダイオードを自画素の検出部下部に形成すると、素子動作を不安定にする。   As described above, if the photodiode is formed below the detection portion of its own pixel in order to increase the sensitivity of the photodiode, the device operation becomes unstable.

本発明の目的は、フォトダイオードの感度の向上と、素子の安定動作の両立を図り得る固体撮像装置を提供することにある。   An object of the present invention is to provide a solid-state imaging device capable of achieving both improvement in sensitivity of a photodiode and stable operation of an element.

本発明の一例に係わる固体撮像装置は、第１導電型の半導体基板又はウェルの表面近傍に形成され、光電変換して得られた信号電荷を蓄積する第２導電型の第１の信号蓄積部と、前記第１の信号蓄積部の一端に隣接して前記基板又はウェルの上部に設けられた第１のゲート電極と、この第１のゲート電極の前記第１の信号蓄積部側とは反対側の端に隣接して設けられた第２導電型の第１のドレイン領域と、第１導電型の半導体基板又はウェルの表面近傍に、第１のドレイン領域の前記ゲート電極側と反対側に離間して形成され、光電変換して得られた信号電荷を蓄積する第２導電型の第２の信号蓄積部と、第１導電型の半導体基板又はウェルの内部に、前記第１のドレイン領域の下方、且つ第２の信号蓄積部に接続して形成された第３の信号蓄積部と、前記第２の信号蓄積部の前記第１のドレイン領域側と反対側の端に隣接して前記半導体基板又はウェルの上部に設けられた第２のゲート電極と、この第２のゲート電極の前記第２の信号蓄積部側とは反対側の端に隣接して設けられた第２導電型の第２のドレイン領域とを具備してなることを特徴とする。   A solid-state imaging device according to an example of the present invention is formed in the vicinity of a surface of a first conductive type semiconductor substrate or well, and stores a signal charge obtained by photoelectric conversion, and a second conductive type first signal storage unit. And a first gate electrode provided on an upper portion of the substrate or well adjacent to one end of the first signal storage unit, and the first signal storage unit side of the first gate electrode is opposite A first conductivity type first drain region provided adjacent to the edge of the first conductivity type, in the vicinity of the surface of the first conductivity type semiconductor substrate or well, on the opposite side of the first drain region to the gate electrode side A second signal storage portion of a second conductivity type, which is formed separately and stores signal charges obtained by photoelectric conversion, and the first drain region inside the first conductivity type semiconductor substrate or well And a third signal formed by being connected to the second signal storage unit A second gate electrode provided on an upper portion of the semiconductor substrate or well, adjacent to an end of the second signal storage unit opposite to the first drain region side, and a second gate electrode And a second drain region of a second conductivity type provided adjacent to an end of the gate electrode opposite to the second signal storage portion side.

本発明によれば、信号蓄積部を隣接する画素の下方に形成して面積を大きくすることで、フォトダイオードの感度の向上と素子の安定動作の両立を図ることができる。   According to the present invention, it is possible to improve both the sensitivity of the photodiode and the stable operation of the element by forming the signal storage portion below the adjacent pixel to increase the area.

本発明の実施の形態を以下に図面を参照して説明する。   Embodiments of the present invention will be described below with reference to the drawings.

図１は、本発明の一実施形態に係わるＭＯＳイメージセンサを示す回路構成図である。   FIG. 1 is a circuit configuration diagram showing a MOS image sensor according to an embodiment of the present invention.

光電変換のためのフォトダイオード（光電変換部）１、その信号電荷を読み出す読み出しトランジスタ２、読み出した信号電荷を増幅する増幅トランジスタ３、信号を読み出すラインを選択する垂直選択トランジスタ４、信号電荷をリセットするリセットトランジスタ５からなる単位セル１５が、二次元状に配列されている。なお、実際にはこれより多くの単位セルが配列される。   A photodiode (photoelectric conversion unit) 1 for photoelectric conversion, a read transistor 2 for reading the signal charge, an amplification transistor 3 for amplifying the read signal charge, a vertical selection transistor 4 for selecting a signal read line, and resetting the signal charge Unit cells 15 composed of reset transistors 5 are arranged two-dimensionally. Actually, more unit cells are arranged.

垂直シフトレジスタ６から水平方向に配線されている水平アドレス線７は垂直選択トランジスタ４のゲートに結線され、信号を読み出すラインを決めている。リセット線８はリセットトランジスタ５のゲートに結線されている。増幅トランジスタ３のソースは垂直信号線９に結線され、その一端には負荷トランジスタ１０が設けられている。垂直信号線９の他端は、水平シフトレジスタ１２から供給される選択パルスにより選択される水平選択トランジスタ１１を介して水平信号線１３に結線されている。   A horizontal address line 7 wired in the horizontal direction from the vertical shift register 6 is connected to the gate of the vertical selection transistor 4 to determine a line for reading a signal. The reset line 8 is connected to the gate of the reset transistor 5. The source of the amplification transistor 3 is connected to the vertical signal line 9, and a load transistor 10 is provided at one end thereof. The other end of the vertical signal line 9 is connected to the horizontal signal line 13 via a horizontal selection transistor 11 selected by a selection pulse supplied from the horizontal shift register 12.

回路的な構成は従来装置と基本的に同様であるが、本実施形態は以下に示す素子構造が従来装置とは異なっている。   The circuit configuration is basically the same as that of the conventional device, but this embodiment is different from the conventional device in the element structure shown below.

図２は、本発明の一実施形態に係わるＣＭＯＳイメージセンサの素子構造を示す図。図２（ａ）は平面図、図２（ｂ）は断面図である。この図では、１つの単位セル部分（１画素に１つのフォトダイオードを含み形成されている）におけるフォトダイオード及び信号読み出しトランジスタを示している。   FIG. 2 is a diagram showing an element structure of a CMOS image sensor according to an embodiment of the present invention. 2A is a plan view, and FIG. 2B is a cross-sectional view. This figure shows a photodiode and a signal readout transistor in one unit cell portion (formed by including one photodiode per pixel).

図２に示すように、本実施形態では、ｐ型のＳｉ基板又はｐウェル２０の内部に、フォトダイオードを構成する、光を電荷に変換して蓄積するｎ型拡散層からなる第１の信号蓄積部３１及び第２の信号蓄積部３２が設けられている。第１の信号蓄積部３１は、ｐ型基板／ウェル２０の表面近傍に形成されている。第２の信号蓄積部３２は、ｐ型基板／ウェル２０の内部、且つ第１の信号蓄積部３１に接続して形成されている。前記第１の信号蓄積部３１の一端に隣接してｐ型基板／ウェル２０上にゲート絶縁膜３３を介してゲート電極３４が設けられている。このゲート電極３４の信号蓄積部３１とは反対側のｐ型基板／ウェル２０の表面部にｎ型拡散層からなるドレイン領域３５が設けられている。以上が１画素を構成する第１の画素３０の構成である。   As shown in FIG. 2, in the present embodiment, a first signal composed of a p-type Si substrate or an n-type diffusion layer that constitutes a photodiode and converts light into electric charges and accumulates inside the p-type well 20. An accumulation unit 31 and a second signal accumulation unit 32 are provided. The first signal storage unit 31 is formed near the surface of the p-type substrate / well 20. The second signal storage unit 32 is formed inside the p-type substrate / well 20 and connected to the first signal storage unit 31. A gate electrode 34 is provided on the p-type substrate / well 20 through a gate insulating film 33 adjacent to one end of the first signal storage unit 31. A drain region 35 made of an n-type diffusion layer is provided on the surface portion of the p-type substrate / well 20 on the opposite side of the gate electrode 34 from the signal storage portion 31. The above is the configuration of the first pixel 30 configuring one pixel.

次に、第１の画素３０に隣接する第２の画素４０の構成について説明する。ｐ型基板／ウェル２０の内部に、フォトダイオードを構成する、光を電荷に変換して蓄積するｎ型拡散層からなる第１の信号蓄積部（第２の信号蓄積部）４１及び第２の信号蓄積部（第３の信号蓄積部）４２が設けられている。第１の信号蓄積部４１は、ドレイン領域３５のゲート電極３４型と反対側の一端に離間配置され、且つｐ型基板／ウェル２０の表面近傍に形成されている。第２の信号蓄積部４２は、隣接する第１の画素３０のドレイン領域３５の下方のｐ型基板／ウェル２０、且つ自画素４０の第１の信号蓄積部４１に接続して形成されている。第１の信号蓄積部４１のドレイン領域３５側と異なる一端に隣接して、ｐ型基板／ウェル２０上にゲート絶縁膜４３を介してゲート電極４４が設けられている。このゲート電極４４の第１の信号蓄積部４１側とは反対側のｐ型基板／ウェル２０の表面部にｎ型拡散層からなるドレイン領域４５が設けられている。以上が１画素を構成する第２の画素４０の構成である。第２の信号蓄積部４２のゲート電極４４の長手方向の長さは、第１の信号蓄積部４１のゲート電極４４の長手方向の長さより長く形成されている。   Next, the configuration of the second pixel 40 adjacent to the first pixel 30 will be described. Inside the p-type substrate / well 20, a first signal storage unit (second signal storage unit) 41 and a second signal storage unit 41 are formed of an n-type diffusion layer that constitutes a photodiode and stores light by converting it into electric charges. A signal storage unit (third signal storage unit) 42 is provided. The first signal storage unit 41 is spaced apart from one end of the drain region 35 opposite to the gate electrode 34 type, and is formed near the surface of the p-type substrate / well 20. The second signal storage unit 42 is formed so as to be connected to the p-type substrate / well 20 below the drain region 35 of the adjacent first pixel 30 and the first signal storage unit 41 of the own pixel 40. . A gate electrode 44 is provided on the p-type substrate / well 20 via a gate insulating film 43 adjacent to one end different from the drain region 35 side of the first signal storage unit 41. A drain region 45 made of an n-type diffusion layer is provided on the surface portion of the p-type substrate / well 20 on the opposite side of the gate electrode 44 from the first signal storage portion 41 side. The above is the configuration of the second pixel 40 configuring one pixel. The length in the longitudinal direction of the gate electrode 44 of the second signal storage unit 42 is formed longer than the length in the longitudinal direction of the gate electrode 44 of the first signal storage unit 41.

第１の画素３０と第２の画素４０との間のｐ型基板／ウェル２０にはトレンチが形成され、トレンチ内に素子分離絶縁膜２１が埋め込まれている。なお、符号５２は隣接する画素の第２の信号蓄積部である。   A trench is formed in the p-type substrate / well 20 between the first pixel 30 and the second pixel 40, and an element isolation insulating film 21 is embedded in the trench. Reference numeral 52 denotes a second signal storage unit of an adjacent pixel.

第１の画素３０のドレイン領域３５と第１の画素３０に隣接する第２の画素４０の第２の信号蓄積部４２との間には、ｐ型のパンチスルーストッパ層２２が形成されている。パンチスルーストッパ層２２のｐ型不純物濃度は、基板／ウェル２０のｐ型不純物濃度より高い。パンチスルーストッパ層２２により、第１の画素３０と第２の画素４０とが素子分離され、第２の画素４０の第２の信号蓄積部４２の蓄積信号が第１の画素３０のドレイン領域３５に流れることがない。また、パンチスルーストッパ層２２と第２の信号蓄積部４２との接合容量により、フォトダイオードの容量をさらに増大させることができる。   A p-type punch-through stopper layer 22 is formed between the drain region 35 of the first pixel 30 and the second signal storage portion 42 of the second pixel 40 adjacent to the first pixel 30. . The p-type impurity concentration of the punch-through stopper layer 22 is higher than the p-type impurity concentration of the substrate / well 20. The first pixel 30 and the second pixel 40 are separated from each other by the punch-through stopper layer 22, and the accumulation signal of the second signal accumulation unit 42 of the second pixel 40 is the drain region 35 of the first pixel 30. Will not flow. Further, the capacitance of the photodiode can be further increased by the junction capacitance between the punch-through stopper layer 22 and the second signal storage unit 42.

このフォトダイオード構造では、第２の画素４０の第２の信号蓄積部４２が隣接する画素３０のドレイン領域３５の下方に形成されているので、実効的なフォトダイオードの面積を広げられる。また、隣接する画素４０の下に第２の信号蓄積部４２を広げても、第２の信号蓄積部４２に蓄積された信号電荷が隣接する画素３０の蓄積信号の読み出し時に読み出されることはない。よって、パンチスルーストッパ層２２により、第２の信号蓄積部４２とドレイン領域３５とを素子分離することだけを考慮すれば良い。   In this photodiode structure, since the second signal storage portion 42 of the second pixel 40 is formed below the drain region 35 of the adjacent pixel 30, the effective photodiode area can be increased. Further, even if the second signal storage unit 42 is extended under the adjacent pixel 40, the signal charge stored in the second signal storage unit 42 is not read out when the storage signal of the adjacent pixel 30 is read. . Therefore, only the element isolation between the second signal storage portion 42 and the drain region 35 by the punch-through stopper layer 22 needs to be considered.

さらに、信号蓄積部を隣接画素の検出部下部に形成する構造においては、自画素のトランジスタのゲート電極の下方に自画素の信号蓄積部が形成されていない。よって、ゲート電極の下方に信号蓄積部と逆導電型の半導体層を形成する必要がない。よって、読み出しトランジスタの閾値を調整する必要が無く、読み出しトランジスタの動作マージンが狭くならず、素子動作の安定化をはかることができる。   Further, in the structure in which the signal accumulation unit is formed below the detection unit of the adjacent pixel, the signal accumulation unit of the own pixel is not formed below the gate electrode of the transistor of the own pixel. Therefore, it is not necessary to form a semiconductor layer having a conductivity type opposite to that of the signal storage portion below the gate electrode. Therefore, it is not necessary to adjust the threshold value of the read transistor, the operation margin of the read transistor is not narrowed, and the element operation can be stabilized.

なお、本発明は、上記実施形態に限定されるものではない。その他、本発明は、その要旨を逸脱しない範囲で、種々変形して実施することが可能である。   In addition, this invention is not limited to the said embodiment. In addition, the present invention can be variously modified and implemented without departing from the scope of the invention.

本発明の一実施形態に係わるＭＯＳイメージセンサを示す回路構成図。The circuit block diagram which shows the MOS image sensor concerning one Embodiment of this invention. 本発明の一実施形態に係わるＣＭＯＳイメージセンサの素子構造を示す図。The figure which shows the element structure of the CMOS image sensor concerning one Embodiment of this invention.

符号の説明Explanation of symbols

１…フォトダイオード，２…トランジスタ，３…増幅トランジスタ，４…垂直選択トランジスタ，５…リセットトランジスタ，６…垂直シフトレジスタ，７…水平アドレス線
８…リセット線，９…垂直信号線，１０…負荷トランジスタ，１１…水平選択トランジスタ，１２…水平シフトレジスタ，１３…水平信号線，２０…ｐ型のＳｉ基板又はｐウェル，２１…素子分離絶縁膜，２２…パンチスルーストッパ層，３０…第１の画素，３１…第１の信号蓄積部，３２…第２の信号蓄積部，３３…ゲート絶縁膜，３４…ゲート電極，３５…ドレイン領域，４０…第２の画素，４１…第１の信号蓄積部，４２…第２の信号蓄積部，４３…ゲート絶縁膜，４４…ゲート電極，４５…ドレイン領域 DESCRIPTION OF SYMBOLS 1 ... Photodiode, 2 ... Transistor, 3 ... Amplification transistor, 4 ... Vertical selection transistor, 5 ... Reset transistor, 6 ... Vertical shift register, 7 ... Horizontal address line 8 ... Reset line, 9 ... Vertical signal line, 10 ... Load Transistor 11, horizontal selection transistor 12, horizontal shift register, 13 horizontal signal line, 20 p-type Si substrate or p-well, 21 element isolation insulating film 22 punch-through stopper layer 30 first Pixel, 31... First signal storage unit, 32... Second signal storage unit, 33... Gate insulating film, 34... Gate electrode, 35. Part, 42 ... second signal storage part, 43 ... gate insulating film, 44 ... gate electrode, 45 ... drain region

Claims (5)

第１導電型の半導体基板又はウェルの表面近傍に形成され、光電変換して得られた信号電荷を蓄積する第２導電型の第１の信号蓄積部と、
前記第１の信号蓄積部の一端に隣接して前記基板又はウェルの上部に設けられた第１のゲート電極と、
この第１のゲート電極の前記第１の信号蓄積部側とは反対側の端に隣接して設けられた第２導電型の第１のドレイン領域と、
第１導電型の半導体基板又はウェルの表面近傍に、第１のドレイン領域の前記ゲート電極側と反対側に離間して形成され、光電変換して得られた信号電荷を蓄積する第２導電型の第２の信号蓄積部と、
第１導電型の半導体基板又はウェルの内部に、前記第１のドレイン領域の下方、且つ第２の信号蓄積部に接続して形成された第３の信号蓄積部と、
前記第２の信号蓄積部の前記第１のドレイン領域側と反対側の端に隣接して前記半導体基板又はウェルの上部に設けられた第２のゲート電極と、
この第２のゲート電極の前記第２の信号蓄積部側とは反対側の端に隣接して設けられた第２導電型の第２のドレイン領域とを具備してなることを特徴とする固体撮像装置。 A second conductivity type first signal storage unit that is formed in the vicinity of the surface of the first conductivity type semiconductor substrate or well and stores signal charges obtained by photoelectric conversion;
A first gate electrode provided on an upper portion of the substrate or well adjacent to one end of the first signal storage unit;
A first drain region of a second conductivity type provided adjacent to an end of the first gate electrode opposite to the first signal storage portion side;
Second conductivity type, which is formed in the vicinity of the surface of the first conductivity type semiconductor substrate or well, on the opposite side to the gate electrode side of the first drain region, and accumulates signal charges obtained by photoelectric conversion. A second signal storage unit of
A third signal storage unit formed inside the first conductivity type semiconductor substrate or well, below the first drain region and connected to the second signal storage unit;
A second gate electrode provided on an upper portion of the semiconductor substrate or well adjacent to an end of the second signal storage portion opposite to the first drain region side;
And a second drain region of a second conductivity type provided adjacent to an end of the second gate electrode opposite to the second signal storage portion side. Imaging device. 前記第３の信号蓄積部は、前記第２のゲート電極の下方に形成されていないことを特徴とする請求項１に記載の固体撮像装置。   The solid-state imaging device according to claim 1, wherein the third signal accumulation unit is not formed below the second gate electrode. 第１のドレイン領域と第２の信号蓄積部との間の前記半導体基板又はウェルにトレンチが形成され、前記トレンチ内に素子分離絶縁膜が形成されていることを特徴とする請求項１に記載の固体撮像装置。   2. The device according to claim 1, wherein a trench is formed in the semiconductor substrate or well between the first drain region and the second signal storage unit, and an element isolation insulating film is formed in the trench. Solid-state imaging device. 第１のドレイン領域と第３の信号蓄積部との間に、第１導電型不純物の濃度が前記半導体基板又はウェルの第１導電型不純物の濃度より高い前記第１導電型の半導体層が形成されていることを特徴とする請求項１に記載の固体撮像装置。   The first conductivity type semiconductor layer having a concentration of the first conductivity type impurity higher than the concentration of the first conductivity type impurity of the semiconductor substrate or well is formed between the first drain region and the third signal storage unit. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is provided. 前記半導体層は、前記第２のゲート電極の下方に形成されていないことを特徴とする請求項４に記載の固体撮像装置。   The solid-state imaging device according to claim 4, wherein the semiconductor layer is not formed below the second gate electrode.
JP2004136584A 2004-04-30 2004-04-30 Solid-state image sensing device Pending JP2005317875A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2004136584A JP2005317875A (en) 2004-04-30 2004-04-30 Solid-state image sensing device
US11/095,592 US7259412B2 (en) 2004-04-30 2005-04-01 Solid state imaging device
CNB200510066870XA CN100438055C (en) 2004-04-30 2005-04-29 Solid state imaging device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004136584A JP2005317875A (en) 2004-04-30 2004-04-30 Solid-state image sensing device

Publications (1)

Publication Number Publication Date
JP2005317875A true JP2005317875A (en) 2005-11-10

Family

ID=35186194

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004136584A Pending JP2005317875A (en) 2004-04-30 2004-04-30 Solid-state image sensing device

Country Status (3)

Country Link
US (1) US7259412B2 (en)
JP (1) JP2005317875A (en)
CN (1) CN100438055C (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6690423B1 (en) * 1998-03-19 2004-02-10 Kabushiki Kaisha Toshiba Solid-state image pickup apparatus
JP2005317875A (en) 2004-04-30 2005-11-10 Toshiba Corp Solid-state image sensing device
KR100760142B1 (en) * 2005-07-27 2007-09-18 매그나칩 반도체 유한회사 Stacked pixel for high resolution cmos image sensors
JP5180537B2 (en) * 2007-08-24 2013-04-10 キヤノン株式会社 Photoelectric conversion device and multichip image sensor
JP5328207B2 (en) * 2008-04-01 2013-10-30 キヤノン株式会社 Solid-state imaging device
US20100149393A1 (en) * 2008-05-22 2010-06-17 Panavision Imaging, Llc Increasing the resolution of color sub-pixel arrays
US8035711B2 (en) * 2008-05-22 2011-10-11 Panavision Imaging, Llc Sub-pixel array optical sensor
US20090290052A1 (en) * 2008-05-23 2009-11-26 Panavision Imaging, Llc Color Pixel Pattern Scheme for High Dynamic Range Optical Sensor
US8294232B2 (en) * 2009-01-15 2012-10-23 Raytheon Company High quantum efficiency optical detectors
JP2011114302A (en) * 2009-11-30 2011-06-09 Sony Corp Method of manufacturing semiconductor device, semiconductor device, solid-state imaging device, and solid-state imaging apparatus
US20110205384A1 (en) * 2010-02-24 2011-08-25 Panavision Imaging, Llc Variable active image area image sensor
CN113727000A (en) * 2016-05-27 2021-11-30 松下知识产权经营株式会社 Image pickup system

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1174499A (en) * 1997-07-04 1999-03-16 Toshiba Corp Solid-state image pickup device, manufacture thereof and system using that solid-state image pickup device
US6690423B1 (en) * 1998-03-19 2004-02-10 Kabushiki Kaisha Toshiba Solid-state image pickup apparatus
US6346722B1 (en) * 1998-06-26 2002-02-12 Nec Corporation Solid state imaging device and method for manufacturing the same
JP4109858B2 (en) * 2001-11-13 2008-07-02 株式会社東芝 Solid-state imaging device
KR100436067B1 (en) 2001-11-16 2004-06-12 주식회사 하이닉스반도체 Image sensor and method of fabricating the same
JP2005317875A (en) 2004-04-30 2005-11-10 Toshiba Corp Solid-state image sensing device

Also Published As

Publication number Publication date
US7259412B2 (en) 2007-08-21
US20050242385A1 (en) 2005-11-03
CN1694261A (en) 2005-11-09
CN100438055C (en) 2008-11-26

Similar Documents

Publication Publication Date Title
JP4514188B2 (en) Photoelectric conversion device and imaging device
JP5328224B2 (en) Solid-state imaging device
JP5292787B2 (en) Solid-state imaging device and camera
TWI389307B (en) Solid-state imaging device and camera
KR101344539B1 (en) Pinned-photodiode pixel with global shutter
US7259412B2 (en) Solid state imaging device
JP3702854B2 (en) Solid-state image sensor
JP2008004692A (en) Solid-state imaging device
JP2007335751A (en) Solid-state imaging apparatus
JP2009510777A (en) Photodetector and N-type layer structure for improved collection
WO2012160802A1 (en) Solid-state image capture device
JP4991418B2 (en) Solid-state imaging device
US20010011736A1 (en) Pixel structure with improved charge transfer
JP4155568B2 (en) Solid-state imaging device and camera
JP2015130533A (en) Solid state imaging device and camera
JP2007134639A (en) Photoelectric conversion device and image sensing element using the same
JP5435640B2 (en) Image sensor with pixel separation
JP2006100620A (en) Solid-state image pickup element and semiconductor device
JP2007165736A (en) Jfet (junction type field effect transistor) and solid-state image pickup device using same
JP6536627B2 (en) Solid-state imaging device and electronic device
JP2007184368A (en) Solid-state image sensor
JP2007251074A (en) Solid-state image sensing element and device
JP5725232B2 (en) Solid-state imaging device and camera
JP2005123280A (en) Solid state image sensing device
JP2007088002A (en) Cmos image sensor ic

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20060302

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20081106

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20081111

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20090310