JP2006216667A - Semiconductor wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide the structure of a semiconductor crystal substrate which suppresses the propagation of a dislocation to an active layer from a GaAs substrate. <P>SOLUTION: A structure in which an InAs nucleus is formed in the shape of a dot (the shape of an island) in a flat surface between the GaAs substrate 1 and the active layers 40, and a buffer layer 20 of a group III-V compound semiconductor is grown to be the grade in which the InAs nucleus is buried on it. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor wafer in which a III-V compound semiconductor layer such as gallium arsenide (GaAs) or aluminum gallium arsenide (AlGaAs) is formed on a GaAs substrate, and more specifically, as an active layer, for example, a heterojunction bipolar transistor ( In the case of having an (HBT) structure, the present invention relates to a substrate structure for improving the reliability of the HBT element.

  When trying to obtain a semiconductor film, the easiest method is to prepare a compound semiconductor substrate made of the same material as the compound semiconductor to be grown and vapor-deposit it thereon. Success in material systems.

  For example, by utilizing the excellent physical properties of compound semiconductors such as GaAs, high performance and high performance semiconductor devices such as HBT, HEMT, MESFET, LED, and laser diode are manufactured by laminating semiconductor films with various physical properties. It has been tried to do.

  Such a semiconductor film is normally formed on a GaAs substrate by a metal organic vapor phase epitaxy (MOVPE method) or the like using a GaAs crystal cut from a single crystal ingot of GaAs as a substrate.

  The type of GaAs substrate is roughly classified from the manufacturing process, the “VGF substrate” obtained by slicing a single crystal ingot prepared by the vertical temperature gradient solidification method (VGF method), and the vertical Bridgman method (VB method). There are a “VB substrate” obtained by slicing a single crystal ingot created by the above method, an “LEC substrate” obtained by slicing a single crystal ingot created by a liquid sealing pulling method (LEC method), and the like.

  Conventionally, when an epitaxial layer of an HBT epitaxial wafer (semiconductor wafer) is grown, a semi-insulating VGF substrate or VB substrate has been used as the GaAs substrate because of a small number of dislocations that are an assembly of defects. . That is, since the LEC substrate has many dislocations, it is difficult to apply it to InGaP-based HBTs, and VGF substrates and VB substrates have been adopted.

On the other hand, a compound semiconductor substrate made of GaAs or the like is mechanically fragile, difficult to handle, and it is difficult to obtain a high-quality, large-area crystal substrate. There is also a method for crystal growth of a compound semiconductor such as GaAs. In this method, an epitaxially grown semiconductor crystal substrate having a structure in which at least one high-resistance compound semiconductor layer to which oxygen is added is provided between the Si substrate and the active layer of the compound semiconductor layer has been proposed (for example, Patent Document 1). reference).
JP-A-6-208963

  However, III-V group compound semiconductors such as GaAs are advantageously grown epitaxially on a GaAs substrate.

  However, when a VGF substrate or a VB substrate is selected as the GaAs substrate, there are the following problems. That is, the VGF substrate and the VB substrate have significantly fewer dislocations than the LEC substrate, but the dislocations themselves exist. Therefore, when these dislocations enter the emitter region, the electrical characteristics of the HBT deteriorate (reliability decreases). There was a problem. Such a problem of deterioration of electrical characteristics is a problem that occurs also in elements other than the HBT.

  Therefore, an object of the present invention is to provide a structure of a semiconductor crystal substrate that solves the above problems and suppresses the propagation of dislocations from the GaAs substrate to the active layer.

  In the present invention, by devising the structure of the GaAs substrate, the effect of suppressing the dislocation propagation to the active layer such as the HBT structure is obtained, and the LEC substrate with many dislocations that has been difficult to apply to the InGaP-based HBT until now. However, it provides a substrate structure that can be used.

  In order to achieve the above object, the present invention is configured as follows.

  According to the first aspect of the present invention, in a semiconductor wafer in which a group III-V compound semiconductor layer is formed on a GaAs substrate, InAs nuclei are dotted in a plane between the active layer of the group III-V compound semiconductor layer and the GaAs substrate. It is characterized by having a structure in which a buffer layer of a III-V group compound semiconductor layer is grown to such an extent that an InAs nucleus is buried thereon.

  According to a second aspect of the present invention, in a semiconductor wafer in which a III-V compound semiconductor layer is formed on a GaAs substrate, InGaAs nuclei are dotted in a plane between the active layer of the III-V compound semiconductor layer and the GaAs substrate. It is characterized by having a structure in which a buffer layer of a III-V compound semiconductor layer is grown to such an extent that InGaAs nuclei are buried thereon.

  According to a third aspect of the present invention, in the semiconductor wafer according to the first or second aspect, the buffer layer is made of any one of GaAs, AlGaAs, InGaAs, or InGaP.

  According to a fourth aspect of the present invention, in the semiconductor wafer according to any one of the first to third aspects, the active layer includes a sub-collector layer made of n-type GaAs, a collector layer made of n-type GaAs, p-type GaAs, It has a heterojunction bipolar transistor structure including a base layer made of either p-type InGaAs or p-type AlGaAs, an emitter layer made of n-type AlGaAs or n-type InGaP, and an emitter contact layer made of n-type InGaAs. And

<Key points of the present invention>
The main point of the present invention is that dislocations are prevented from extending to the upper layer by forming InAs nuclei in the form of dots on the substrate and performing lateral growth of the InAs nuclei by the facet surface during the growth of the buffer layer.

  That is, on the GaAs substrate 1 shown in FIG. 2A, by a vapor phase growth method, in a three-dimensional island growth mode instead of a normal secondary growth mode, as shown in FIG. The InAs nuclei 21 are formed in a dot shape (island shape) in the plane. Then, a single crystal compound semiconductor buffer layer 30 such as GaAs is grown so that the InAs nuclei 21 are sufficiently buried thereon, and the surface is flattened (FIGS. 2C and 2D). Thus, when the surface of the buried InAs nuclei (InAs dots) 21 is flattened by the growth of the compound semiconductor buffer layer 30, the propagation direction of the dislocations 22 that propagate in the direction perpendicular to the substrate surface is usually Since it changes in the lateral direction as shown in FIG. 2C in the process of burying growth, the density of dislocations 32 appearing on the outermost surface is greatly reduced as shown in FIG.

  For this reason, when forming a III-V compound semiconductor layer on a GaAs substrate, it is possible to adopt any GaAs substrate, regardless of whether it is a “VGF substrate”, “VB substrate”, or “LEC substrate”. And good device characteristics can be secured.

  InAs dots 21 are formed on the GaAs surface in the form of dots instead of a thin film if the growth temperature is in the range of 400 to 550 ° C. (effective is 450 to 500 ° C.). Originally, the lattice constant difference between GaAs and InAs is large, so InAs does not grow as a thin film on GaAs. The reason why the lower limit of the growth temperature is set to 400 ° C. is that when the growth temperature is lower than 400 ° C., it grows in a polycrystalline or amorphous state and does not become dots. The upper limit of the growth temperature is set to 550 ° C. because if the growth temperature is higher than 550 ° C., In re-evaporation occurs and it becomes impossible to form clean dots.

  If the height of the InAs dots is at least 5 nm or more, the effect of lateral growth by the facet surface will not be obtained. Further, the upper limit of InAs dots is preferably 20 nm or less so that the shape of the dots can be maintained. If the thickness exceeds 20 nm, InAs itself grows laterally and it becomes impossible to form clean dots.

  Although InGaAs nuclei can be used instead of InAs nuclei, the higher the In composition ratio in the InGaAs nuclei, the better.

  According to the semiconductor crystal substrate of the present invention, dislocations are prevented from extending to the upper layer by forming InAs nuclei in the form of dots on a GaAs substrate and performing lateral growth of the InAs nuclei on the buffer layer during the growth of the buffer layer. Therefore, the effect of suppressing dislocation propagation to the active layer such as the HBT structure can be obtained. Therefore, according to the present invention, it is possible to provide an element such as an HBT and a wafer thereof having higher reliability than the conventional one.

  Further, according to the present invention, even an LEC substrate with many dislocations, which has been difficult to apply to InGaP-based HBTs, can be used without being affected by the dislocations.

  Hereinafter, the present invention will be described based on the illustrated embodiments.

  FIG. 1 shows an example embodiment. In this embodiment, in a semiconductor wafer in which a group III-V compound semiconductor layer is formed on a GaAs substrate 1, an InAs nucleus is formed in a plane between the active layer 40 of the group III-V compound semiconductor layer and the GaAs substrate 1. Is formed in a dot shape (island shape), and a single crystal GaAs buffer layer 30 is grown thereon to embed InAs nuclei, thereby planarizing the surface. As described with reference to FIG. 2, when the buffer layer 30 is grown, lateral growth by the facets of the InAs nuclei 21 is performed to prevent the dislocations 22 from extending to the upper layer. The buffer layer may be made of AlGaAs, InGaAs, or InGaP in addition to GaAs.

  By selecting the structure of the active layer 40, various heterojunction compound semiconductor devices such as HBT, HEMT, MESFET, LED, and laser diode can be manufactured.

  A typical laminated structure of the active layer 40 is composed of a sub-collector layer made of n-type GaAs, a collector layer made of n-type GaAs, and any one of p-type GaAs, p-type InGaAs or p-type AlGaAs. There is an HBT structure including a base layer, an emitter layer made of n-type AlGaAs or n-type InGaP, and an emitter contact layer made of n-type InGaAs.

  That is, on a gallium arsenide (GaAs) substrate, a sub-collector layer made of GaAs crystal showing n-type conduction to form an ohmic contact with a metal electrode, and a GaAs crystal showing n-type conduction drawing electrons from the base layer. And a base layer made of a GaAs crystal, indium gallium arsenide (InGaAs) crystal, or aluminum gallium arsenide (AlGaAs) crystal exhibiting p-type conduction for controlling the flow of electrons, and a heterojunction to the base layer. Forming an emitter layer made of an AlGaAs crystal or indium gallium phosphide (InGaP) crystal exhibiting n-type conduction, injecting electrons into the base layer, and suppressing injection of holes from the base layer; and a metal electrode and an ohmic contact Emitter capacitor made of InGaAs crystal showing n-type conductivity to be formed In the heterojunction bipolar transistor (HBT) configured to include a transfected layer, prior to growing the aforementioned sub-collector layer, a semiconductor crystal substrate, characterized in that the InAs core on the substrate surface is formed in a dot shape.

  In this semiconductor crystal substrate, before the subcollector is grown, a GaAs, AlGaAs, InGaAs or InGaP buffer is grown so that the InAs nuclei are sufficiently filled. Each layer of the HBT structure is grown by the MOVPE method or the MBE method.

  FIG. 3 and Table 1 show the structure of an AlGaAs / GaAs HBT epitaxial wafer (semiconductor wafer) according to an embodiment of the present invention.

  In FIG. 3, a VB or VGF substrate is used as the semi-insulating GaAs substrate 1. On this substrate, first, an InAs dot layer 20 having InAs nuclei (InAs dots) formed in a dot shape with a height of about 10 nm in a plane is formed, and an InAs nuclei is buried thereon to planarize the surface. A GaAs buffer layer 30 was grown to 100 nm. Further, an epitaxial layer having an HBT structure was grown thereon by a growth method similar to the conventional one, and an epitaxial wafer for HBT (semiconductor wafer) of this example was obtained.

On the GaAs buffer layer 30, a subcollector layer 2 made of n ⁺ -type GaAs having a thickness of 500 nm and a carrier concentration of 5 × 10 ¹⁸ cm ⁻³ and In _z Ga _1-z P (z = 0.55) Layer 2a and collector layer 3 made of n ^- type GaAs having a thickness of 500 nm and a carrier concentration of 2 × 10 ¹⁶ cm ⁻³ are sequentially stacked, and a carrier concentration by C doping is 4 × 10 ¹⁹ cm ⁻³ , A base layer 4 made of p ⁺ -type GaAs having a thickness of 70 nm is laminated.

On this base layer 4, an n-type Al _0.3 Ga _0.7 As layer 5 a having a carrier concentration of 5 × 10 ¹⁷ cm ⁻³ and a thickness of 100 nm as an emitter layer 5 is mixed with AlAs on the layer 5 a. N ⁺ -type Al _x Ga grown by gradually decreasing the crystal ratio x from 0.3 to 0 and having a thickness of about 50 nm and a carrier concentration of 5 × 10 ¹⁷ cm ⁻³ to 5 × 10 ¹⁸ cm ⁻³ by Si doping _{A 1-x} As graded layer 5b is laminated.

Further, on the emitter layer 5, an emitter contact layer 6 is formed on the n ⁺ type GaAs layer 6a having a thickness of 100 nm and a carrier concentration of 5 × 10 ¹⁸ cm ⁻³ by Si doping, and on this layer 6a. N ⁺ type In _y Ga _1-y As (y = 0 → 0.5) graded layer 6b having a thickness of 50 nm and a carrier concentration by Se doping of 1 × 10 ¹⁹ cm ⁻³ to 4 × 10 ¹⁹ cm ⁻³ And an n ⁺ -type In _0.5 Ga _0.5 As layer 6c (non-alloy layer) formed on the graded layer 6b and having a thickness of 50 nm and a carrier concentration of 4 × 10 ¹⁹ cm ⁻³ by Se doping are sequentially laminated. ing. The n ⁺ -type In _y Ga _{1 -y} As graded layer 6b has a structure in which the InAs mixed crystal ratio y is gradually increased from 0 to 0.5 from the lower surface to the upper surface.

  These InAs dot layer 20, GaAs buffer layer 30, subcollector layer 2, collector layer 3, base layer 4, emitter layer 5 and emitter contact layer 6 were grown by the MOVPE method.

  As a comparative example, an HBT epitaxial wafer having a conventional structure was grown in exactly the same manner as the stacked structure of the HBT epitaxial wafer (semiconductor wafer) of this example except for the formation of the InAs dot layer 20.

  These HBT epitaxial wafers (semiconductor wafers) were subjected to a process to produce an HBT element having an emitter size of 2 × 20 μm.

These devices were subjected to a reliability test. The test conditions were Vce = 3V, Ic = 10 mA (current density 2.5 × 10 ⁴ A / cm ² ), the temperature of the oven for heating the HBT element was 160 ° C., and the change in current gain β when energized for 500 hours ( (Depression) was within 10%.

  The results of the reliability test are shown in Table 2.

  Of the 500 prototypes tested for the conventional HBT, about 5 were rejected, whereas the HBT having the structure of the present embodiment (the present invention) did not fail. Further, in the conventional structure of the HBT, even when the HBT passed the reliability test, there was a tendency that the current amplification factor β gradually decreased.

<Other examples and modifications>
In the above embodiment, GaAs is used as the material of the buffer layer. However, any of GaAs, AlGaAs, InGaAs, and InGaP can be selected and used as the buffer layer material. A buffer made of these materials can be used. Even in the case of a layer, a similar low dislocation effect can be secured and a highly reliable element can be obtained. However, InGaAs and InGaP are limited to thicknesses and compositions that do not cause strain relaxation due to lattice mismatch.

  In the above embodiment, a VB or VGF substrate is used as the semi-insulating GaAs substrate 1, but in the present invention, even when an LEC substrate having many dislocations is used, the effect of suppressing dislocation propagation can be obtained. . That is, when an LEC substrate is used, about 3% (15 out of 500) is considered to be unsuitable for reliability when the structure of the conventional semiconductor crystal substrate is different depending on the user's process. Yes. On the other hand, according to the structure of the semiconductor crystal substrate of the present invention, the inappropriate ratio can be made almost 0%. Accordingly, even LEC substrates that have been difficult to apply to InGaP-based HBTs can be used.

It is a figure which shows the structure of the semiconductor crystal substrate of this invention. It is a figure where it uses for description of an effect | action of the semiconductor crystal substrate of this invention. It is a figure which shows the structure of the semiconductor crystal substrate for HBT which concerns on the Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 GaAs substrate 2 Subcollector layer 3 Collector layer 4 Base layer 5 Emitter layer 6 Emitter contact layer 20 InAs dot layer 21 InAs nucleus 22, 32 Dislocation 30 Compound semiconductor buffer layer (GaAs buffer layer)
40 Active layer

Claims (4)

In a semiconductor wafer in which a III-V compound semiconductor layer is formed on a GaAs substrate,
Between the active layer of the III-V compound semiconductor layer and the GaAs substrate, InAs nuclei are formed in dots in a plane, and a buffer layer of the III-V compound semiconductor layer is formed so that the InAs nuclei are buried thereon. A semiconductor wafer characterized by having a grown structure. In a semiconductor wafer in which a III-V compound semiconductor layer is formed on a GaAs substrate,
Between the active layer of the III-V compound semiconductor layer and the GaAs substrate, InGaAs nuclei are formed in the shape of dots in a plane, and the buffer layer of the III-V compound semiconductor layer is formed so that the InGaAs nuclei are buried on it. A semiconductor wafer characterized by having a grown structure. In the semiconductor wafer according to claim 1 or 2,
A semiconductor wafer, wherein the buffer layer is made of any one of GaAs, AlGaAs, InGaAs, or InGaP. In the semiconductor wafer in any one of Claims 1 thru | or 3,
As the active layer, a sub-collector layer made of n-type GaAs, a collector layer made of n-type GaAs, a base layer made of p-type GaAs, p-type InGaAs or p-type AlGaAs, n-type AlGaAs or n-type A semiconductor wafer having a heterojunction bipolar transistor structure including an emitter layer made of InGaP and an emitter contact layer made of n-type InGaAs.

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