JP2006215934A - Constant current source circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To supply stable electric current even if a power source voltage fluctuates. <P>SOLUTION: This constant current source circuit outputting constant electric current is provided with a current mirror circuit 10 to which power source voltage VDD is supplied, a current mirror circuit 20 connected to the current mirror circuit 10 in series for deciding electric current flowing through the current mirror circuit 10, and an operation stop prevention circuit 30 working not to shut off electric current I<SB>0</SB>flowing through NPN bipolar transistors Q1 and Q2 in the current mirror circuit 20 when the power source voltage VDD is lowered. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a constant current source circuit, and more particularly to a constant current source circuit that outputs a constant current.

Conventionally, a constant current source circuit (constant current source) for supplying a constant current to individual circuits constituting a semiconductor integrated circuit is known. (For example, refer to Patent Document 1).
FIG. 4 is a circuit diagram showing a conventional constant current source circuit.

  The constant current source circuit shown in FIG. 4 includes a current mirror circuit 91 including a pair of PMOS transistors M91 and M92, a current mirror circuit 92 including a pair of NPN transistors Q91 and Q92, and resistors R90, R91, and R92. The current (emitter current) I flowing through each of the NPN transistors Q91 and Q92 becomes the output current (constant current) of the current mirror circuit 92.

In this circuit, when the power supply voltage VDD decreases, the current I of the NPN transistor Q92 reduces the charge of the diode junction capacitance between the base and the collector, whereby the voltage between the base and the collector of the NPN transistor Q92, that is, the point The voltage V91 of P91 decreases and tries to balance the voltage of the entire circuit. The maximum rate of decrease of voltage V91 is determined by current I of NPN transistor Q92.
Japanese Patent Laid-Open No. 11-231955

  However, in the conventional constant current source circuit, there is no discharge path for the charge charged in the NPN transistor Q92 other than the path that goes out to GND through the resistor R90, so that the voltage drop of the power supply voltage VDD is fast (large). In some cases, the decrease in the potential V91 at the point P91 cannot follow the decrease in the power supply voltage VDD.

  In this case, the gate-source voltage VSG of the PMOS transistors M91 and M92 decreases and the voltage VSG becomes equal to the threshold voltage of the PMOS transistors M91 and M92 (the voltage for driving the PMOS transistors M91 and M92). Thus, the PMOS transistors M91 and M92 are turned off (cut off).

Then, since the base current is not supplied to the NPN transistors Q91 and Q92, the current (emitter current) I also does not flow, and the voltage V91 does not decrease any more.
As a result, the gate-source voltage VSG of the PMOS transistors M91 and M92 cannot exceed the threshold voltage of the PMOS transistors M91 and M92, and the PMOS transistors M91 and M92 and the NPN transistors Q91 and Q92 are turned off. There is a problem that the output current does not flow and the constant current source circuit is stopped.

  The present invention has been made in view of these points, and an object thereof is to provide a constant current source circuit that stably supplies a current.

  In the present invention, in order to solve the above problem, in a constant current source circuit that outputs a constant current, a current mirror circuit to which a power supply voltage is supplied and a current that is connected in series to the current mirror circuit and flows through the current mirror circuit A constant current source circuit comprising: at least one bipolar transistor for determining the operation; and an operation stop prevention circuit that operates so as not to cut off the current flowing through the bipolar transistor when the power supply voltage decreases. Provided.

  According to the above configuration, it is ensured that a current flows through the bipolar transistor even when the power supply voltage is drastically lowered, so that the current can be supplied stably.

  According to the present invention, by providing the operation stop prevention circuit, even when the power supply voltage is lowered, a discharge path for charges charged in the bipolar transistor is secured, and the emitter current of the bipolar transistor can be made constant. The current can be supplied stably.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(First embodiment)
FIG. 1 is a circuit diagram showing a constant current source circuit according to the first embodiment.

The constant current source circuit shown in FIG. 1 is a circuit that outputs a constant current I ₀ , and includes a current mirror circuit 10, a current mirror circuit 20 connected in series to the current mirror circuit 10, and an operation stop prevention circuit 30. , Resistors R0, R1, and R2.

The current mirror circuit 10 includes PMOS transistors M1 and M2.
The PMOS transistors M1 and M2 are connected to each other and to the gate and drain of the PMOS transistor M2. The source of the PMOS transistor M1 is connected to the supply line of the power supply voltage VDD via the resistor R1. The source of the PMOS transistor M2 is connected to the supply line of the power supply voltage VDD via the resistor R2.

The PMOS transistors M1 and M2 can be replaced with PNP transistors, respectively.
The current mirror circuit 20 includes NPN transistors (bipolar transistors) Q1 and Q2.

  NPN transistors Q1 and Q2 have both bases connected to each other and the collector and base of NPN transistor Q1. One end of a resistor R0 is connected to the emitter of the NPN transistor Q2. The other end of the resistor R3 and the emitter of the NPN transistor Q1 are both connected to GND. The NPN transistors Q1 and Q2 are formed so that the emitter area ratio between the NPN transistors Q1 and Q2 is n (n = A2 / A1), where A1 and A2 are the respective emitter areas. Note that the current mirror circuit 20 can also be configured by switching the NPN transistor Q1, the NPN transistor Q2, and the resistor R1 from left to right.

  The collector of the NPN transistor Q1 and the drain of the PMOS transistor M1 are connected, and the collector of the NPN transistor Q2 and the drain of the PMOS transistor M2 are connected.

The operation stop prevention circuit 30 includes PMOS transistors M3 and M4, NMOS transistors M5 and M6, and a resistor R3.
The PMOS transistor M3 has a gate (the other end) connected to a point P1, which is a connection portion between the PMOS transistor M2 and the NPN transistor Q2, and a source (one end) connected to the power supply voltage VDD.

  The PMOS transistor M4 and the NMOS transistor M5 constitute an inverter circuit, and their gates are respectively connected to the drain of the PMOS transistor M3. The drains of the PMOS transistor M4 and the NMOS transistor M5 are connected to the gate of the NMOS transistor M6, respectively. That is, this inverter circuit inverts the output of the PMOS transistor M3 and outputs the inverted signal to the NMOS transistor M6.

  The NMOS transistor M6 is turned on / off by the output voltage of the inverter circuit described above, and has a drain connected to the point P1 and a source connected to GND.

Next, the basic operation of the constant current source circuit configured as described above will be described.
When the currents flowing through the NPN transistors Q1 and Q2 are I ₀ and the base-emitter voltages of the NPN transistors Q1 and Q2 are Vd1 and Vd2, respectively, the following equation (1) is established.

Vd1 = I ₀ * R3 + Vd2 (1)
On the other hand, Vd1 and Vd2 are given by the following equations (2) and (3).
Vd1 = V _T * ln (I ₀ / I _s ) (2)
Vd2 = V _T * ln (I ₀ / nI _s ) (3)
_{However, V T = kT / q (} k is the Boltzmann constant, T is the absolute temperature, q the electron of the charge), and the I _s is the saturation current value (constant).

Then, when Expression (2) and Expression (3) are substituted into Expression (1), current I ₀ flowing through NPN transistors Q1 and Q2 is given by the following expression.
I ₀ = (V _T / R3) * ln (n) (4)
That is, the current I ₀ is inversely proportional to the resistance value of the resistor R3.

This current I ₀ becomes an output current of the current mirror circuit 20.
This output current I ₀ is input (supplied) to the current mirror circuit 10, folded, and output from an output terminal (not shown) connected to the point P 1, for example.

When the power supply voltage VDD fluctuates (changes) in the constant current source circuit configured as described above, the voltage V1 at the point P1 in FIG. 1 fluctuates, so that the voltage balance of the entire constant current source circuit is maintained. This content will be specifically described. In the resistor R2, the PMOS transistor M2, the NPN transistor Q2 and the resistor R0 connected in series in FIG. 1, the voltage applied to the resistor R2 is R2 · I ₀ and is applied between the source and drain of the PMOS transistor M2. The voltage VSD is VSG (I ₀ ), and the voltage Vd2 applied between the base and emitter of the NPN transistor Q2 is V _T * ln (I ₀ / nI _S ) as described above, and the resistance R0 voltage applied to is R0 * I _0. Since these are uniquely determined by the current I ₀ , they are constant regardless of fluctuations in the power supply voltage VDD.

Therefore, when the power supply voltage VDD drops, only the voltage VCB between the base and the collector of the NPN transistor Q2, that is, the voltage V1 at the point P1 drops.
Next, the operation of the PMOS transistor M3 will be described.

When the current I ₀ is zero, the gate-source voltage of the PMOS transistor M3 is equal to the gate-source voltage VSG1 of the PMOS transistors M1 and M2. The threshold voltages Vth of the PMOS transistors M1, M2, and M3 are all equal, and these PMOS transistors M1, M2, and M3 are turned on / off by the potential difference between the power supply voltage VDD and the voltage V1.

  As described above, when the power supply voltage VDD suddenly drops (here, “abruptly” means that the power supply voltage VDD drops more rapidly than the voltage V1 drops, and the voltage drop of the voltage V1 This means that the voltage drop of the power supply voltage VDD cannot be followed.) This potential difference decreases, and the PMOS transistors M1, M2, and M3 are turned off substantially simultaneously. That is, the PMOS transistor M3 constitutes detection means for detecting that the rate of decrease of the power supply voltage VDD is faster than the rate of decrease of the voltage V1 applied to the point P1.

Next, the operation of the constant current source circuit of the present invention when the power supply voltage is lowered will be described with reference to FIG.
FIG. 2 is a waveform diagram showing the state of each part when the power supply voltage drops in the constant current source circuit shown in FIG.

As shown in FIG. 2, the gate-source voltage VSG1 of the PMOS transistors M1 and M2 is represented by a potential difference between the power supply voltage VDD and the voltage V1 at the point P1.
In the section t1-t2, the power supply voltage VDD does not decrease, the potential difference between the power supply voltage VDD and the voltage V2 is maintained at a predetermined value or more, and the gates of the transistors M1 and M2 are turned on as the gate-source voltage VSG1. The voltage is higher than the threshold voltage Vth.

  Thereafter, when the power supply voltage VDD rapidly decreases at time t2, the gate-source voltage VSG1 decreases, and when the threshold voltage Vth becomes lower than the voltage VSG1 (time t21), the PMOS transistor M1 , M2 is turned off (blocked).

Then, as described above, since the base current is not supplied to the NPN transistors Q1 and Q2, conventionally, the current (emitter current) I ₀ does not flow, and the voltage V1 does not decrease any more. As a result, the voltage VSG1 does not increase, the PMOS transistors M1, M2, and the NPN transistors Q1, Q2 are settled off, the output current does not flow, and the constant current source circuit is stopped. .

  However, in this embodiment, the PMOS transistors M1 and M2 are turned off and simultaneously the PMOS transistor M3 is turned off, and the Lo signal is input to the inverter circuit configured by the PMOS transistor M4 and the NMOS transistor M5. Then, the output of this inverter circuit becomes Hi, and the NMOS transistor M6 is turned on.

  As a result, a discharge path is formed, and the voltage V1 applied to the point P1 is discharged to GND via the NMOS transistor M6. As a result, the voltage drop at the point P1 can follow the voltage drop of the power supply voltage VDD, the gate-source voltage VSG1 increases, and can exceed the threshold voltage Vth again at time t22. The base current is supplied to the NPN transistors Q1 and Q2, and the constant current source circuit is restarted.

  As described above, according to the present invention, by providing the operation stop prevention circuit 30, even when the power supply voltage VDD suddenly drops, a discharge path for the charge charged in the NPN transistor Q2 is secured, Since the voltage V1 decreases (because it shifts to the required potential level), the gate-source voltage VSG1 increases and can exceed the threshold voltage Vth again at time t22, making the constant current source circuit easy and It can be surely restarted.

(Second Embodiment)
Next, a second embodiment of the constant current source circuit of the present invention will be described.
FIG. 3 is a circuit diagram illustrating a constant current source circuit according to the second embodiment.

The following description will be made based on FIG. 3, but the description will focus on the points different from the first embodiment described above, and the description of the same matters will be omitted.
The constant current source circuit according to the second embodiment is different from the first embodiment in that a current mirror circuit 40 is provided instead of the current mirror circuit 10.

  In the current mirror circuit 40 shown in FIG. 3, a CMOS configuration including a PMOS transistor M11 and an NMOS transistor M13 is connected in series to the power supply voltage VDD and the collector of the NPN transistor Q1, while the PMOS transistor M12 and the NMOS transistor M14 are connected. The configured CMOS configuration is connected in series with the power supply voltage VDD and the collector of the NPN transistor Q2. That is, two CMOS configurations are connected in parallel to the power supply voltage VDD, and an intermediate contact of each CMOS configuration is connected to the gates of the NMOS transistors M13 and M14 and the gates of the PMOS transistors M11 and M12.

The currents flowing through the NPN transistors Q1 and Q2, that is, the current represented by the above-described equation (4) are input to the current mirror circuit 40, turned back, and output from the drain of the PMOS transistor M15. That is, the current mirror circuit 40 outputs a current I _{0 that} is inversely proportional to the resistance value of the resistor R3 as a constant current.

Also in such a modification, the same effect as the constant current source circuit of the first embodiment can be obtained.
The PMOS transistors M11, M12, and M15 can be replaced with PNP transistors, and the NMOS transistors M13 and M14 can be replaced with NPN transistors.

  The preferred embodiment of the present invention has been described in detail above, but the present invention is not limited to the specific embodiment.

1 is a circuit diagram illustrating a constant current source circuit according to a first embodiment. It is a wave form diagram which shows the mode of each part when the power supply voltage falls in the constant current source circuit shown in FIG. It is a circuit diagram which shows the constant current source circuit of 2nd Embodiment. It is a circuit diagram which shows the conventional constant current source circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Current mirror circuit 20 Current mirror circuit 30 Operation stop prevention circuit 40 Current mirror circuit 91 Current mirror circuit 92 Current mirror circuit I, I ₀ current M1, M2, M11, M12 PMOS transistor M13, M14 NMOS transistor Q1, Q2 NPN bipolar transistor V1 voltage VDD Power supply voltage

Claims (5)

In a constant current source circuit that outputs a constant current,
A current mirror circuit to which a power supply voltage is supplied; and
At least one bipolar transistor connected in series to the current mirror circuit for determining a current flowing in the current mirror circuit;
An operation stop prevention circuit that operates so as not to cut off the current flowing through the bipolar transistor when the power supply voltage drops;
A constant current source circuit comprising:   2. The constant current source circuit according to claim 1, wherein the current mirror circuit includes at least a pair of MOS transistors.   3. The constant current source according to claim 2, wherein the operation stop prevention circuit operates such that a potential difference between the power supply voltage and a collector voltage of the bipolar transistor is equal to or higher than a threshold voltage of each MOS transistor. circuit.   The operation stop prevention circuit has one end supplied with the power supply voltage and the other end connected to a connection between the current mirror circuit and the bipolar transistor, and a voltage drop rate applied to the connection 2. The constant current source circuit according to claim 1, wherein the voltage of the connection portion is connected to a reference potential when the power supply voltage drops more rapidly.   The operation stop prevention circuit is configured such that the difference between the voltage applied to the connection part and the power supply voltage is smaller than a predetermined voltage, so that the power supply voltage drop speed is lower than the voltage drop speed applied to the connection part. 5. The constant current source circuit according to claim 4, further comprising detection means for detecting that the current is fast.

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