JP2006210831A - Ic chip - Google Patents

Ic chip Download PDF

Info

Publication number
JP2006210831A
JP2006210831A JP2005023994A JP2005023994A JP2006210831A JP 2006210831 A JP2006210831 A JP 2006210831A JP 2005023994 A JP2005023994 A JP 2005023994A JP 2005023994 A JP2005023994 A JP 2005023994A JP 2006210831 A JP2006210831 A JP 2006210831A
Authority
JP
Japan
Prior art keywords
conductive adhesive
chip
conductive
bump
bumps
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2005023994A
Other languages
Japanese (ja)
Inventor
Noboru Eguchi
登 江口
Masaji Nakazono
正司 中園
Shintaro Takahashi
晋太郎 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Display Corp
Original Assignee
Kyocera Display Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Display Corp filed Critical Kyocera Display Corp
Priority to JP2005023994A priority Critical patent/JP2006210831A/en
Publication of JP2006210831A publication Critical patent/JP2006210831A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Landscapes

  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To lower occurrence of leak between adjacent bumps or electrodes by lowering the density of conductive particles in a bump forming region. <P>SOLUTION: On the entire circuit forming surface 9 in the substrate 8 of a driving IC chip 7, a nonconducting adhesive material 13 not containing conductive particles is arranged to cover a bump 10, and a conducting adhesive material 14 containing conductive particles 14a is arranged on the nonconducting adhesive material 13 in the bump forming region 11 on the circuit forming surface 9. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明はICチップに係り、特に、複数の導電粒子を含有する導電接着材を介してICチップのバンプと外部配線の電極とを接続するICチップに関する。   The present invention relates to an IC chip, and more particularly, to an IC chip that connects a bump of an IC chip and an electrode of an external wiring through a conductive adhesive containing a plurality of conductive particles.

従来より、例えば、中間に液晶を充填した一対の基板の所定の部分に選択的に電界を与えて特定の図形や文字等の情報を表示する表示パネルの基板上に、直接パネル駆動用ICチップ等のICチップを実装するCOG(Chip on Glass )方式の表示装置が携帯電話等の表示手段として用いられている。   Conventionally, for example, an IC chip for directly driving a panel on a substrate of a display panel that displays information such as specific figures and characters by selectively applying an electric field to a predetermined portion of a pair of substrates filled with liquid crystal in the middle. A COG (Chip on Glass) type display device on which an IC chip such as the above is mounted is used as a display means for a mobile phone or the like.

図5(a)(b)および(c)は、従来の表示パネルとパネル駆動用ICチップとの接続構造を示す模式的断面図である。   5A, 5B, and 5C are schematic cross-sectional views showing a connection structure between a conventional display panel and a panel driving IC chip.

図5(a)(b)および(c)に示すように、表示パネル21においては、一対の基板22の相互に対向する面にそれぞれ透明電極23が設けられており、前記透明電極23は、両基板22のうち平面形状において大きく形成された一方の基板22の端子部24に延設されて電極端子25とされている。また、パネル駆動用ICチップ27においては、基板28の回路形成面29における各端縁部分に、図示しない回路の電極に接続されたバンプ30が設けられている。   As shown in FIGS. 5A, 5B, and 5C, in the display panel 21, transparent electrodes 23 are provided on the mutually opposing surfaces of the pair of substrates 22, respectively. The both terminals 22 are extended to the terminal portion 24 of one of the substrates 22 that is formed to be large in plan view, thereby forming electrode terminals 25. In the panel driving IC chip 27, bumps 30 connected to electrodes of a circuit (not shown) are provided at each edge portion of the circuit forming surface 29 of the substrate 28.

このような表示パネル21の電極端子25とパネル駆動用ICチップ27のバンプ30とを接続する場合には、図5(a)に示すように、まず、表示パネル21の電極端子25上におけるパネル駆動用ICチップ27の圧着領域に、例えば複数の導電粒子34aが含有された熱硬化性樹脂34bからなる異方性導電膜(ACF:Anisotropic Conductive Film)等の導電接着材34を配設する。次に、図5(b)に示すように、表示パネル21の電極端子25とパネル駆動用ICチップ27のバンプ30との位置合わせを行いながら、導電接着材34を介して表示パネル21上にパネル駆動用ICチップ27を載置する。そして、図5(c)に示すように、パネル駆動用ICチップ27を加圧することにより、複数の導電粒子34aを介してバンプ30と電極端子25を接続して、表示パネル21とパネル駆動用ICチップ27とを電気的に接続する。   When the electrode terminals 25 of the display panel 21 and the bumps 30 of the panel driving IC chip 27 are connected, as shown in FIG. 5A, first, the panel on the electrode terminals 25 of the display panel 21 is displayed. A conductive adhesive 34 such as an anisotropic conductive film (ACF) made of a thermosetting resin 34b containing a plurality of conductive particles 34a, for example, is disposed in the pressure-bonding region of the driving IC chip 27. Next, as shown in FIG. 5B, the electrode terminals 25 of the display panel 21 and the bumps 30 of the panel driving IC chip 27 are aligned on the display panel 21 via the conductive adhesive 34. A panel driving IC chip 27 is placed. Then, as shown in FIG. 5C, by pressing the panel driving IC chip 27, the bumps 30 and the electrode terminals 25 are connected via the plurality of conductive particles 34a, and the display panel 21 and the panel driving chip are connected. The IC chip 27 is electrically connected.

しかし、前述の表示パネル21とパネル駆動用ICチップ27との接続方法によれば、導電接着材34を介して電極端子25の方向にパネル駆動用ICチップ27を加圧する際、図6に示すように、導電接着材34の熱硬化性樹脂34bがパネル駆動用ICチップ27の基板における外縁方向に流動する。すると、もともとは基板28における各バンプ30が形成された端縁部分であるバンプ形成領域31よりも内側に配置されていた各導電粒子34aが、熱硬化性樹脂34bとともに基板28における外縁方向に流動してバンプ形成領域31の内縁や隣位する各バンプ30間に滞留し、バンプ形成領域31において各導電粒子34aの密度が高くなってしまうおそれがあった。この結果、滞留した各導電粒子34aによって隣位するバンプ30間または電極端子25間においてリークが発生してしまうことがあるという問題を有していた。   However, according to the method for connecting the display panel 21 and the panel driving IC chip 27 described above, when the panel driving IC chip 27 is pressed in the direction of the electrode terminal 25 via the conductive adhesive 34, it is shown in FIG. Thus, the thermosetting resin 34 b of the conductive adhesive 34 flows toward the outer edge of the substrate of the panel driving IC chip 27. Then, the respective conductive particles 34a originally arranged on the inner side of the bump forming region 31 which is an edge portion where the respective bumps 30 are formed on the substrate 28 flow in the outer edge direction on the substrate 28 together with the thermosetting resin 34b. As a result, the inner edge of the bump formation region 31 or between the adjacent bumps 30 may remain, and the density of the conductive particles 34 a may increase in the bump formation region 31. As a result, there is a problem in that leakage may occur between the adjacent bumps 30 or between the electrode terminals 25 due to the accumulated conductive particles 34a.

また、近年の表示パネル21の表示の高精細化にともなう電極端子25の微細化により電極端子25とバンプ30との導通面積が狭くなってしまっている。このため、導電接着材34に含有される導電粒子34aの数量を増加して電極端子25とバンプ30とを確実に導通することも考えられているが、この場合、バンプ形成領域31における各導電粒子34aの密度はさらに高くなり、バンプ30間または電極端子25間におけるリークも一層発生してしまうおそれがある。さらに、各電極端子25の狭ピッチ化により、より一層バンプ30間または電極端子25間においてリークが発生しやすくなってしまうという問題があった。   In addition, the conductive area between the electrode terminals 25 and the bumps 30 has become narrow due to the miniaturization of the electrode terminals 25 accompanying the recent high definition of the display on the display panel 21. For this reason, it is considered that the number of the conductive particles 34a contained in the conductive adhesive 34 is increased so that the electrode terminals 25 and the bumps 30 are reliably connected. The density of the particles 34a is further increased, and there is a possibility that more leakage between the bumps 30 or between the electrode terminals 25 may occur. Furthermore, there is a problem that leakage is more likely to occur between the bumps 30 or between the electrode terminals 25 due to the narrowing of the pitch of each electrode terminal 25.

本発明はこれらの点に鑑みてなされたものであり、バンプ形成領域における各導電粒子の密度を低下させることにより、隣位するバンプ間または電極間におけるリークの発生を低下させることができるICチップを提供することを目的とする。   The present invention has been made in view of these points, and by reducing the density of each conductive particle in the bump formation region, an IC chip that can reduce the occurrence of leakage between adjacent bumps or electrodes. The purpose is to provide.

前記目的を達成するため、本発明に係るICチップの特徴は、基板の回路形成面に複数のバンプが設けられ、前記各バンプが外部配線の各電極と接続されるICチップにおいて、前記各バンプを覆うように前記回路形成面に導電粒子を含有しない無導電接着材が配設され、前記バンプの形成領域の前記無導電接着材上に、導電粒子を含有する導電接着材が配設されている点にある。   In order to achieve the above object, an IC chip according to the present invention is characterized in that a plurality of bumps are provided on a circuit forming surface of a substrate, and each bump is connected to each electrode of an external wiring. A non-conductive adhesive containing no conductive particles is disposed on the circuit forming surface so as to cover the conductive layer, and a conductive adhesive containing conductive particles is disposed on the non-conductive adhesive in the bump formation region. There is in point.

また、前記導電接着材は、前記バンプ上の前記無導電接着材上のみに配設されていてもよく、さらには、前記導電接着材の厚みは、前記導電粒子の直径寸法の2〜3倍であってもよい。   The conductive adhesive may be disposed only on the non-conductive adhesive on the bump, and the thickness of the conductive adhesive is 2 to 3 times the diameter of the conductive particles. It may be.

この本発明によれば、ICチップの基板における回路形成面には、バンプを覆うように無導電接着材が配設され、導電接着材はバンプ形成領域の無導電接着材上に配設されるようになっている。ここで、無導電接着材および導電接着材を介してICチップを外部配線の電極に加圧して接続させると、無導電接着材が基板の外縁方向に流動するが、無導電接着材には導電粒子が含有されていないので、バンプ形成領域の内縁や各バンプ間さらには各電極間に導電粒子が滞留してしまうのを防止することができる。   According to the present invention, a nonconductive adhesive is disposed on the circuit forming surface of the substrate of the IC chip so as to cover the bumps, and the conductive adhesive is disposed on the nonconductive adhesive in the bump forming region. It is like that. Here, when the IC chip is pressed and connected to the electrode of the external wiring via the non-conductive adhesive and the conductive adhesive, the non-conductive adhesive flows in the direction of the outer edge of the substrate. Since particles are not contained, it is possible to prevent the conductive particles from staying between the inner edge of the bump formation region, between the bumps, and between the electrodes.

以上述べたように、本発明に係るICチップによれば、バンプ形成領域の内縁等における各導電粒子の滞留の発生を防止することができるので、滞留した各導電粒子によって発生する各バンプ間または各電極間におけるリークを防止することができる。   As described above, according to the IC chip according to the present invention, it is possible to prevent the staying of each conductive particle at the inner edge of the bump forming region or the like, so that between each bump generated by each staying conductive particle or Leakage between the electrodes can be prevented.

以下、本発明に係るICチップの一実施形態を図1から図4を参照して説明する。ここで、本実施形態においては、外部配線としての表示パネルに、ICチップとしてのパネル駆動用ICチップを接続する場合を用いて説明するが、本実施形態はこれに限定されるものではなく、例えば、外部配線としてのフレキシブル配線基板等の配線基板にICチップを接続する場合等に用いてもよい。   Hereinafter, an embodiment of an IC chip according to the present invention will be described with reference to FIGS. Here, in the present embodiment, a case where a panel driving IC chip as an IC chip is connected to a display panel as external wiring will be described, but the present embodiment is not limited to this. For example, it may be used when an IC chip is connected to a wiring board such as a flexible wiring board as external wiring.

図1は、本実施形態に係るICチップの表示パネルとの一接続工程を示す模式的平面図であり、図1に示すように、表示パネル1においては、ガラス等からなる一対の透明基板2の相互に対向する面にそれぞれ透明電極3が設けられている。これら透明電極3は、両透明基板2のうち平面形状において大きく形成された一方の透明基板2の端子部4に延設されて、電極端子5とされている。   FIG. 1 is a schematic plan view showing one connection process of the IC chip and the display panel according to the present embodiment. As shown in FIG. 1, the display panel 1 includes a pair of transparent substrates 2 made of glass or the like. The transparent electrodes 3 are provided on the surfaces facing each other. These transparent electrodes 3 are extended to the terminal portion 4 of one transparent substrate 2 which is formed to be large in the planar shape out of the two transparent substrates 2, and serve as electrode terminals 5.

また、パネル駆動用ICチップ7においては、基板8の一面に回路が形成されており、基板8の回路形成面9における各端縁部分には、図示しない回路の電極に接続されたバンプ10が基板8から突出して設けられている。そして、回路形成面9における各バンプ10が形成された基板8の端縁部分はバンプ形成領域11とされている。   In the panel driving IC chip 7, a circuit is formed on one surface of the substrate 8, and bumps 10 connected to circuit electrodes (not shown) are formed on each edge portion of the circuit forming surface 9 of the substrate 8. Projecting from the substrate 8 is provided. And the edge part of the board | substrate 8 in which each bump 10 in the circuit formation surface 9 was formed is made into the bump formation area 11. FIG.

このパネル駆動用ICチップ7の回路形成面9には、バンプ10を覆うように導電粒子を含有しない熱硬化性樹脂13aからなる無導電接着材13が配設されており、バンプ形成領域11の無導電接着材13上には、熱硬化性樹脂14bに複数の導電粒子14aが含有された導電接着材14が配設されている。   On the circuit forming surface 9 of the panel driving IC chip 7, a non-conductive adhesive material 13 made of a thermosetting resin 13 a not containing conductive particles is disposed so as to cover the bumps 10. On the non-conductive adhesive 13, a conductive adhesive 14 in which a plurality of conductive particles 14a are contained in a thermosetting resin 14b is disposed.

次に、この表示パネル1とパネル駆動用ICチップ7との接続方法について図2を参照して説明する。   Next, a method of connecting the display panel 1 and the panel driving IC chip 7 will be described with reference to FIG.

図2(a)に示すように、まず、パネル駆動用ICチップ7の基板8における回路形成面9の一面に、所定の厚さ寸法の無導電接着材13を各バンプ10を覆うように塗布する。この無導電接着材13は、表示パネル1とパネル駆動用ICチップ7との確実な圧着に適当な量を塗布するようになっており、本実施形態においては、無導電接着材13を、バンプ10の高さ寸法よりも5〜10μm程度高くなるように塗布する。   As shown in FIG. 2A, first, a non-conductive adhesive 13 having a predetermined thickness is applied to one surface of the circuit forming surface 9 of the substrate 8 of the panel driving IC chip 7 so as to cover each bump 10. To do. The non-conductive adhesive 13 is applied in an appropriate amount for reliable crimping between the display panel 1 and the panel driving IC chip 7. In this embodiment, the non-conductive adhesive 13 is used as a bump. It is applied so as to be higher by about 5 to 10 μm than the height dimension of 10.

次に、図2(b)および図3に示すように、導電接着材14を、基板8の回路形成面9におけるバンプ形成領域11の全体に、無導電接着材13上から塗布する。この導電接着材14は、導電粒子14aの直径寸法以上の厚み寸法に塗布されることが好ましく、本実施形態においては、4〜10μmの直径寸法の導電粒子14aを用い、導電接着材14を、10〜15μm程度の厚み寸法となるように塗布する。また、導電接着材14を構成する樹脂としては、導電粒子14aの流動を防止するため、高粘度のものを用いることが望ましい。   Next, as shown in FIGS. 2B and 3, the conductive adhesive 14 is applied to the entire bump forming region 11 on the circuit forming surface 9 of the substrate 8 from above the nonconductive adhesive 13. The conductive adhesive 14 is preferably applied to a thickness dimension equal to or larger than the diameter dimension of the conductive particles 14a. In the present embodiment, the conductive adhesive 14 is used by using conductive particles 14a having a diameter of 4 to 10 μm. It applies so that it may become a thickness dimension of about 10-15 micrometers. Moreover, as resin which comprises the electrically conductive adhesive material 14, in order to prevent the flow of the electrically-conductive particle 14a, it is desirable to use a highly viscous thing.

また、本実施形態においては、熱硬化性樹脂からなる無導電接着材13および導電接着材14を用いているが、これに限定されるものではなく、無導電接着材13および導電接着材14に同質の材料を用いるものであれば、例えば、熱可塑性樹脂や紫外線硬化性樹脂等の種々の樹脂を用いることができる。   In the present embodiment, the non-conductive adhesive 13 and the conductive adhesive 14 made of thermosetting resin are used. However, the present invention is not limited to this, and the non-conductive adhesive 13 and the conductive adhesive 14 are used. As long as materials of the same quality are used, for example, various resins such as a thermoplastic resin and an ultraviolet curable resin can be used.

これにより、回路形成面9の所定の位置に無導電接着材13および導電接着材14が配設されたパネル駆動用ICチップ7を完成させる。   Thus, the panel driving IC chip 7 in which the nonconductive adhesive 13 and the conductive adhesive 14 are disposed at predetermined positions on the circuit forming surface 9 is completed.

続いて、図2(c)に示すように、表示パネル1の電極端子5とバンプ10との位置合わせを行いながら、無導電接着材13および導電接着材14を介して、前記パネル駆動用ICチップ7を、表示パネル1の端子部4上に載置する。   Subsequently, as shown in FIG. 2C, the panel driving IC is interposed through the non-conductive adhesive 13 and the conductive adhesive 14 while aligning the electrode terminals 5 and the bumps 10 of the display panel 1. The chip 7 is placed on the terminal portion 4 of the display panel 1.

そして、図2(d)に示すように、パネル駆動用ICチップ7上から電極端子5の方向に無導電接着材13および導電接着材14に所定の圧力および温度を加える。すると、まず、パネル駆動用ICチップ7上からの加圧により、各バンプ10と各電極端子5とが各導電粒子14aを介して当接し、各導電粒子14aは各バンプ10と各電極端子5とに挟持されるとともに、無導電接着材13がパネル駆動用ICチップ7の基板8における外縁方向に流動する。さらに、加熱によって無導電接着材13および導電接着材14の熱硬化性樹脂13a、14bを硬化させることにより、各バンプ10と各電極端子5とを各導電粒子14aを介して電気的に接続し、無導電接着材13および導電接着材14を介して表示パネル1とパネル駆動用ICチップ7を接続する。   Then, as shown in FIG. 2D, a predetermined pressure and temperature are applied to the non-conductive adhesive 13 and the conductive adhesive 14 in the direction from the panel driving IC chip 7 to the electrode terminal 5. Then, first, each bump 10 and each electrode terminal 5 come into contact with each other through each conductive particle 14 a by pressurization from above the panel driving IC chip 7, and each conductive particle 14 a is in contact with each bump 10 and each electrode terminal 5. And the non-conductive adhesive 13 flows in the direction of the outer edge of the substrate 8 of the panel driving IC chip 7. Further, the bumps 10 and the electrode terminals 5 are electrically connected through the conductive particles 14a by curing the thermosetting resins 13a and 14b of the non-conductive adhesive 13 and the conductive adhesive 14 by heating. The display panel 1 and the panel driving IC chip 7 are connected through the non-conductive adhesive 13 and the conductive adhesive 14.

本実施形態によれば、パネル駆動用ICチップ7の基板8における回路形成面9には、無導電接着材13が各バンプ10を覆うように塗布され、導電接着材14はバンプ形成領域11上の無導電接着材13上のみに塗布されるようになっている。このような、無導電接着材13および導電接着材14を介してパネル駆動用ICチップ7を電極端子5方向に加圧接続すると、無導電接着材13の熱硬化性樹脂13aが基板8の外縁方向に流動するが、無導電接着材13には導電粒子14aが含有されていないので、バンプ形成領域11の内縁や各バンプ10間さらには各電極端子5間における導電粒子14aの滞留の発生を防止することができる。   According to the present embodiment, the non-conductive adhesive 13 is applied to the circuit forming surface 9 of the substrate 8 of the panel driving IC chip 7 so as to cover the bumps 10, and the conductive adhesive 14 is placed on the bump forming region 11. It is applied only on the non-conductive adhesive 13. When the panel driving IC chip 7 is pressed and connected in the direction of the electrode terminal 5 through the non-conductive adhesive 13 and the conductive adhesive 14, the thermosetting resin 13 a of the non-conductive adhesive 13 is attached to the outer edge of the substrate 8. Although the non-conductive adhesive 13 does not contain the conductive particles 14a, the conductive particles 14a are prevented from staying between the inner edge of the bump forming region 11, the bumps 10, and the electrode terminals 5. Can be prevented.

また、無導電接着材13および導電接着材14を介してパネル駆動用ICチップ7を電極端子5に加圧接続する際、導電接着材14の各導電粒子14aは基板8から突出して形成されている各バンプ10によってまず加圧され、各バンプ10と各電極端子5とによって挟持される。このため、無導電接着材13および導電接着材14の各熱硬化性樹脂13a、14bの流動によって各導電粒子14aが基板8の外縁方向に流動することなく、各導電粒子14aを各バンプ10と各電極端子5との間に介在させることができる。   Further, when the panel driving IC chip 7 is pressure-connected to the electrode terminal 5 via the non-conductive adhesive 13 and the conductive adhesive 14, the conductive particles 14 a of the conductive adhesive 14 are formed so as to protrude from the substrate 8. The bumps 10 are first pressurized and sandwiched between the bumps 10 and the electrode terminals 5. For this reason, each conductive particle 14a does not flow in the direction of the outer edge of the substrate 8 due to the flow of each thermosetting resin 13a, 14b of the non-conductive adhesive 13 and the conductive adhesive 14, and each conductive particle 14a is connected to each bump 10. It can be interposed between each electrode terminal 5.

したがって、本実施形態における表示パネル1とパネル駆動用ICチップ7との接続方法によれば、バンプ形成領域11の内縁等における各導電粒子14aの滞留の発生を防止することができるので、滞留した各導電粒子14aによって発生する各バンプ10間または各電極端子5間におけるリークを防止することができる。これとともに、各バンプ10と各電極端子5との間に介在する各導電粒子14aによって、各バンプ10と各電極端子5とを確実に導通させることができる。   Therefore, according to the connection method between the display panel 1 and the panel driving IC chip 7 in the present embodiment, it is possible to prevent the conductive particles 14a from staying at the inner edge or the like of the bump forming region 11, and thus stayed. Leakage between the bumps 10 or between the electrode terminals 5 generated by the conductive particles 14a can be prevented. At the same time, each bump 10 and each electrode terminal 5 can be reliably conducted by each conductive particle 14 a interposed between each bump 10 and each electrode terminal 5.

また、表示パネル1における表示の精細化にともなう電極端子5の微細化に対応して、導電接着材14における導電粒子14aの含有密度を高くしても、回路形成面9におけるバンプ形成領域11の内側に導電接着材14は塗布されないので、回路形成面9におけるバンプ形成領域11の内縁や各バンプ10間等において各導電粒子14aの滞留が発生してしまうのを防止することができる。この結果、導電接着材14における導電粒子14aの含有密度を高くすることができるので、各バンプ10と各電極端子5とをより確実に導通させることができる。   Moreover, even if the density of the conductive particles 14a in the conductive adhesive 14 is increased in response to the miniaturization of the electrode terminals 5 accompanying the refinement of the display in the display panel 1, the bump formation region 11 on the circuit formation surface 9 is increased. Since the conductive adhesive 14 is not applied to the inside, it is possible to prevent the stagnation of the conductive particles 14a from occurring at the inner edge of the bump forming region 11 on the circuit forming surface 9 or between the bumps 10. As a result, since the content density of the conductive particles 14a in the conductive adhesive 14 can be increased, each bump 10 and each electrode terminal 5 can be more reliably conducted.

さらに、無導電接着材13を用いることにより、表示パネル1とパネル駆動用ICチップ7との接続に寄与しない導電粒子14aの数量を減少させることができるので、コストの低廉化を図ることができる。   Furthermore, by using the non-conductive adhesive 13, the number of conductive particles 14a that do not contribute to the connection between the display panel 1 and the panel driving IC chip 7 can be reduced, so that the cost can be reduced. .

さらにまた、従来は導電接着材14の塗布位置の精度上の問題から、各電極端子5上に塗布する導電接着材14の塗布領域を、パネル駆動用ICチップ7の基板8の面積よりも大きく設定しなければならなかった。一方、本実施形態によれば、無導電接着材13および導電接着材14はパネル駆動用ICチップ7に塗布されるので、導電接着材14等の塗布領域が基板8の面積よりも大きくなることはない。このように、導電接着材14等の塗布領域を従来と比較して狭くすることができるので、パネル駆動用ICチップ7が接続される表示パネル1の端子部4の面積を狭くすることができ、ひいては表示パネル1の狭額縁化を図ることができる。   Furthermore, conventionally, due to the problem of accuracy of the application position of the conductive adhesive 14, the application area of the conductive adhesive 14 applied on each electrode terminal 5 is larger than the area of the substrate 8 of the panel driving IC chip 7. Had to set. On the other hand, according to the present embodiment, since the non-conductive adhesive 13 and the conductive adhesive 14 are applied to the panel driving IC chip 7, the application region of the conductive adhesive 14 and the like is larger than the area of the substrate 8. There is no. As described above, since the application region of the conductive adhesive 14 or the like can be made narrower than in the conventional case, the area of the terminal portion 4 of the display panel 1 to which the panel driving IC chip 7 is connected can be reduced. As a result, the frame of the display panel 1 can be narrowed.

なお、本発明は前記実施形態に限定されるものではなく、必要に応じて種々変更することが可能である。   In addition, this invention is not limited to the said embodiment, A various change is possible as needed.

例えば、本実施形態においては、導電接着材14をバンプ形成領域11の全体に連続して塗布するものであるが、これに限定されず、図4に示すように、各バンプ10上のみに個別に導電接着材14を塗布してもよい。これにより、各バンプ10間または各電極端子5間に位置する各導電粒子14aの密度を低下させることができ、各バンプ10間および各電極端子5間のリークをより確実に防止することができる。   For example, in the present embodiment, the conductive adhesive 14 is continuously applied to the entire bump forming region 11. However, the present invention is not limited to this, and as shown in FIG. The conductive adhesive 14 may be applied to the substrate. Thereby, the density of each electroconductive particle 14a located between each bump 10 or between each electrode terminal 5 can be reduced, and the leak between each bump 10 and between each electrode terminal 5 can be prevented more reliably. .

本発明に係るICチップにおける外部配線との一接続工程を示す模式的平面図Schematic plan view showing one connection process with external wiring in the IC chip according to the present invention (a)は、図1のA−Aにおける一接続工程を示す模式的断面図、(b)は、図2(a)の次の接続工程を示す模式的断面図、(c)は、図2(b)の次の接続工程を示す模式的断面図、(d)は、図2(c)の次の接続工程を示す模式的断面図(A) is a schematic cross-sectional view showing one connection step in AA of FIG. 1, (b) is a schematic cross-sectional view showing the next connection step of FIG. 2 (a), and (c) is a diagram. 2 (b) is a schematic cross-sectional view showing the next connection step, and (d) is a schematic cross-sectional view showing the next connection step in FIG. 2 (c). 図1のB−Bにおける一接続工程を示す模式的断面図Typical sectional drawing which shows one connection process in BB of FIG. 本発明に係る他のICチップにおける外部配線との一接続工程を示す模式的断面図Typical sectional drawing which shows one connection process with the external wiring in the other IC chip concerning this invention (a)は、従来のICチップと外部配線との一接続工程を示す模式的断面図、(b)は、図5(a)の次の接続工程を示す模式的断面図、(c)は、図2(b)の次の接続工程を示す模式的断面図(A) is a schematic cross-sectional view showing one connection process between a conventional IC chip and external wiring, (b) is a schematic cross-sectional view showing the next connection process of FIG. 5 (a), and (c) is , A schematic cross-sectional view showing the next connection step of FIG. 図5の一接続工程を示す模式的平面図Schematic plan view showing one connection step of FIG.

符号の説明Explanation of symbols

1 表示パネル
2 透明基板
3 透明電極
4 端子部
5 電極端子
7 パネル駆動用ICチップ
8 基板
9 回路形成面
10 バンプ
11 バンプ形成領域
13 無導電接着材
13a 熱硬化性樹脂
14 導電接着材
14a 導電粒子
14b 熱硬化性樹脂
DESCRIPTION OF SYMBOLS 1 Display panel 2 Transparent substrate 3 Transparent electrode 4 Terminal part 5 Electrode terminal 7 Panel drive IC chip 8 Substrate 9 Circuit formation surface 10 Bump 11 Bump formation area 13 Non-conductive adhesive 13a Thermosetting resin 14 Conductive adhesive 14a Conductive particle 14b thermosetting resin

Claims (3)

基板の回路形成面に複数のバンプが設けられ、前記各バンプが外部配線の各電極と接続されるICチップにおいて、
前記各バンプを覆うように前記回路形成面に導電粒子を含有しない無導電接着材が配設され、前記バンプの形成領域の前記無導電接着材上に、導電粒子を含有する導電接着材が配設されていることを特徴とするICチップ。
In an IC chip in which a plurality of bumps are provided on the circuit forming surface of the substrate, and each bump is connected to each electrode of external wiring.
A non-conductive adhesive containing no conductive particles is disposed on the circuit forming surface so as to cover the bumps, and a conductive adhesive containing conductive particles is disposed on the non-conductive adhesive in the bump formation region. An IC chip characterized by being provided.
前記導電接着材は、前記バンプ上の前記無導電接着材上のみに配設されている請求項1に記載のICチップ。   The IC chip according to claim 1, wherein the conductive adhesive is disposed only on the nonconductive adhesive on the bump. 前記導電接着材の厚みは、前記導電粒子の直径寸法の2〜3倍である請求項1または2に記載のICチップ。   The IC chip according to claim 1 or 2, wherein the thickness of the conductive adhesive is 2 to 3 times the diameter of the conductive particles.
JP2005023994A 2005-01-31 2005-01-31 Ic chip Pending JP2006210831A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005023994A JP2006210831A (en) 2005-01-31 2005-01-31 Ic chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005023994A JP2006210831A (en) 2005-01-31 2005-01-31 Ic chip

Publications (1)

Publication Number Publication Date
JP2006210831A true JP2006210831A (en) 2006-08-10

Family

ID=36967287

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005023994A Pending JP2006210831A (en) 2005-01-31 2005-01-31 Ic chip

Country Status (1)

Country Link
JP (1) JP2006210831A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015213157A (en) * 2014-04-14 2015-11-26 日亜化学工業株式会社 Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015213157A (en) * 2014-04-14 2015-11-26 日亜化学工業株式会社 Semiconductor device
US10290778B2 (en) 2014-04-14 2019-05-14 Nichia Corporation Semiconductor device having semiconductor element bonded to base body by adhesive member
US10978623B2 (en) 2014-04-14 2021-04-13 Nichia Corporation Light emitting element including adhesive member containing particles

Similar Documents

Publication Publication Date Title
US7208835B2 (en) Integrated circuit package and assembly thereof
JP4968665B2 (en) Flat display panel and connection structure
KR101857331B1 (en) Anisotropic conductive film, method for producing anisotropic conductive film, method for producing connection body, and connection method
KR20170139217A (en) Display device and method for manufacturing the same
KR20040108612A (en) Anisotropic conductive material body, display apparatus, method for producing the display apparatus, and conductive member
JP6006955B2 (en) Manufacturing method of connecting body, connecting method
JP2009054833A (en) Ectronic device and its manufacturing emthod, electrooptical device, and electronic device
JP2015076486A (en) Display device
US9477123B2 (en) Liquid crystal display device and production method thereof
JP2006210831A (en) Ic chip
JP2009295857A (en) Connecting structure of ic chip and external wiring, and ic chip
KR100807352B1 (en) Electrode having projections on electrode pad, electronic apparatus including device mounting structure having the same and method of mounting device of electronic apparatus
JP2005129757A (en) Method of connecting semiconductor device
JP2005167274A (en) Semiconductor device, method for manufacturing same, and liquid crystal display device
JP2005268590A (en) Anisotropic conducting film, packaging structure using it, and display unit
JP2002344097A (en) Mounting substrate and display device having the same
KR102579426B1 (en) Display device and manufacturing method thereof
JP2005122078A (en) Liquid crystal display and method for manufacturing the same
KR20220106049A (en) Display device and manufacturing method thereof
JP4484750B2 (en) WIRING BOARD, ELECTRONIC CIRCUIT ELEMENT HAVING THE SAME, AND DISPLAY DEVICE
JP2005191386A (en) Electrode connecting method and method for manufacturing liquid crystal display element
JP2006237484A (en) Semiconductor chip, its manufacturing method and indicating panel
KR20090094622A (en) Conductive ball with easily pressed down, method of mamufacturing thereof and anisotropic conductive film using the same
KR20090132931A (en) Semiconductor device having electrode attached polymer particle and semiconductor package using the same
KR100761596B1 (en) Semiconductor device having tuberous electrode and Semiconductor package using the same