JP2006203261A - Semiconductor apparatus - Google Patents

Semiconductor apparatus Download PDF

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JP2006203261A
JP2006203261A JP2006122442A JP2006122442A JP2006203261A JP 2006203261 A JP2006203261 A JP 2006203261A JP 2006122442 A JP2006122442 A JP 2006122442A JP 2006122442 A JP2006122442 A JP 2006122442A JP 2006203261 A JP2006203261 A JP 2006203261A
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electrode terminal
semiconductor device
solder balls
signal
solder
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Takashi Nakamura
尚 中村
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Renesas Technology Corp
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Renesas Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

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Abstract

<P>PROBLEM TO BE SOLVED: To obtain a semiconductor apparatus which is formed in a plate mounting package of BGA, CSP or the like and is capable of preventing short-circuit between a power supply electrode terminal and an earth electrode terminal. <P>SOLUTION: A solder ball 3c configuring at least one signal electrode terminal is provided by disposing it between the solder ball 3a configuring the power supply electrode terminal and the solder ball 3b configuring the earth electrode terminal in the solder balls 3 formed on a mounting surface 6 of the package 2. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体装置に関し、特にＢＧＡ（Ball Grid Array）、ＣＳＰ（Chip Scale Package）等、外部電極端子に半田ボールを使用した多ピンの面実装パッケージにおける電極配置に関するものである。   The present invention relates to a semiconductor device, and more particularly to electrode arrangement in a multi-pin surface mount package using solder balls as external electrode terminals, such as BGA (Ball Grid Array) and CSP (Chip Scale Package).

メモリＩＣやＡＳＩＣ等の分野では、高速化、多ピン化及び小型化の要求から、従来のＱＦＰ等のような外部電極端子にピンを使用したパッケージでは対応できなくなっていた。このため、外部電極端子に半田ボールを使用したＢＧＡ、ＣＳＰ等のような薄く小形で外部電極端子数の多いパッケージが開発され、このようなパッケージでは、多端子化及び小型化を行うために、外部電極端子をなす半田ボールのピッチは１ｍｍ以下となるように形成されていた。   In the fields of memory ICs, ASICs, and the like, due to demands for high speed, multiple pins, and miniaturization, conventional packages using pins for external electrode terminals such as QFP cannot be used. For this reason, a thin and small package with a large number of external electrode terminals such as BGA, CSP, etc. using solder balls as external electrode terminals has been developed. In such a package, in order to increase the number of terminals and reduce the size, The pitch of the solder balls forming the external electrode terminal was formed to be 1 mm or less.

図７は、従来の半導体装置における実装面の例を示した平面図である。図７において、半導体装置１００は、パッケージ１０１における実装面１０２上にそれぞれの外部電極端子をなす各半田ボールがそれぞれ形成されている。実装面１０２上に形成された各半田ボールは、電源電極端子をなす半田ボール１０３ａ、アース電極端子をなす半田ボール１０３ｂ、並びに電源電極端子及びアース電極端子以外の外部電極端子である信号電極端子をなす半田ボール１０３ｃからなる。   FIG. 7 is a plan view showing an example of a mounting surface in a conventional semiconductor device. In FIG. 7, in the semiconductor device 100, each solder ball that forms each external electrode terminal is formed on the mounting surface 102 of the package 101. Each solder ball formed on the mounting surface 102 includes a solder ball 103a that forms a power electrode terminal, a solder ball 103b that forms a ground electrode terminal, and a signal electrode terminal that is an external electrode terminal other than the power electrode terminal and the ground electrode terminal. It consists of a formed solder ball 103c.

なお、従来において、本発明と目的が異なるが、電源リードと接地リードとの間に２本の信号リードを配置することによって、電源電位及び接地電位の変動を抑えてトランジスタの誤動作を防止した、外部電極端子にリードを使用する半導体装置があった（例えば、特許文献１参照。）。
特開平６−１５１６８８号公報 Conventionally, although the object is different from the present invention, by arranging two signal leads between the power supply lead and the ground lead, fluctuations in the power supply potential and the ground potential are suppressed to prevent the malfunction of the transistor. There has been a semiconductor device that uses a lead for an external electrode terminal (see, for example, Patent Document 1).
JP-A-6-151688

ここで、半田ボール間のピッチが１ｍｍ以下になると、実装の際に半田ショートや、固定異物又は可動異物による電極端子間のショートが発生しやすくなる。しかし、ＢＧＡやＣＳＰ等の面実装パッケージにおいては、このようなショートを、ＱＦＰ等のピンを使用したパッケージのように目視やプロービングで発見することは不可能である。このため、ＢＧＡやＣＳＰ等の面実装パッケージにおける電極端子間のショート等の接続不良を検出する方法として、バウンダリスキャンがあった。   Here, when the pitch between the solder balls is 1 mm or less, a solder short or a short between the electrode terminals due to a fixed foreign matter or a movable foreign matter tends to occur during mounting. However, in a surface mount package such as BGA or CSP, such a short circuit cannot be found by visual observation or probing like a package using pins such as QFP. For this reason, there is a boundary scan as a method for detecting a connection failure such as a short circuit between electrode terminals in a surface mount package such as BGA or CSP.

上記バウンダリスキャンは、電源電極端子及びアース電極端子以外の外部電極端子である信号電極端子が絡んだショート、すなわち、信号電極端子間、信号電極端子と電源電極端子との間、及び信号電極端子とアース電極端子との間で生じたショートを電気的に検出することができる。しかし、図７で示したように、半田ボール１０３ａ及び１０３ｂを隣接させて形成した場合、半田ボールのピッチが１ｍｍ以下になると、電源電極端子とアース電極端子との間で半田くず等の異物によってショートする可能性が大きくなる。これに対して、電源電極端子とアース電極端子との間で生じたショートは、バウンダリスキャンでは検出することができないという問題があった。   The boundary scan is a short circuit involving signal electrode terminals that are external electrode terminals other than the power electrode terminal and the ground electrode terminal, that is, between the signal electrode terminals, between the signal electrode terminal and the power electrode terminal, and the signal electrode terminal. A short circuit occurring between the ground electrode terminal and the ground electrode terminal can be detected electrically. However, as shown in FIG. 7, when the solder balls 103a and 103b are formed adjacent to each other, when the pitch of the solder balls becomes 1 mm or less, foreign matter such as solder scraps between the power electrode terminal and the ground electrode terminal. The possibility of short-circuiting increases. On the other hand, there is a problem that a short circuit generated between the power electrode terminal and the ground electrode terminal cannot be detected by the boundary scan.

本発明は、上記のような問題を解決するためになされたものであり、ＢＧＡやＣＳＰ等の面実装パッケージで形成され、電源電極端子及びアース電極端子の間でのショートを防止することができる半導体装置を得ることを目的とする。   The present invention has been made to solve the above problems, and is formed of a surface mount package such as BGA or CSP, and can prevent a short circuit between a power electrode terminal and a ground electrode terminal. An object is to obtain a semiconductor device.

この発明に係る半導体装置は、アース電極端子をなす複数のアース用半田ボールと、電源電極端子をなす複数の電源用半田ボールと、信号電極端子をなす複数の信号用半田ボールとをパッケージの実装面上に有する半導体装置であって、
すべての前記アース用半田ボールは、それぞれ、最も近接する信号用半田ボールまでのピッチが１ｍｍ以下であり、かつ、最も近接する電源用半田ボールまでのピッチが、前記最も近接する信号用半田ボールまでのピッチの２倍以上になるように配置されるものである。 A semiconductor device according to the present invention includes a plurality of ground solder balls forming ground electrode terminals, a plurality of power solder balls forming power electrode terminals, and a plurality of signal solder balls forming signal electrode terminals. A semiconductor device having on a surface,
All the grounding solder balls each have a pitch of 1 mm or less to the nearest signal solder ball, and the pitch to the nearest power supply solder ball reaches the nearest signal solder ball. It is arranged so as to be twice or more of the pitch of.

また、この発明に係る半導体装置は、アース電極端子をなす複数のアース用半田ボールと、電源電極端子をなす複数の電源用半田ボールと、信号電極端子をなす複数の信号用半田ボールとをパッケージの実装面上に有する半導体装置であって、
すべての前記アース用半田ボールは、それぞれ、最も近接する信号用半田ボールまでの距離が１ｍｍ以下であり、かつ、最も近接する前記電源用半田ボールとの間に前記最も近接する信号用半田ボールの少なくとも１つが配置されるものである。 According to another aspect of the present invention, there is provided a semiconductor device including a plurality of grounding solder balls forming ground electrode terminals, a plurality of power solder balls forming power electrode terminals, and a plurality of signal solder balls forming signal electrode terminals. A semiconductor device on the mounting surface,
Each of the grounding solder balls has a distance of 1 mm or less to the nearest signal solder ball, and the nearest signal solder ball is between the nearest power supply solder ball. At least one is arranged.

また、この発明に係る半導体装置は、請求項２において、すべての前記アース用半田ボールは、それぞれ、前記最も近接する電源用半田ボールまでのピッチが、前記最も近接する信号用半田ボールまでのピッチの２倍以上になるように配置されるものである。   The semiconductor device according to the present invention is the semiconductor device according to claim 2, wherein all the grounding solder balls have a pitch to the nearest power supply solder ball, and a pitch to the nearest signal soldering ball. It is arranged so as to be twice or more of.

また、この発明に係る半導体装置は、請求項１、２又は３において、配線パターンを有する実装基板を有し、前記複数のアース用半田ボール、前記複数の電源用半田ボール及び前記複数の信号用半田ボールは、前記実装基板上の配線パターンに、加熱されて熱溶融することによって接続されたものである。   According to a second aspect of the present invention, there is provided a semiconductor device comprising: a mounting substrate having a wiring pattern; and the plurality of grounding solder balls, the plurality of power supply solder balls, and the plurality of signals. The solder ball is connected to the wiring pattern on the mounting substrate by being heated and melted.

この発明に係る半導体装置は、極性の異なる電源電極端子を隣接させないように、各外部電極端子を配置したことから、実装基板に実装した後、バウンダリスキャンで検出することができなかった電源電極端子とアース電極端子とのショートを発生し難くすることができ、バウンダリスキャンによる各電極端子間で生じたショート検出率を大幅に向上させ、半導体装置の実装時の信頼性を大幅に向上させることができる。   In the semiconductor device according to the present invention, since the external electrode terminals are arranged so that the power electrode terminals having different polarities are not adjacent to each other, the power electrode terminals that could not be detected by the boundary scan after being mounted on the mounting board And the ground electrode terminal can be made difficult to occur, the detection rate of the short circuit between each electrode terminal by the boundary scan can be greatly improved, and the reliability when mounting the semiconductor device can be greatly improved. it can.

また、上記面実装パッケージにおける外部電極端子の半田ボールピッチは、１ｍｍ以下である。このことから、外部電極端子間のショートを引き起こす半田くず等の異物は、大きさが１ｍｍ以下であり、半田くず等の異物によって外部電極端子間がショートしたとしても、電源電極端子とアース電極端子との間でショートが発生せず、電源電極端子と信号電極端子との間、又はアース電極端子と信号電極端子との間で生じるショートである。このため、これらの電極端子間のショートは、バウンダリスキャンで検出することができ、半導体装置の実装時の信頼性を大幅に向上させることができる。   The solder ball pitch of the external electrode terminals in the surface mount package is 1 mm or less. For this reason, foreign matter such as solder scraps causing a short circuit between external electrode terminals is 1 mm or less in size, and even if the external electrode terminals are short-circuited by foreign substances such as solder scraps, the power electrode terminal and the ground electrode terminal Between the power electrode terminal and the signal electrode terminal, or between the ground electrode terminal and the signal electrode terminal. For this reason, a short circuit between these electrode terminals can be detected by boundary scan, and the reliability at the time of mounting a semiconductor device can be greatly improved.

また、極性の異なる電源電極端子間に、電源電極端子とは異なる少なくとも１つの信号電極端子を設けるように、上記各外部電極端子を配置した。このことから、電源電極端子とアース電極端子との間でショートが発生し難く、半田くず等の異物によって生じる外部電極端子間のショートは、ほとんどすべて電源電極端子と信号電極端子との間、又はアース電極端子と信号電極端子との間で生じるショートである。このため、これらの電極端子間のショートは、バウンダリスキャンで検出することができ、半導体装置の実装時の信頼性を大幅に向上させることができる。   The external electrode terminals are arranged so that at least one signal electrode terminal different from the power electrode terminal is provided between the power electrode terminals having different polarities. From this, it is difficult for a short circuit to occur between the power electrode terminal and the ground electrode terminal, and almost all short circuits between external electrode terminals caused by foreign matters such as solder scraps are between the power electrode terminal and the signal electrode terminal, or This is a short circuit that occurs between the ground electrode terminal and the signal electrode terminal. For this reason, a short circuit between these electrode terminals can be detected by boundary scan, and the reliability at the time of mounting a semiconductor device can be greatly improved.

次に、図面に示す実施の形態に基づいて、本発明を詳細に説明する。
実施の形態１．
図１は、本発明の実施の形態１における半導体装置の例を示した斜視図であり、図２は、図１で示した半導体装置の側面図である。図１及び図２において、半導体装置１は、パッケージ２における実装面上にそれぞれの外部電極端子をなす各半田ボール３がそれぞれ形成されており、ＢＧＡ又はＣＳＰ等で形成されている。該各半田ボール３は、１ｍｍ以下のピッチでそれぞれ形成されており、例えば１.５ｃｍ角の実装面を有するパッケージ２において、該実装面上には１５０個以上の半田ボール３が形成されている。なお、本実施の形態１においては、分かりやすいように半田ボール３の数を少なく示している。 Next, the present invention will be described in detail based on the embodiments shown in the drawings.
Embodiment 1 FIG.
FIG. 1 is a perspective view showing an example of a semiconductor device according to Embodiment 1 of the present invention, and FIG. 2 is a side view of the semiconductor device shown in FIG. 1 and 2, in the semiconductor device 1, each solder ball 3 that forms each external electrode terminal is formed on the mounting surface of the package 2, and is formed of BGA, CSP, or the like. Each solder ball 3 is formed at a pitch of 1 mm or less. For example, in a package 2 having a 1.5 cm square mounting surface, 150 or more solder balls 3 are formed on the mounting surface. . In the first embodiment, the number of solder balls 3 is reduced for easy understanding.

図３は、図１及び図２で示した半導体装置１を実装基板上に実装した状態を示す側面図である。図３において、実装基板５上に形成された配線パターン（図示せず）における所定の位置に配置された各半田ボール３は、加熱されて熱溶融することによって実装基板５上にそれぞれ接続される。
図４は、半導体装置１における実装面の例を示した平面図である。図４において、パッケージ２の実装面６上に形成された各半田ボール３は、電源電極端子をなす半田ボール３ａ、アース電極端子をなす半田ボール３ｂ、並びに電源電極端子及びアース電極端子以外の外部電極端子である信号電極端子をなす半田ボール３ｃで構成されている。 FIG. 3 is a side view showing a state where the semiconductor device 1 shown in FIGS. 1 and 2 is mounted on a mounting substrate. In FIG. 3, each solder ball 3 arranged at a predetermined position in a wiring pattern (not shown) formed on the mounting substrate 5 is connected to the mounting substrate 5 by being heated and melted. .
FIG. 4 is a plan view showing an example of a mounting surface in the semiconductor device 1. In FIG. 4, each solder ball 3 formed on the mounting surface 6 of the package 2 includes a solder ball 3a that forms a power electrode terminal, a solder ball 3b that forms a ground electrode terminal, and external parts other than the power electrode terminal and the ground electrode terminal. It is comprised by the solder ball 3c which makes the signal electrode terminal which is an electrode terminal.

半田ボール３ａと３ｂとの間には、少なくとも１つの半田ボール３ｃが設けられており、半田ボール３ａと３ｂが隣接しないように半田ボール３ａ〜３ｃがそれぞれ配置されて形成されている。このようにすることによって、外部電極端子間のショートを引き起こす半田くず等の異物は、大きさが１ｍｍ以下であることから、半田くず等の異物によって外部電極端子間がショートしたとしても、ほとんどすべて電源電極端子と信号電極端子との間、又はアース電極端子と信号電極端子との間で生じるショートであり、電源電極端子とアース電極端子との間でショートが発生し難い。このため、これらの電極端子間のショートは、バウンダリスキャンで検出することができる。   At least one solder ball 3c is provided between the solder balls 3a and 3b, and the solder balls 3a to 3c are arranged so that the solder balls 3a and 3b are not adjacent to each other. By doing this, foreign matter such as solder scraps that cause a short circuit between external electrode terminals is 1 mm or less in size, so even if the external electrode terminals are short-circuited by foreign substances such as solder scraps, almost all This is a short circuit that occurs between the power electrode terminal and the signal electrode terminal or between the ground electrode terminal and the signal electrode terminal, and it is difficult for a short circuit to occur between the power electrode terminal and the ground electrode terminal. For this reason, a short circuit between these electrode terminals can be detected by a boundary scan.

なお、外部電極端子間のショートを引き起こす半田くず等の異物は、通常大きさが１ｍｍ以下であることから、半田ボール３ａと３ｂとの間の間隔を電極端子間のショートが発生し難くなるぐらいまで広げるようにしてもよい。図５及び図６は、このようにした場合の半導体装置１の実装面の例を示した平面図である。図５では、半田ボール３ａと半田ボール３ｂとの間は、一定の半田ボールピッチに対して少なくとも１つ以上半田ボール３を設けないようにしており、このようにすることによって、電源電極端子とアース電極端子との間でショートが発生し難くすることができる。また図６では、半田ボール３ａと半田ボール３ｂとの間のみ半田ボールピッチを大きくしており、このようにすることによって、電源電極端子とアース電極端子との間でショートが発生し難くすることができる。   Incidentally, foreign matters such as solder scraps that cause a short circuit between the external electrode terminals are usually 1 mm or less in size, so that it is difficult for the short circuit between the electrode terminals to occur between the solder balls 3a and 3b. You may make it extend to. 5 and 6 are plan views showing examples of the mounting surface of the semiconductor device 1 in such a case. In FIG. 5, between the solder balls 3a and the solder balls 3b, at least one or more solder balls 3 are not provided with respect to a constant solder ball pitch. It is possible to make it difficult for a short circuit to occur with the ground electrode terminal. In FIG. 6, the solder ball pitch is increased only between the solder balls 3a and 3b. By doing so, it is difficult to cause a short circuit between the power electrode terminal and the ground electrode terminal. Can do.

このように、本発明の実施の形態１における半導体装置は、パッケージ２の実装面６上に形成する半田ボール３において、電源電極端子をなす半田ボール３ａとアース電極端子をなす半田ボール３ｂとの間に、少なくとも１つの信号電極端子をなす半田ボール３ｃを配置して設けるようにした、このことから、実装基板に実装した後、バウンダリスキャンで検出することができなかった電源電極端子とアース電極端子とのショートを発生し難くすることができ、バウンダリスキャンによる各電極端子間で生じたショート検出率を大幅に向上させ、半導体装置の実装時の信頼性を大幅に向上させることができる。   As described above, in the semiconductor device according to the first embodiment of the present invention, the solder ball 3 formed on the mounting surface 6 of the package 2 includes the solder ball 3a serving as the power electrode terminal and the solder ball 3b serving as the ground electrode terminal. A solder ball 3c forming at least one signal electrode terminal is disposed between the power supply electrode terminal and the ground electrode which cannot be detected by the boundary scan after being mounted on the mounting board. A short circuit with a terminal can be made difficult to occur, a detection rate of a short circuit generated between each electrode terminal by a boundary scan can be greatly improved, and reliability at the time of mounting a semiconductor device can be greatly improved.

本発明の実施の形態１における半導体装置の例を示した斜視図である。It is the perspective view which showed the example of the semiconductor device in Embodiment 1 of this invention. 図１で示した半導体装置の側面図である。FIG. 2 is a side view of the semiconductor device shown in FIG. 1. 図１及び図２で示した半導体装置１を実装基板上に実装した状態を示す側面図である。It is a side view which shows the state which mounted the semiconductor device 1 shown in FIG.1 and FIG.2 on the mounting board | substrate. 図１及び図２で示した半導体装置１における実装面の例を示した平面図である。FIG. 3 is a plan view illustrating an example of a mounting surface in the semiconductor device 1 illustrated in FIGS. 1 and 2. 図１及び図２で示した半導体装置１の実装面の他の例を示した平面図である。FIG. 4 is a plan view illustrating another example of the mounting surface of the semiconductor device 1 illustrated in FIGS. 1 and 2. 図１及び図２で示した半導体装置１の実装面の他の例を示した平面図である。FIG. 4 is a plan view illustrating another example of the mounting surface of the semiconductor device 1 illustrated in FIGS. 1 and 2. 従来の半導体装置における実装面の例を示した平面図である。It is the top view which showed the example of the mounting surface in the conventional semiconductor device.

符号の説明Explanation of symbols

１ 半導体装置、 ２ パッケージ、 ３ 半田ボール、 ３ａ 電源電極端子をなす半田ボール、 ３ｂ アース電極端子をなす半田ボール、 ３ｃ 信号電極端子をなす半田ボール、 ６ 実装面
DESCRIPTION OF SYMBOLS 1 Semiconductor device, 2 Package, 3 Solder ball, 3a Solder ball which forms power supply electrode terminal, 3b Solder ball which forms ground electrode terminal, 3c Solder ball which forms signal electrode terminal, 6 Mounting surface

Claims (4)

アース電極端子をなす複数のアース用半田ボールと、電源電極端子をなす複数の電源用半田ボールと、信号電極端子をなす複数の信号用半田ボールとをパッケージの実装面上に有する半導体装置であって、
すべての前記アース用半田ボールは、それぞれ、最も近接する信号用半田ボールまでのピッチが１ｍｍ以下であり、かつ、最も近接する電源用半田ボールまでのピッチが、前記最も近接する信号用半田ボールまでのピッチの２倍以上になるように配置されることを特徴とする半導体装置。 A semiconductor device having a plurality of ground solder balls forming ground electrode terminals, a plurality of power solder balls forming power electrode terminals, and a plurality of signal solder balls forming signal electrode terminals on a package mounting surface. And
All the grounding solder balls each have a pitch of 1 mm or less to the nearest signal solder ball, and the pitch to the nearest power supply solder ball reaches the nearest signal solder ball. A semiconductor device, wherein the semiconductor device is disposed so as to be twice or more the pitch of the above. アース電極端子をなす複数のアース用半田ボールと、電源電極端子をなす複数の電源用半田ボールと、信号電極端子をなす複数の信号用半田ボールとをパッケージの実装面上に有する半導体装置であって、
すべての前記アース用半田ボールは、それぞれ、最も近接する信号用半田ボールまでの距離が１ｍｍ以下であり、かつ、最も近接する前記電源用半田ボールとの間に前記最も近接する信号用半田ボールの少なくとも１つが配置されることを特徴とする半導体装置。 A semiconductor device having a plurality of ground solder balls forming ground electrode terminals, a plurality of power solder balls forming power electrode terminals, and a plurality of signal solder balls forming signal electrode terminals on a package mounting surface. And
Each of the grounding solder balls has a distance to the nearest signal solder ball of 1 mm or less, and the nearest signal solder ball is between the nearest power supply solder ball. At least one semiconductor device is arranged. すべての前記アース用半田ボールは、それぞれ、前記最も近接する電源用半田ボールまでのピッチが、前記最も近接する信号用半田ボールまでのピッチの２倍以上になるように配置されることを特徴とする請求項２記載の半導体装置。   All the grounding solder balls are arranged such that the pitch to the nearest power supply solder ball is at least twice the pitch to the nearest signal soldering ball. The semiconductor device according to claim 2. 配線パターンを有する実装基板を有し、前記複数のアース用半田ボール、前記複数の電源用半田ボール及び前記複数の信号用半田ボールは、前記実装基板上の配線パターンに、加熱されて熱溶融することによって接続されたものであることを特徴とする請求項１、２又は３記載の半導体装置。
A mounting board having a wiring pattern, wherein the plurality of grounding solder balls, the plurality of power supply solder balls, and the plurality of signal soldering balls are heated and thermally melted by the wiring pattern on the mounting board; The semiconductor device according to claim 1, wherein the semiconductor devices are connected by each other.
JP2006122442A 2006-04-26 2006-04-26 Semiconductor apparatus Pending JP2006203261A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009071982A2 (en) * 2007-12-04 2009-06-11 Ati Technologies Ulc Under bump routing layer method and apparatus
US8294266B2 (en) 2007-08-01 2012-10-23 Advanced Micro Devices, Inc. Conductor bump method and apparatus
US8314474B2 (en) 2008-07-25 2012-11-20 Ati Technologies Ulc Under bump metallization for on-die capacitor
WO2013133122A1 (en) * 2012-03-07 2013-09-12 三菱電機株式会社 High-frequency package

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8294266B2 (en) 2007-08-01 2012-10-23 Advanced Micro Devices, Inc. Conductor bump method and apparatus
WO2009071982A2 (en) * 2007-12-04 2009-06-11 Ati Technologies Ulc Under bump routing layer method and apparatus
WO2009071982A3 (en) * 2007-12-04 2009-07-23 Ati Technologies Ulc Under bump routing layer method and apparatus
US8314474B2 (en) 2008-07-25 2012-11-20 Ati Technologies Ulc Under bump metallization for on-die capacitor
WO2013133122A1 (en) * 2012-03-07 2013-09-12 三菱電機株式会社 High-frequency package
US9368457B2 (en) 2012-03-07 2016-06-14 Mitsubishi Electric Corporation High-frequency package

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