JP2006203058A - Light emitting device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a light emitting device which has a simple structure, is easily manufactured, and can stably obtain a large luminous efficiency over a long period of time. <P>SOLUTION: The light emitting device contains a nitride semiconductor substrate (GaN substrate), a nitride semiconductor layer laminated on the first main surface of the nitride semiconductor substrate, and a second electrode (n electrode 11) formed on a second main surface as a main surface opposed to the first main surface of the nitride semiconductor substrate. The nitride semiconductor substrate contains an area (plate-like crystal reversal area 51) where a dislocation bundle exists to concentrate a dislocation along a thickness direction from the first main surface of the nitride semiconductor substrate to the second main surface; and a monocrystal area enclosed with an area where the dislocation bundle exists. A specific resistance of the monocrystal area is 0.5 Ωcm or less. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a light emitting device and a method for manufacturing the same, and more specifically to a light emitting device formed of a nitride semiconductor. The light emitting device in the present invention may refer only to a semiconductor element or a semiconductor chip mainly formed of a nitride semiconductor substrate and a semiconductor layer stacked thereon, or the semiconductor chip may be a mounting component. In some cases, it refers only to a device mounted on and sealed with resin. Furthermore, it may be used for both meanings. A semiconductor chip may be simply called a chip. Further, the substrate and the epitaxial layer formed thereon may be simply referred to as a substrate.

  White light emitting diodes (LEDs) are currently actively used for lighting small electronic devices such as personal digital assistants, but have the potential to be used for lighting in large spaces or large areas in the future. ing. In order to be used for illumination in a large space and a large area, it is necessary to increase the light output of the LED. For this reason, it is necessary to apply a large current to the electrode of the LED to solve the problem of temperature rise due to heat generation.

  FIG. 84 shows the structure of a GaN-based LED currently proposed (Patent Document 1). In this GaN-based LED, an n-type GaN layer 102 is provided on a sapphire substrate 101, and a quantum well structure 103 is formed between the n-type GaN layer 102 and the p-type GaN layer 104. Light emission occurs in this quantum well structure 103. A p-electrode 105 is formed on the p-type GaN layer 104 so as to be in ohmic contact, and an n-electrode 106 is formed on the n-type GaN layer 102 so as to be in ohmic contact.

  The p electrode 105 and the n electrode 106 are connected to the mounting component 109 with solder balls 107 and 108 interposed therebetween. The mounting component (submount component) is composed of a Si substrate, and a circuit for protecting from an external surge voltage is formed. In other words, a large forward voltage and reverse voltage are applied to the light-emitting device with an emphasis on the fact that the main cause of circuit failure for a group III nitride semiconductor such as Ga, Al, In is a surge voltage such as a transient voltage or electrostatic discharge. A power shunt circuit for protecting the light emitting device is formed of a Zener diode or the like so that no voltage is applied. The protection from surge voltage will be described in detail later.

  In the GaN-based LED, (a1) the p-type GaN layer 104 is down-mounted so as to emit light from the back surface side of the sapphire substrate 101, and (a2) the n-electrode layer 106 is formed on the n-type GaN layer 102. It has a feature in that. The structure of this GaN-based LED is very complex as seen in FIG. The reason why the n-electrode layer 106 is formed on the (a2) n-type GaN layer 102 that causes such a complicated structure is that the n-type electrode cannot be provided on the sapphire substrate because the sapphire substrate 101 is an insulator. .

  In the GaAs-based, GaP-based, and GaN-based compound semiconductors used in the light-emitting device as well as the light-emitting device using the sapphire substrate described above, a proposal for providing a protective circuit against transient voltage and electrostatic discharge in the light-emitting device is provided. It has been done frequently (see Patent Documents 2 to 4). In particular, a GaN-based compound semiconductor has a reverse breakdown voltage as low as about 50 V and a forward voltage as low as about 150 V, so that it is important to provide a power shunt circuit for the protection. That is, the GaN-based chip or the like is formed on a submount Si substrate, and a protection circuit including a Zener diode or the like is formed on the Si substrate. Many of the above protection circuit proposals are evidence that the main cause of circuit failure for III-nitride semiconductors such as Ga, Al, In, etc. is surge voltage such as transient voltage or electrostatic discharge. You can say that.

  In addition to the light-emitting device provided with the above-described protection circuit, an example in which a GaN-based light-emitting device is formed on a SiC substrate that is a conductor is also known. That is, light is emitted from the p-type GaN layer using a laminated structure of (SiC substrate rear surface n electrode / SiC substrate / n-type GaN layer / quantum well laminated structure (light emitting layer) / p-type GaN layer / p electrode). LEDs having such a structure are also widely used.

In addition, by making the main surface of the light-emitting device a pentagon or more polygon, the distance from the end face of the element to the inner wall of the light reflecting recess is made uniform to reduce the variation in light output and can be mounted in the light reflecting recess. It has also been proposed to increase the output by increasing the chip size (see, for example, Patent Document 5).
JP 2003-8083 A JP 2000-286457 A JP-A-11-54801 Japanese Patent Laid-Open No. 11-220176 JP 2000-261038 A

  In the GaN-based LED using the sapphire substrate shown in FIG. 84, it is inevitable that the structure becomes complicated and the manufacturing cost increases. In order to cultivate demand for the use of lighting in a wide space, it is essential that the LED is inexpensive, so the above structure is not preferable. Further, since the p-electrode 105 and the n-electrode 106 are arranged on the down mounting surface side, the electrode area, particularly the p-electrode area, is limited. In order to obtain a high output by flowing a large current, it is desirable that the p electrode has a particularly large area. However, the structure shown in FIG. 84 is limited, and as a result, the optical output is limited. Furthermore, it is not preferable to dispose two electrode layers on one surface in order to release heat generated with current.

  In addition, resistance when a current flows through the n-type GaN layer 102 in a direction parallel to the substrate is large, which causes heat generation, driving voltage, and power consumption. In particular, if the thickness of the n-type GaN layer is reduced for the purpose of shortening the film formation process, the yield of exposure of the n-type GaN film becomes very poor in addition to the above-mentioned problems of heat generation and power consumption.

  In addition, it can be said for all light-emitting devices including the above-described light-emitting device using the sapphire substrate. However, since the heat radiation area is limited and the thermal resistance (temperature increase due to unit energy input per unit area) is large, 1 The injection current per light emitting device cannot be increased. In particular, when a sapphire substrate is used, since the area of the p-electrode is limited as described above, it is usual to perform a thermal design with little margin.

  Furthermore, in the case of a GaN-based LED using the sapphire substrate, the heat radiation area is limited, so that the p electrode and the n electrode are formed in a comb shape in order to lower the electrical resistance and reduce the amount of heat generation. It is driven into the situation of adopting a structure that expands the contact area by making it complicated. Such a comb-shaped electrode is not easy to process and surely increases the manufacturing cost.

  As described above, the design of the thermal conditions in the light emitting device is of fundamental importance. When trying to obtain a large output, the thermal conditions are limited by the above-mentioned thermal conditions, and it is alleviated as much as possible. Inevitably, a complicated electrode shape must be adopted.

Furthermore, there are the following problems. When a GaN-based light emitting device formed on a sapphire substrate is mounted down and the back surface of the sapphire substrate is used as a light emission surface, the refractive index of sapphire is about 1.8 and the refractive index of GaN is 2.4. Therefore, at the interface between the GaN layer that has generated and propagated the light and the sapphire substrate, light having a predetermined incident angle or more is totally reflected and does not go outside. That is, light in the range of incident angle θ ≧ sin ⁻¹ (1.8 / 2.4) ≈48.6 ° stops in the GaN layer and does not go outside. For this reason, the light emission efficiency in the main surface of a sapphire substrate falls. However, the problem of luminous efficiency is important, but it does not stop there. The totally reflected light propagates through the GaN layer and is emitted from the side of the GaN layer. The amount of light that is totally reflected occupies a considerable proportion, and since the GaN layer is thin, the energy density of light emitted from the side portion becomes high. The sealing resin that is located on the side of the GaN layer and is irradiated with the light is damaged, causing a problem of shortening the lifetime of the light emitting device.

  Further, in a GaN-based LED having a structure in which light is extracted from the p-layer side (SiC substrate back surface n electrode / SiC substrate / n-type GaN layer / quantum well stacked structure (light-emitting layer) / p-type GaN layer / p electrode), the p-electrode Because of the large light absorption rate, high output light cannot be efficiently emitted outside. If the coverage of the p-electrode is decreased, that is, the aperture ratio is increased to increase the amount of light emitted, the p-type GaN layer has a high electric resistance, so that current cannot be caused to flow through the entire p-type GaN layer. . For this reason, light emission cannot be activated over the whole quantum well structure, and a light emission output falls. Also, the electrical resistance increases, causing problems of heat generation and power supply capacity. Further, if the thickness of the p-type GaN layer is increased for the purpose of allowing current to flow uniformly throughout the p-type GaN layer, the light absorption by the p-type GaN layer is large and the output is restricted.

  Further, in Patent Document 5 described above, a light emitting diode having a hexagonal principal surface as a pentagon or more polygon is described, but a specific manufacturing method thereof is not described. It is usually difficult to produce a light-emitting device such as a light-emitting diode whose main surface is a pentagon or more polygon by machining or the like.

  An object of the present invention is to provide a light emitting device that has a simple structure, is easy to manufacture, and can stably obtain a large light emission efficiency over a long period of time.

  A light emitting device according to the present invention includes a nitride semiconductor substrate, a nitride semiconductor layer stacked on a first main surface of the nitride semiconductor substrate, and a first electrode formed on the nitride semiconductor layer. A light emitting device including a second electrode formed on a second main surface opposite to the first main surface of the nitride semiconductor substrate, wherein the nitride semiconductor substrate is a nitride The semiconductor substrate includes a region where dislocation bundles in which dislocations are concentrated along the thickness direction from the first main surface to the second main surface of the semiconductor substrate, and a single crystal region surrounded by the region where the dislocation bundles exist. The specific resistance of the single crystal region is 0.5 Ω · cm or less.

  In this way, since dislocations in the nitride semiconductor substrate are concentrated in the region where the dislocation bundle exists, most of the nitride semiconductor substrate constituting the light-emitting device is formed in a region having a low defect (dislocation) density (low A single crystal region which is a defect region). For this reason, it is possible to improve the light extraction efficiency particularly when a large current is applied.

  Further, in this configuration, since an electrode (n-type electrode) is provided on the back surface (second main surface) of the nitride semiconductor substrate having a low electrical resistance, current can be supplied even if an n-electrode is provided with a small coverage, that is, a large aperture ratio. The entire nitride semiconductor substrate can be made to flow. For this reason, the rate of light absorption at the emission surface is reduced, and the light emission efficiency can be increased. Needless to say, light may be emitted not only from the second main surface but also from the side surface. The same applies to the following light-emitting devices.

  Nitride semiconductor “substrate” refers to a plate-like object that can be carried independently, and is distinct from “film” and “layer” that are difficult to maintain by themselves. . The same applies to the GaN substrate and the AlN substrate described later.

  The method for manufacturing a light emitting device according to the present invention includes a step of immersing a nitride semiconductor substrate in an etchant of an alkaline solution, and etching the nitride semiconductor substrate in a state where the etchant in which the nitride semiconductor substrate is immersed is sealed. And a dividing step of dividing the nitride semiconductor substrate.

  Thus, the substrate can be divided by etching in the manufacturing process of the light emitting device according to the present invention. For this reason, even if the planar shape of the single crystal region surrounded by the region where the dislocation bundle exists is a shape other than a square such as a regular triangle or a regular hexagon, the substrate can be easily divided.

  Next, embodiments and examples of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(Embodiment 1)
FIG. 1 is a diagram showing Embodiment 1 of an LED according to the present invention. FIG. 2 is a view showing a laminated structure including the light emitting layer of the LED of FIG. FIG. 3 is a plan view of the LED of FIG. 4 is a plan view of the chip constituting the LED shown in FIG. 1 as viewed from the side where the p-electrode is formed. FIG. 5 is a plan view of the chip constituting the LED shown in FIG. 1 as viewed from the side where the n-electrode is formed. Embodiment 1 of LED as a light-emitting device according to the present invention will be described with reference to FIGS.

  As shown in FIG. 1, a laminated structure including a light emitting layer, which will be described in detail later, is formed on the first main surface side of the GaN substrate 1, and a p-electrode 12 is provided. In the present embodiment, the p-electrode 12 is down-mounted on the lead frame mount 21 a by the conductive adhesive 14.

  The second main surface 1a of the GaN substrate 1 is a surface that emits light emitted from the light emitting layer, and an n-electrode 11 is provided on this surface. As can be seen from FIG. 3, the planar shape of the n-electrode 11 is a circular shape having a diameter D. The n electrode 11 is formed at the center of the second main surface 1a so as not to cover the entire second main surface.

  The n-electrode 11 is electrically connected to the lead portion 21 b of the lead frame by a wire 13. The wire 13 and the laminated structure are sealed with an epoxy resin 15 as a sealing member. Of the above configuration, the stacked structure from the GaN substrate 1 to the p-electrode 12 is enlarged and shown in FIG. In FIG. 2, the laminated structure in FIG. 1 is turned upside down.

Referring to FIG. 2, n-type GaN epitaxial layer 2 is positioned on GaN substrate 1, and n-type Al _x Ga _1-x N layer 3 is formed thereon. A quantum well (MQW: Multi-Quantum Well) 4 composed of an Al _x Ga _1-x N layer and an Al _x In _y Ga _1-xy N layer is formed thereon. A p-type Al _x Ga _1-x N layer 5 is arranged so that the quantum well 4 is sandwiched between the n-type Al _x Ga _1-x N layer 3. A p-type GaN layer 6 is disposed on the p-type Al _x Ga _{1 -x} N layer 5. In the above structure, the quantum well 4 emits light. Also, as shown in FIG. 1, a p-electrode 12 is formed on the p-type GaN layer 6 so as to cover the entire upper surface of the p-type GaN layer 6, and is down-mounted.

As can be seen from FIG. 3, the planar shape of the GaN substrate 1, the stacked structure thereon, and the p-electrode 12 is a regular hexagon. The interior angle of the regular hexagon is set to fall within a numerical range of ((60 ° ± 3 °) × 2 = (120 ° ± 6 °)). As shown in FIG. 4, the p-electrode 12 has a regular hexagonal shape in which the length of one side of the outer periphery is L _P1 . Further, the planar shape of the layer (p-type GaN layer 6) closest to the p-electrode 12 in the stacked structure formed on the GaN substrate 1 is also a regular hexagon with one side length L _P0 . The planar shape of the p-type GaN layer 6 and the planar shape of the p-electrode 12 are similar. As shown in FIG. 5, the planar shape of the GaN substrate 1 is also a regular hexagon with one side length of L _N0 . A circular n-electrode 11 having a diameter D is disposed at the substantially central portion of the GaN substrate 1. Here, since the end face of the GaN substrate 1 or the like is not inclined, the length L _P0 = the length L _N0 .

  Next, a method for manufacturing the LED shown in FIGS. 1 to 5 will be briefly described. FIG. 6 is a flowchart for explaining a method of manufacturing the LED shown in FIGS. FIG. 7 is a schematic plan view showing a state of the wafer when the LED chips shown in FIGS. 1 to 5 are collected from the wafer. FIG. 8 is a schematic cross-sectional view taken along line VIII-VIII in FIG. With reference to FIGS. 6-8, the manufacturing method of LED shown in FIGS. 1-5 is demonstrated.

  First, as shown in FIG. 6, a GaN substrate preparation step (S10) is performed. In this step, a GaN substrate having plate-like crystal inversion regions 51 distributed in parallel in the thickness direction of the GaN substrate is prepared. As shown in FIG. 7, the plate crystal inversion region 51 is arranged so as to surround a single crystal region whose planar shape is a regular hexagon. When the nitride semiconductor substrate (GaN substrate 1) is manufactured, the region where dislocation bundles (= cores) are collected takes a crystal arrangement that is inverted with respect to the surrounding crystal arrangement. For this reason, the plate-like crystal inversion region 51 and the dislocation bundle are the same in that the periphery and the crystal arrangement are inverted. The difference between the two is that the dislocation bundle collects dislocations in a string-like or thick line shape, and thus the crystal inversion region is a string, whereas the plate-like crystal inversion region 51 is plate-like. It is in. That is, in the plate-like crystal inversion region 51, dislocations are distributed with high density in a planar region having a thickness.

Next, an epitaxial film forming step (S20) for forming a laminated structure from the GaN substrate 1 to the p-electrode 12 is performed. In this process, any process used for forming a normal epitaxial film can be used. As a result, an n-type GaN epitaxial layer 2, an n-type Al _x Ga _1-x N layer 3, a quantum well 4, a p-type Al _x Ga _1-x N layer 5, and a p-type GaN layer 6 are formed. The plate-like crystal inversion region 51 of the GaN substrate 1 includes the n-type GaN epitaxial layer 2, the n-type Al _x Ga _{1 -x} N layer 3, the quantum well 4, and the p-type Al _x Ga _{1 -x} N layer 5 described above. , And propagates to the p-type GaN layer 6 respectively.

  Next, an electrode formation step (S30) is performed. In the step (S30), the p-electrode 12 is formed on the p-type GaN layer 6. In addition, an n-electrode 11 is formed on the back surface of the GaN substrate 1 opposite to the surface on which the stacked structure is formed. As a method for forming the p-electrode 12 and the n-electrode 11, any film forming method can be used. At this time, the p-electrode 12 is disposed on a regular hexagonal single crystal region surrounded by the plate-like crystal inversion region 51. The planar shape of the p-electrode 12 is a regular hexagon as already described. Adjacent p-electrodes 12 are formed in a state separated by a distance L3. The distance L3 is larger than the width of the plate crystal inversion region 51. The n-electrode 11 has a circular planar shape and is also disposed on a regular hexagonal single crystal region. Adjacent n-electrodes 11 are formed in a state separated by a distance L2.

  Next, in order to protect the light extraction surface (second main surface 1a) of the chip from the etching solution in an etching step described later, a step (S110) of forming a protective mask on the light extraction surface of the substrate is performed. In this step (S110), a film having resistance to an etchant (for example, an alkaline solution such as a KOH solution) used for etching is formed on the second main surface 1a of the GaN substrate 1 as a protective mask. As a material constituting the protective mask, any material can be used as long as the material has resistance to the etchant. For example, nickel or the like can be used as a material constituting the protective mask.

Next, a dividing step (S40) by etching is performed. In this dividing step (S40), the GaN substrate 1 on which the n electrode 11 and the p electrode 12 described above are formed is immersed in an alkaline solution etchant for a predetermined time. As a result, the GaN substrate 1 and the n-type GaN epitaxial layer 2, the n-type Al _x Ga _1-x N layer 3, the quantum well 4, the p-type Al _x Ga _1-x N layer 5, and the p-type GaN layer 6 are formed. By selectively etching the propagated plate crystal inversion region 51, the GaN substrate 1 can be divided. The temperature of the etchant can be arbitrarily set. For example, when a KOH solution is used as the etchant, the temperature is preferably set to an arbitrary temperature in the range of 80 ° C. to 250 ° C. If the GaN substrate 1 can be divided, a part of the plate crystal inversion region 51 may remain. For example, a part of the plate-like crystal inversion region 51 may remain at the outer edge of the chip shown in FIG. 5 (the outer edge of the GaN substrate 1). Note that as a material constituting a container (etching container) for holding a KOH solution as an etchant, any material can be used as long as the material has resistance to the KOH solution. For example, Teflon (registered trademark) or the like can be used as a material constituting the container.

  Next, after the division of the GaN substrate 1 is completed, the GaN substrate 1 is pulled up from an alkaline solution as an etchant, and the above-described protective mask is removed. Next, a cleaning / assembling step (S50) is performed for cleaning and assembly for obtaining the LED shown in FIG. In this way, the LED shown in FIG. 1 can be obtained.

  In the LED shown in FIGS. 1 to 5, the planar shape of the first and second main surfaces of the GaN substrate 1 is a regular hexagon, but the first and second of the GaN substrate 1 are shown. The planar shape of the main surface is not limited to the regular hexagon described above, and may be an arbitrary polygon. Hereinafter, an LED using a chip whose planar shape is a shape other than a regular hexagon will be described.

  FIG. 9 is a plan view showing a first modification of the first embodiment of the LED according to the present invention shown in FIGS. FIG. 10 is a plan view of the chip constituting the LED shown in FIG. 9 as viewed from the side where the p-electrode is formed. FIG. 11 is a plan view of the chip constituting the LED shown in FIG. 9 as viewed from the side where the n-electrode is formed. With reference to FIGS. 9-11, the 1st modification of Embodiment 1 of LED by this invention is demonstrated.

  The LED shown in FIGS. 9 to 11 basically has the same structure as the LED shown in FIGS. 1 to 5, but the planar shape of the chip is different. That is, in the LEDs shown in FIGS. 1 to 5, the planar shape of the chip is a regular hexagon, whereas in the LEDs shown in FIGS. 9 to 11, the planar shape of the chip is a regular triangle. .

Specifically, as can be seen from FIGS. 9 to 11, the planar shape of the GaN substrate 1, the stacked structure thereon, and the p-electrode 12 is an equilateral triangle. The interior angle of the equilateral triangle is set to fall within a numerical range of (60 ° ± 3 °). As shown in FIG. 10, the p-electrode 12 is an equilateral triangle having a length of one side of the outer periphery of L _P1 . Further, the planar shape of the layer (p-type GaN layer 6) closest to the p-electrode 12 in the stacked structure formed on the GaN substrate 1 is also an equilateral triangle with one side length L _P0 . The planar shape of the p-type GaN layer 6 and the planar shape of the p-electrode 12 are similar. Further, as shown in FIG. 11, the planar shape of the GaN substrate 1 is also an equilateral triangle having a side length of L _N0 . Here, since the end face of the GaN substrate 1 or the like is not inclined, the above length L _P0 = length L _N0 . The LED shown in FIGS. 9 to 11 can be basically manufactured by the same method as that of Embodiment 1 of the LED according to the present invention shown in FIGS. However, the difference is that the planar shape of the region (single crystal region) surrounded by the plate-like crystal inversion region 51 formed on the GaN substrate 1 is an equilateral triangle.

  FIG. 12 is a plan view showing a second modification of the first embodiment of the LED according to the present invention shown in FIGS. FIG. 13 is a plan view of the chip constituting the LED shown in FIG. 12 as viewed from the side where the p-electrode is formed. FIG. 14 is a plan view of the chip constituting the LED shown in FIG. 12 as viewed from the side where the n-electrode is formed. With reference to FIGS. 12-14, the 2nd modification of Embodiment 1 of LED by this invention is demonstrated.

  The LED shown in FIGS. 12 to 14 basically has the same structure as the LED shown in FIGS. 1 to 5, but the planar shape of the chip is different. That is, in the LED shown in FIGS. 1 to 5, the planar shape of the chip is a regular hexagon, whereas in the LED shown in FIGS. 12 to 14, the planar shape of the chip is a rhombus.

Specifically, as can be seen from FIGS. 12 to 14, the planar shape of the GaN substrate 1, the stacked structure thereon, and the p-electrode 12 is rhombus. As shown in FIG. 13, the p-electrode 12 has a rhombus whose length on one side of the outer periphery is L _P1 . Further, in the laminated structure formed on the GaN substrate 1, the planar shape of the layer closest to the p-electrode 12 (p-type GaN layer 6) is also a rhombus whose side is L _P0 . The planar shape of the p-type GaN layer 6 and the planar shape of the p-electrode 12 are similar. Further, as shown in FIG. 14, the planar shape of the GaN substrate 1 is also a rhombus whose length of one side is L _N0 . Here, since the end face of the GaN substrate 1 or the like is not inclined, the length L _P0 = the length L _N0 . The LED shown in FIGS. 12 to 14 can be basically manufactured by the same method as that of Embodiment 1 of the LED according to the present invention shown in FIGS. However, the difference is that the planar shape of the region (single crystal region) surrounded by the plate-like crystal inversion region 51 formed on the GaN substrate 1 is a rhombus.

  FIG. 15 is a plan view showing a third modification of the first embodiment of the LED according to the present invention shown in FIGS. 16 is a plan view of the chip constituting the LED shown in FIG. 15 as viewed from the side on which the p-electrode is formed. FIG. 17 is a plan view of the chip constituting the LED shown in FIG. 15 as viewed from the side where the n-electrode is formed. With reference to FIGS. 15-17, the 3rd modification of Embodiment 1 of LED by this invention is demonstrated.

  The LED shown in FIGS. 15 to 17 basically has the same structure as the LED shown in FIGS. 1 to 5, but the planar shape of the chip is different. That is, in the LED shown in FIGS. 1 to 5, the planar shape of the chip is a regular hexagon, whereas in the LED shown in FIGS. 15 to 17, the planar shape of the chip is a parallelogram. Yes.

Specifically, as can be seen from FIGS. 15 to 17, the planar shape of the GaN substrate 1, the stacked structure thereon, and the p-electrode 12 is a parallelogram. As shown in FIG. 16, p electrode 12 is it is in L _P1 length of relatively long one side of the outer periphery, the length of the relatively short side is in the parallelogram T _P1. Further, in the laminated structure formed on the GaN substrate 1, the plane shape of the layer closest to the p-electrode 12 (p-type GaN layer 6) is such that the length of one side of the outer periphery is relatively long, L _P0. Is a rhombus with a side length of T _P0 . The planar shape of the p-type GaN layer 6 and the planar shape of the p-electrode 12 are similar. As shown in FIG. 17, the planar shape of the GaN substrate 1 is also a parallelogram having a relatively long side of the outer periphery of L _N0 and a relatively short side of T _N0 . Here, since the end face of the GaN substrate 1 or the like is not inclined, the length L _P0 = the length L _N0 and the length T _P0 = the length T _N0 . The LED shown in FIGS. 15 to 17 can be basically manufactured by a method similar to the manufacturing method of Embodiment 1 of the LED according to the present invention shown in FIGS. However, the difference is that the planar shape of the region (single crystal region) surrounded by the plate-like crystal inversion region 51 formed on the GaN substrate 1 is a parallelogram.

  FIG. 18 is a plan view showing a fourth modification of the first embodiment of the LED according to the present invention shown in FIGS. FIG. 19 is a plan view of the chip constituting the LED shown in FIG. 18 as viewed from the side where the p-electrode is formed. 20 is a plan view of the chip constituting the LED shown in FIG. 18 as viewed from the side on which the n-electrode is formed. With reference to FIGS. 18-20, the 4th modification of Embodiment 1 of LED by this invention is demonstrated.

  The LED shown in FIGS. 18 to 20 basically has the same structure as the LED shown in FIGS. 1 to 5, but the planar shape of the chip is different. That is, in the LED shown in FIGS. 1 to 5, the planar shape of the chip is a regular hexagon, whereas in the LED shown in FIGS. 18 to 20, the planar shape of the chip is a trapezoid.

Specifically, as can be seen from FIGS. 18 to 20, the planar shape of the GaN substrate 1, the stacked structure thereon, and the p-electrode 12 is a trapezoid. As shown in FIG. 19, the p-electrode 12 has a length of a relatively long one of two sides parallel to each other on the outer periphery is L _P12 and a length of a relatively short one of the two parallel sides. Is L _P11 , and the length of the vertical side in FIG. 19 connecting the two sides described above is a trapezoid with T _P1 . In addition, the planar shape of the layer (p-type GaN layer 6) closest to the p-electrode 12 in the stacked structure formed on the GaN substrate 1 is also the length of a relatively long one of two sides parallel to each other on the outer periphery. Is L _P02 , the length of a relatively short one of the two sides is L _P01 , and the length of the vertical side connecting the two sides is T _P0 . The planar shape of the p-type GaN layer 6 and the planar shape of the p-electrode 12 are similar. In addition, as shown in FIG. 20, the planar shape of the GaN substrate 1 is such that the length of a relatively long side of two sides parallel to each other on the outer periphery is L _N02 , and the relatively short side of the two sides of it is an L _N01 length, the length of the longitudinal sides connecting the two sides described above is the trapezoidal T _N0. Here, since the end face of the GaN substrate 1 or the like is not inclined, the length L _P02 = the length L _N02 , the length L _P01 = the length L _N01 , and the length T _P0 = the length T _N0 . Further, the LED shown in FIGS. 18 to 20 can be basically manufactured by a method similar to the manufacturing method of Embodiment 1 of the LED according to the present invention shown in FIGS. However, the difference is that the planar shape of the region (single crystal region) surrounded by the plate-like crystal inversion region 51 formed on the GaN substrate 1 is a trapezoid.

(Embodiment 2)
FIG. 21 is a diagram showing a second embodiment of an LED as a light-emitting device according to the present invention. 22 is a plan view of the chip constituting the LED shown in FIG. 21 as viewed from the side on which the p-electrode is formed. FIG. 23 is a plan view of the chip constituting the LED shown in FIG. 21 as viewed from the side on which the n-electrode is formed. A second embodiment of the LED according to the present invention will be described with reference to FIGS.

The second embodiment of the LED according to the present invention shown in FIG. 21 basically has the same structure as the first embodiment of the LED according to the present invention shown in FIGS. However, the LED shown in FIG. 21 includes a GaN substrate 1, an n-type GaN epitaxial layer 2, an n-type Al _x Ga _1-x N layer 3, a quantum well 4, a p-type Al _x Ga _1-x N layer 5, p The LED 80 shown in FIGS. 1 to 5 is different from the LED shown in FIGS. 1 to 5 in that the side surface 80 of the chip made of the type GaN layer 6 is formed to be inclined with respect to the second main surface 1a of the GaN substrate 1.

As shown in FIG. 22, the p-electrode 12 has a regular hexagonal shape in which the length of one side of the outer periphery is L _P1 . Further, the planar shape of the layer (p-type GaN layer 6) closest to the p-electrode 12 in the stacked structure formed on the GaN substrate 1 is also a regular hexagon with one side length L _P0 . The planar shape of the p-type GaN layer 6 and the planar shape of the p-electrode 12 are similar. As shown in FIG. 23, the planar shape of the second main surface of the GaN substrate 1 is also a regular hexagon with one side length of L _N0 . A circular n-electrode 11 having a diameter D is disposed at the substantially central portion of the GaN substrate 1. Here, as shown in FIG. 21, since the side surface 80 of the chip is inclined, the length L _N0 is larger than the length L _P0 . Thus, the light extraction efficiency can be further improved by inclining the side surface 80 of the chip.

  Next, a method for manufacturing the LED shown in FIGS. 21 to 23 will be briefly described. FIG. 24 is a flowchart for explaining a method of manufacturing the LED shown in FIGS. FIG. 25 is a schematic plan view showing a state of the wafer when the LED chips shown in FIGS. 21 to 23 are collected from the wafer. 26 is a schematic cross-sectional view taken along line XXVI-XXVI in FIG. FIG. 27 is an enlarged schematic view showing a region corresponding to one chip in the wafer shown in FIG. With reference to FIGS. 24 to 27, a method of manufacturing the LED shown in FIGS. 21 to 23 will be described.

  As can be seen from FIG. 24, the LED manufacturing method shown in FIGS. 21 to 23 is basically the same as the LED manufacturing method shown in FIG. 6. That is, in the LED manufacturing method shown in FIGS. 21 to 23, as in the manufacturing method shown in FIG. 6, the GaN substrate preparation step (S10), the epitaxial film formation step (S20), and the electrode formation step) (S30). To implement. Thereafter, in order to protect the light extraction surface (second main surface 1a) of the chip from the etching solution in an etching step described later, a step (S110) of forming a protective mask on the light extraction surface of the substrate is performed. In this step (S110), a film having resistance to an etchant (for example, an alkaline solution such as a KOH solution) used for etching is formed on the second main surface 1a of the GaN substrate 1 as a protective mask. As a material constituting the protective mask, any material can be used as long as the material has resistance to the etchant.

Thereafter, the dividing step (S40) by etching is performed as in the manufacturing method shown in FIG. However, in the dividing step (S40), the GaN substrate 1 is etched by immersing the GaN substrate 1 in the etchant (S41) and performing etching while maintaining the etchant in which the GaN substrate 1 is immersed at a predetermined temperature and pressure. Includes a separation step (S42) for separating (dividing). In this dividing step (S40), the GaN substrate 1, the n-type GaN epitaxial layer 2, and the n-type Al _x Ga _1-x N are adjusted by adjusting process conditions such as the temperature and pressure of the etchant and the etching time. The plate-like crystal inversion region 51 propagated to the epitaxial film layer composed of the layer 3, the quantum well 4, the p-type Al _x Ga _1-x N layer 5, the p-type GaN layer 6 and the like is selectively etched. At the same time, the side surfaces of the GaN substrate 1 and the above-described epitaxial film layer are partially removed by etching by optimizing the process conditions such as the temperature and pressure of the etchant and the etching time, so that the GaN substrate 1 and the above-described epitaxial layer are removed. The side surface of the film layer (the side surface 80 of the chip facing the boundary line 82) is inclined as shown in FIGS. As described above, the shape of the side surface of the epitaxial film layer (for example, whether the side surface is inclined) can be controlled by appropriately changing the etching conditions.

  In the separation step (S42) described above, in order to change the pressure condition of the etchant from atmospheric pressure, for example, the etchant is put in a sealed container and the etchant in which the GaN substrate 1 is immersed in the sealed container is sealed. Etching may be performed. Thereafter, the protective mask described above is removed. As a result, as shown in FIG. 27, a plurality of convex portions having convex side surfaces 80 and having a regular hexagonal planar shape (a convex portion to be a chip including a single crystal region) are formed simultaneously. become.

Incidentally, the dividing step may each chip is completely divided by etching in (S40), but by only the depth H ₁ etching as shown in FIG. 26 the plate-shaped crystal inversion regions 51 such as GaN substrate 1 partially while removing, in a state of being left without etching the GaN substrate 1 by a depth H _2, may end the etching. In this case, after the etching, a process such as cleaving the connection portion of the GaN substrate 1 located at the bottom of the groove formed by the etching is performed so as to be a unit including one or a plurality of single crystal regions.

  Thereafter, the LED shown in FIGS. 21 to 23 can be obtained by performing the cleaning / assembly process (S50) in the same manner as the manufacturing method shown in FIG.

(Embodiment 3)
FIG. 28 is a diagram showing Embodiment 3 of an LED as a light-emitting device according to the present invention. With reference to FIG. 28, Embodiment 3 of the LED according to the present invention will be described.

  The third embodiment of the LED according to the present invention shown in FIG. 28 basically has the same structure as the second embodiment of the LED according to the present invention shown in FIGS. However, in the LED shown in FIG. 28, the non-specular treatment is performed on the surface of the second main surface 1a of the GaN substrate 1 on which the n-electrode 11 is formed. Specifically, an uneven portion is formed on the second main surface 1a of the GaN substrate 1 in a portion other than the region where the n-electrode 11 is disposed. In this way, in addition to the effects of the LEDs shown in FIGS. 21 to 23, the second main surface (light emission surface) of the GaN substrate 1 is further subjected to non-specular treatment, so that the light emission surface is obtained. The probability that the light generated in the light emitting layer is confined in the GaN substrate 1 by total reflection can be reduced. As a result, the amount of light emitted from the light exit surface can be increased, so that the light extraction efficiency can be improved.

  Next, a method for manufacturing the LED shown in FIG. 28 will be briefly described with reference to FIG. Here, FIG. 29 is a schematic plan view showing a state of the wafer when the LED chip shown in FIG. 28 is taken from the wafer.

  The LED manufacturing method shown in FIG. 28 is basically the same as the LED manufacturing method shown in FIG. 24 except that the step (S110) of forming a protective mask on the light extraction surface of the substrate is not performed. Is different from the manufacturing method shown in FIG. That is, in the LED manufacturing method shown in FIG. 28, after the GaN substrate preparation step (S10), the epitaxial film formation step (S20), and the electrode formation step (S30), as in the manufacturing method shown in FIG. Without performing the step of forming the protective mask (S110), the dividing step (S40) by etching is performed as it is.

For this reason, in the dividing step (S40), the second main surface 1a (light emission surface) of the GaN substrate 1 is also exposed to an etchant such as an alkaline solution. As a result, the second main surface 1a is also etched, and as a result, an uneven portion is formed on the second main surface 1a as shown in FIG. That is, in the division step (S40) described above, as shown in FIG. 29, the chip division, the formation of the inclined side surface 80, and the non-specular treatment on the second main surface 1a are performed simultaneously. As shown in FIG. 29, in the division step (S40), the GaN substrate 1 on which the epitaxial film layer, the n electrode 11 and the p electrode 12 are formed has a plate-like crystal so as to divide each single crystal region. by inversion region 51 is selectively etched, V-shaped grooves of depth H ₁ is formed. At the same time, an uneven portion is formed by etching on the second main surface of the GaN substrate 1 on which the n-electrode 11 is formed. At this time, each chip may be divided by sufficiently increasing the depth H1 of the V-shaped groove, or the portion not etched is left as shown in FIG. 29, and the bottom of the V-shaped groove is left. The chip may be divided by later cleaving the portion of the thickness H2 located in the area.

  And after implementing a division | segmentation process (S40), LED shown in FIG. 28 can be obtained by implementing a washing | cleaning and assembly process (S50) similarly to the manufacturing method shown in FIG.

  In the first and second embodiments of the LED according to the present invention already described, a concavo-convex portion may be formed on the second main surface 1a of the GaN substrate 1 as shown in FIG. May be processed).

(Embodiment 4)
FIG. 30 is a plan view showing Embodiment 4 of an LED as a light emitting device according to the present invention. FIG. 31 is a plan view of the chip constituting the LED shown in FIG. 30 as viewed from the side on which the p-electrode is formed. 32 is a schematic cross-sectional view taken along line XXXII-XXXII in FIG. A fourth embodiment of an LED according to the present invention will be described with reference to FIGS.

  The LED shown in FIGS. 30 to 32 basically has the same structure as the LED shown in FIG. 28, but uses a large-area chip including a plurality (nine) of single crystal regions as the chip. Is different from the LED shown in FIG. The LED shown in FIGS. 30 to 32 uses a chip in which nine chips (unit chips) of the LED shown in FIG. 28 having a hexagonal planar shape are gathered in 3 rows × 3 columns. Each of the unit chips has a side surface 80 inclined with respect to the second main surface 1 a of the GaN substrate 1. Each unit chip is formed with a p-electrode 12 having a regular hexagonal planar shape. Further, in the center of the second main surface 1a of the GaN substrate 1 in the chip (the center of the second main surface 1a of the unit chip located in the center), a plane having a diameter D as shown in FIG. An n-electrode 11 having a circular shape is formed. If it does in this way, LED which enlarged the area of the light emission surface is easily realizable by using a chip provided with a plurality of unit chips.

Next, a method for manufacturing the LED shown in FIGS. 30 to 32 will be briefly described. The manufacturing method of the LED shown in FIGS. 30 to 32 is basically the same as the manufacturing method of the LED shown in FIG. However, the difference is that the wafer is divided so as to include nine unit chips. That is, in the LED manufacturing method shown in FIGS. 30 to 32, the GaN substrate preparation step (S10), the epitaxial film formation step (S20), and the electrode formation step (S30) are performed as in the manufacturing method shown in FIG. carry out. In the electrode formation step (S30), the n electrodes 11 are arranged so that one n electrode 11 is formed per nine unit chips. Thereafter, the second main surface on which the n-electrode 11 is formed at the same time as the chip division is subjected to non-specular treatment, so that the etching is performed without performing the step (S110) of forming the protective mask shown in FIG. The dividing step (S40) is performed. In the division step (S40) described above, the chip division, the formation of the inclined side surface 80, and the non-mirror surface treatment on the second main surface 1a are performed simultaneously. By this dividing step (S40), the plate-like crystal inversion region 51 is formed on the GaN substrate 1 on which the epitaxial film layer, the n electrode 11 and the p electrode 12 are formed so as to divide the single crystal region of each unit chip. by being selectively etched, V-shaped grooves of depth H ₁ is formed. At the same time, an uneven portion is formed by etching on the second main surface of the GaN substrate 1 on which the n-electrode 11 is formed.

  Then, after the etching is completed, the chips are divided from the wafer so as to have a planar shape as shown in FIG. 30 including nine unit chips. As a method of division, for example, a method of cleaving a portion of the GaN substrate 1 located at the bottom of the V-shaped groove located on the outer periphery of the 3 × 3 unit chip group that becomes the LED chip shown in FIG. Or a protective mask is formed so as to cover the unit chip group of 3 rows × 3 columns, and the bottom portion of the V-shaped groove of the GaN substrate 1 located on the outer periphery of the unit chip group is etched. You may use the method of removing.

  Thereafter, in the same manner as the manufacturing method shown in FIG. 24, the LED shown in FIGS. 30 to 32 can be obtained by performing the cleaning / assembly process (S50).

  The LED according to the present invention uses the GaN substrate 1 (nitride semiconductor substrate) as described above. Hereinafter, the specific configuration and effect of the LED as the light emitting device will be described in more detail.

  First, a sapphire substrate is compared with a GaN substrate that is a nitride semiconductor substrate. Here, the LED of Invention Example A in Example 1 of the present invention has the same structure as the LED shown in FIG. Hereinafter, the LED of Example A of the present invention will be described with reference to FIG. As shown in FIG. 1, in the LED of Invention Example A, a laminated structure including a light emitting layer, which will be described in detail later, is formed on the first main surface side of the GaN substrate 1, and a p-electrode 12 is provided. ing. The present embodiment has one feature in that the p-electrode 12 is down-mounted on the lead frame mount portion 21 a by the conductive adhesive 14.

  The second main surface 1a of the GaN substrate 1 is a surface that emits light emitted from the light emitting layer, and an n-electrode 11 is provided on this surface. The n electrode 11 does not cover the entire second main surface. It is important to increase the ratio of the portion not covered with the n-electrode 11. If the aperture ratio is increased, the light blocked by the n-electrode is reduced, and the emission efficiency for emitting light to the outside can be increased.

  The n-electrode 11 is electrically connected to the lead portion 21 b of the lead frame by a wire 13. The wire 13 and the laminated structure are sealed with an epoxy resin 15. As described above, FIG. 2 shows an enlarged view of the laminated structure from the GaN substrate 1 to the p-electrode 12 in the above configuration. In FIG. 2, the laminated structure in FIG. 1 is turned upside down.

Next, a method for manufacturing the LED of Invention Example A will be described.
(A1) A GaN off-substrate shifted by 0.5 ° from the c-plane was used. This substrate had a specific resistance of 0.01 Ω · cm and a thickness of 400 μm. In the GaN substrate, plate-like crystal inversion regions 51 (see FIG. 8) distributed in parallel in the thickness direction of the GaN substrate are formed. The dislocation density in the plate crystal inversion region 51 was 1E9 / cm ² . Further, the dislocation density of the single crystal region surrounded by the plate crystal inversion region 51 was 1E6 / cm ² . As a method for measuring the specific resistance of the GaN substrate on which the plate-like crystal inversion region 51 is formed as described above, a method such as electrical resistance measurement by a four-terminal method can be used. Further, the method of measuring the specific resistance is not limited to the above method, and any other method can be used.
(A2) The following laminated structure was formed on the Ga surface which is the first main surface of the GaN substrate by MOCVD (Metal Organic Chemical Vapor Deposition). (SiW-doped n-type GaN layer / Clad layer Si-doped n-type Al _0.2 Ga _0.8 N layer / MQW (Multi-Quantum Well) / two layers of GaN layer and In _0.15 Ga _0.85 N layer) (Clad layer Mg-doped p-type Al _0.2 Ga _0.8 N layer / Mg-doped p-type GaN layer) Note that a plate-like crystal inversion region 51 of a GaN substrate propagates in the laminated structure as shown in FIG.
(A3) The emission wavelength was 450 nm, and the internal quantum efficiency calculated for convenience by comparing PL (Photo Luminescence) intensity at a low temperature of 4.2 K and PL intensity at a room temperature of 298 K was 50%.
(A4) The wafer was activated to reduce the resistance of the Mg-doped p-type layer. The carrier concentration by hole measurement was 5E17 / cm ^{3 for} the Mg-doped p-type Al _0.2 Ga _0.8 N layer and 1E18 / cm ³ for the Mg-doped p-type GaN layer.
(A5) An n-electrode having a diameter (D) of 100 μm is formed at the center of the chip every L2 = 439 μm on the N surface of the back surface, which is the second main surface of the GaN substrate, by photolithography, vapor deposition, and lift-off method (See FIG. 7). As the n-electrode, a stacked structure (Ti layer 20 nm / Al layer 100 nm / Ti layer 20 nm / Au layer 200 nm) was formed in order from the bottom in contact with the GaN substrate. By heating this in a nitrogen (N ₂ ) atmosphere, the contact resistance was set to 1E-5 Ω · cm ² or less.
(A6) The p-electrode is in contact with the p-type GaN layer, a planar shape is a regular hexagonal shape, and a Ni layer having a side length L _P1 of 186 μm and a thickness of 4 nm is formed thereon. A layer was formed (see FIG. 7). This was heat-treated in an inert gas atmosphere, so that the contact resistance was 5E-4 Ω · cm ² . The distance L3 between adjacent p-electrodes 12 was 117 μm (see FIG. 7).
(A7) Then, a protective mask for protecting the second main surface from an etching process to be described later is formed on the N surface on the back surface which is the second main surface of the GaN substrate on which the n electrode 11 is formed. As the protective mask, a film having resistance to a KOH solution used for etching is formed.
(A8) Thereafter, as described in the dividing step (S40) by etching in FIG. 6, the plate-like crystal inversion region 51 (see FIGS. 7 and 8) is obtained by etching using a KOH solution as an alkaline solution as an etchant. Is selectively removed. The chip having a regular hexagonal plan shape thus obtained was used as a light emitting device. The light emitting device formed into a chip has a regular hexagonal shape with a side of 236 μm on the outermost periphery of the chip, a regular hexagonal shape with a light emission surface of 186 μm on one side (light emitting area is 0.09 mm ² ), Takes the shape of a regular hexagon with a side of 186 μm. That is, in FIG. 5, L _N0 = 236 μm. Further, the diameter D of the n electrode is 100 μm.
(A9) Referring to FIG. 1, the chip was mounted so that the p-type GaN layer side of the chip was in contact with the mount 21a of the lead frame to form a light emitting device. The light emitting device and the mount are fixed by the conductive adhesive 14 applied to the mount portion, and conduction is obtained.
(A10) In order to improve heat dissipation from the light emitting device, the p-type GaN layer of the light emitting device was mounted so as to be in contact with the entire mount portion. Also, an Ag-based adhesive with good thermal conductivity was selected, and a lead frame of CuW-based adhesive with high thermal conductivity was selected. Thereby, the obtained thermal resistance was 8 ° C./W.
(A11) Further, the n electrode and the lead portion of the lead frame were made conductive by wire bonding, and then resin sealing was performed with an epoxy resin to form a lamp.

  Next, Comparative Example B will be briefly described. In FIG. 33, a p-electrode 112 is down-mounted with a conductive adhesive 114 on the lead frame mount. The n electrode is connected by a conductive adhesive 114 to a lead frame mount 121a that is separated from the lead frame mount to which the p electrode is connected. A laminated structure including a light emitting layer (FIG. 34) is provided thereon, and is in contact with a predetermined range of the n-type GaN layer 102. The n-type GaN layer 102 is formed on the sapphire substrate 101, and an n-electrode 111 is provided in a range outside the range where the above laminated structure is in contact. The n-electrode 111 is electrically connected to the lead frame mount 121a or the lead frame lead 121b by a wire or a conductive adhesive.

Light emitted from the light emitting layer is emitted to the outside through the sapphire substrate 101. An epoxy resin 115 is sealed so as to cover the laminated structure including the sapphire substrate.
(B1) A sapphire insulating off substrate shifted by 0.2 ° from the c-plane was used. The thickness of this sapphire substrate was 400 μm.
(B2) to (b4) The same treatment as (a2) to (a4) in Invention Example A was performed.
(B5) In Comparative Example B, since the sapphire substrate is an insulator, the n-electrode needs to be provided on the same growth film side as the p-electrode. Therefore, this wafer is further etched by photolithography and RIE from the Mg-doped p-type layer side to the Si-doped n-type layer with a Cl-based gas to expose the n-type GaN layer for providing the n-electrode, thereby isolating elements. (FIGS. 35 and 36). The shape of the element is 300 μm □ (a square having a side of 300 μm), and the exposed n-type GaN has a width of 150 μm □ per element. That is, the length L4 of the side of the rectangular step of the exposed portion is 150 μm.
(B6) On the exposed n-type GaN layer, an n-electrode having a diameter of 100 μm was attached by photolithography, vapor deposition, and lift-off method. The thickness, heat treatment, and contact resistance were the same as Example A of the present invention.
(B7) The p-electrode was placed on the p-type GaN layer portion obtained by removing the n-type GaN exposed portion 150 μm □ from the device 300 μm □. The thickness, heat treatment, and contact resistance were the same as Example A of the present invention.
(B8) Thereafter, as shown in FIGS. 35 and 36, scribing was performed so that the chip boundary 150 appeared as a side surface, and the resulting light-emitting device was made into a chip. The light-emitting device formed into a chip has a light emission surface of a shape of 300 μm □ (a square having a side length of 300 μm) and a light-emitting layer of a shape of 300 μm □. That is, in FIG. 36, L1 = 300 μm and L2 = 400 μm. Further, the width D of one side of the n-electrode is 100 μm.
(B9) The same process as the corresponding process in Invention Example A was performed.
(B10) Similarly to Example A of the present invention, in order to improve heat dissipation from the light emitting device, the p-type GaN layer of the light emitting device was mounted so as to be in contact with the entire mount portion. In FIG. 33, the contact area between the p-type GaN layer 106 and the p-electrode 112 is 0.0675 mm ² . Since heat generation of the light emitting device occurs in the quantum well layer 104 and the p-type GaN layer 106, this heat dissipation is mainly determined by the area of the p electrode 112. In the case of FIG. 33, the n-electrode 111 is also connected to the mount portion 121a of the lead frame by the conductive adhesive 114, but the heat radiation area is substantially the above contact area of 0.0675 mm ² . The contact area between the p-type GaN layer 6 and the p-electrode 12 in Invention Example A is 0.18 mm ² . The materials of the adhesive and the lead frame were the same as those of Example A of the present invention. In Comparative Example B, reflecting the above structure, the thermal resistance was 10.4 ° C./W, which was 1.3 times that of Invention Example A.
(B11) The same process as the corresponding process in Invention Example A was performed.

(Experiment and its results)
The present invention example A and comparative example B were mounted in an integrating sphere, and then a predetermined current was applied to compare the light output values collected and output from the detector. The results are shown in FIG. According to FIG. 37, in a relatively ideal state where current is injected into the MQW layer without leaking, non-radiative recombination in the MQW layer is relatively small, and the temperature rise of the chip due to heat generation is small. The light output value increases in proportion to the increase in applied current. For example, in the case of 20 mA injection, the output of Invention Example A was 8 mW, and Comparative Example B was 7.2 mW.

  This is because the GaN-based epitaxial film / sapphire substrate is the main configuration in Comparative Example B, as compared with the GaN-based epitaxial film / GaN substrate as the main configuration in Invention Example A. Since the refractive index of the sapphire substrate is about 1.8, which is considerably smaller than the refractive index 2.4 of GaN, in Comparative Example B, the light formed and propagated in the GaN-based epitaxial film is the same as that of the GaN-based epitaxial film. At the interface with the sapphire substrate, the total reflection is easier than in the invention example A. This causes the output of Comparative Example B to be smaller than that of Invention Example A.

However, when the current was increased 5 times and 100 mA was applied, an output of 40 mW, which was 5 times greater, was obtained in Example A of the present invention, but only 25.2 mW was obtained in Comparative Example B (see FIG. 37). The current density in the MQW light emitting section at this time was 110 A / cm ² in Invention Example A and 150 A / cm ² in Comparative Example B, as shown in FIG. That is, the current density in the MQW light emitting portion of Invention Example A is larger than that of Comparative Example B.

  In the present invention example A, the heat radiation area is sufficiently wide with respect to the generated heat, and the n-electrode is provided on the second main surface side of the substrate so that there is no portion where the current density becomes extremely large. Means that On the other hand, in Comparative Example B, the heat dissipation area is smaller than that of Invention Example A, and the n-type GaN layer is provided with the n-electrode exposed, so that the current flowing in the n-type GaN layer in a direction parallel to the layer. This means that the current density of becomes extremely large. As a result, in Comparative Example B, the heat generation further increases.

  In addition, unlike the comparative example B, the inventive example A is in the position where the n electrode and the p electrode are opposed to each other, so there is no risk of an electrical short. In the comparative example B on the same side, for example, It is also possible to prevent an unnecessary increase in manufacturing cost by providing a film for electrically insulating the n electrode.

  Furthermore, the test result about the electrostatic withstand voltage of the invention example A and the comparative example B will be described. In the test, a light emitting device and a capacitor charged with static electricity were opposed to each other to cause discharge between them. At this time, in Comparative Example B, it was broken at a static voltage of about 100V. On the other hand, the invention sample A did not break down to about 8000V. Inventive Example A was found to have an electrostatic withstand voltage about 80 times that of Comparative Example B.

  In the above invention example A, since the GaN-based light emitting device is formed on the GaN substrate, even if the GaN-based light-emitting chip is mounted down and light is emitted from the back surface of the GaN substrate, the difference in refractive index Since there is no between them, light propagates from the GaN-based light emitting chip to the GaN substrate without total reflection. For this reason, compared with the structure which formed the GaN-type light-emitting device using the sapphire substrate, the light output in a GaN substrate main surface can be raised. Furthermore, since light is not concentrated and emitted from the side portion of the GaN layer, the sealing resin is not damaged, and the lifetime is not limited by the sealing resin.

In the present invention example, only an example with an emission wavelength of 450 nm is shown, and the same effect can be obtained even when the emission wavelength and the layer structure are changed. Needless to say, the same effect can be obtained even if an Al _x Ga _1-x N substrate (where x is larger than 0 and equal to or smaller than 1) is used instead of the GaN substrate if the substrate characteristics are equivalent.

In Example 2 of the present invention, Example C of the present invention when the area is further increased will be described. Invention Example C is the same as the structure of Invention Example A shown in FIG. 1, but the length L _P1 (see FIG. 4), which is the dimension, is 186 μm in Invention Example A. In the present invention example C, the length L _P1 is about 10 times as long as 1.87 mm, and thus the area is 100 times. First, the manufacturing method of Example C of the present invention is as follows.

(Invention Sample C)
(C1) to (c4) Although a large GaN substrate is used, the same process as the corresponding process in Example A of the present invention is performed.
(C5) On the second main surface which is the back surface of the GaN substrate, an n-electrode having a diameter of 100 μm was attached to the center of the chip every 3.36 mm by photolithography, vapor deposition, and lift-off method. As the n-electrode, a stacked structure of (Ti layer 20 nm / Al layer 100 nm / Ti layer 20 nm / Au layer 200 nm) was formed in order from the bottom in contact with the back surface of the GaN substrate. This was heat-treated in an inert atmosphere so that the contact resistance was 1E-5 Ω · cm ² or less.
(C6) After that, a dividing process by etching was performed so as to obtain a predetermined shape, and a chip was obtained as a light emitting device. The length L _P0 = L _N0 = 1.92 mm, the length L _P1 = 1.87 mm, and the diameter D = 100 μm (see FIGS. 4 and 5) in the light-emitting element formed into a chip.
(C7)-(c11) The same process as the corresponding process in Invention Example A was performed. Next, a modified example C1 in which the arrangement of the n-electrode according to Invention Example C was modified was produced as follows.

(Invention Sample C1)
FIG. 39 and FIG. 40 are diagrams showing the present invention example C1, which is a modification of the above-described invention example C. FIG. The invention example C1 is characterized in that the n-electrode 11 is arranged at six corners of the GaN substrate, that is, at six corners. In addition, a reflective cup 37 is disposed on the lead frame so as to surround the semiconductor chip in mounting the semiconductor chip.

  In the production of the present invention example C1, the same treatment was performed in the steps corresponding to the invention example A. However, six Au wires were used as bonding wires, and the diameter of each cross section was 25 μm. The shape of each n electrode located at the six corners is 36 μm □.

  Next, Comparative Example D will be described. The structure of Comparative Example D is the same as the structure shown in FIG. However, compared with L1 in Comparative Example B of FIG. 33 being 300 μm (0.3 mm), L1 in Comparative Example D is 3 mm, which is 10 times. Further, the dimension L4 of the n-type GaN layer portion forming the n-electrode is 150 μm, which is the same as in Comparative Example B in FIG. The manufacturing method of Comparative Example D is as follows.

(Comparative Example D)
(D1) A sapphire large-sized insulating off-substrate shifted by 0.2 ° from the c-plane was used. The thickness of the sapphire substrate was 400 μm.
(D2) to (d4) The same processes as those in Example A of the present invention were performed.
(D5) In the case of Comparative Example D, since the sapphire substrate is an insulator, the n electrode needs to be provided on the same growth film side as the p electrode. Therefore, the n-type GaN layer for providing the n-electrode is exposed by further etching this wafer with Cl-based gas from the Mg-doped p-type layer side to the Si-doped n-type layer by photolithography and RIE. Then, element isolation was performed. The size of the element was 3 mm □ and a large size as described above. The width of the portion of the n-type GaN layer exposed to arrange the n-electrode was 150 μm □ per element.
(D6) On the exposed n-type GaN layer, an n-type electrode having a diameter of 100 μm was attached by photolithography technique, vapor deposition, and lift-off method. The thickness, heat treatment, and contact resistance are the same as Example A of the present invention.
(D7) The p-electrode was provided on the p-type GaN layer excluding the exposed portion 150 μm □ of the n-type GaN layer for disposing the element isolation trench and the n-electrode from the element region 3.1 mm □. The thickness, heat treatment, and contact resistance were the same as Example A of the present invention.
(D8) to (d11) The same processing as that in the invention sample A was performed.

  Next, another comparative example E will be described. Comparative Example E is the same as Comparative Examples B and D in that a p-electrode 112 and an n-electrode 111 are both provided on the down-mounting side using a sapphire substrate as shown in FIG. However, as apparent from the plan view of FIG. 42, the p electrode 112 is formed in a comb shape, the n electrode 111 is disposed between the teeth of the comb, and an insulator is disposed between the p electrode 112 and the n electrode 111. Is different in that This is because the current flowing through the p-electrode and the n-electrode is equalized so that a portion where the current density becomes extremely high is not generated. The manufacturing method of Comparative Example E is as follows.

(Comparative Example E)
In the same manufacturing method as in Comparative Example D, five n-electrodes 111 were provided at intervals of 0.5 mm, and 0.1 mm wide comb-shaped electrodes (see FIGS. 41 and 42). A p-electrode was provided on the remaining back surface portion of the n-type GaN layer 102 while separating the n-electrode 111 and the p-electrode 112 by 0.1 mm. Furthermore, an insulator 119 for protecting the surface was provided in the gap between the n electrode and the p electrode so that each electrode would not be electrically short-circuited. In order to prevent further short circuiting, a conductive adhesive 114 is provided at a portion corresponding to each electrode position of the mounting portion 121a of the lead frame, and the chip is mounted while controlling the deviation of the chip and the lead frame in the horizontal and vertical directions and the rotation direction. Mounted on the lead frame.

(Experiment and its results)
The present invention example C and the comparative example D were mounted in an integrating sphere, a predetermined current was applied, and the light output values collected and output from the detector were compared. At a current application of 20 mA, the output of Invention Example C was 8 mW, while Comparative Example D was 7.2 mW. On the other hand, when a current of 2 A (2000 mA) was applied, in Example C of the present invention, an output of 800 mW of 100 times was obtained. However, Comparative Example D was damaged.

  Therefore, as a result of measuring the temperature of the element with a thermoviewer while applying current without applying resin sealing to Comparative Example D, the n-type GaN layer was concentrated in the direction parallel to the layer from the n electrode to the MQW light emitting portion. It was found that the part where the current flows was abnormally heated and damaged.

  Therefore, a structure having a structure in which a current flowing in a direction parallel to the n-type GaN layer from the n-type electrode to the MQW light-emitting portion is dispersed in comparison with Comparative Example D was prepared. This is Comparative Example E described above. In Comparative Example E, an output of 7.2 mW at an applied current of 20 mA and 720 mW at 2 A, 0.9 times that of Example C of the present invention, could be obtained.

  Thus, if it is going to obtain the performance close | similar to this invention example C, compared with this invention example C, since a very complicated structure and process are needed, a manufacturing cost will become very large.

  Next, an electrostatic withstand voltage test was performed on the above-described inventive example C and comparative examples D and E. In the test, as described above, the light emitting device and the capacitor charged with static electricity were opposed to each other to cause discharge between them. At this time, Comparative Examples D and E were broken at a static voltage of about 100V. On the other hand, Example C of the present invention did not break down to about 8000V. That is, in the present invention example, an extremely high electrostatic withstand voltage of about 80 times could be obtained.

  In Example C1 of the present invention, the aperture ratio greatly exceeds 50% and is almost 100%. Further, by being positioned at the corner of the GaN substrate, it is drastically reduced that it becomes an obstacle to light extraction as compared with the case of being positioned at the center. In the case shown in FIG. 39, since the n-electrode is located outside the active layer as viewed in plan, the n-electrode has no influence on the light extraction. As a result, the present invention example C1 can obtain a higher output than the present invention example C.

  In Example 3 of the present invention, the influence of the aperture ratio on the light emission surface and the electrical resistance of the GaN substrate on the light output was measured. The aperture ratio was adjusted by changing the substrate area or the p electrode size and the n electrode size. As the test body, an LED having the structure shown in FIG. 1 was used. However, as shown in FIG. 43, a test body in which a fluorescent material 26 was arranged to form a white LED was also tested for some tests. There are three test bodies, Example F of the present invention and Comparative Examples G and H, in which the specific resistance of the GaN substrate does not fall within the scope of the present invention. Each of test bodies F, G, and H to be described later was prepared by sealing with an epoxy resin without including the fluorescent material shown in FIG. 1 and a white LED equipped with the fluorescent material shown in FIG. The aperture ratio was {(p electrode area−n electrode area) / p electrode area} × 100 (%).

In Example F of the present invention, L _P0 = L _N0 = 5.05 mm, D = 100 μm, and the aperture ratio is almost 100%. In Comparative Example G, L _P0 = L _N0 = 5.05 mm, D = 100 μm, and the aperture ratio is 97%. Further, L _P0 = L _N0 = 5.05 mm, D = 4.3 mm of Comparative Example H, and the aperture ratio is 77%. The manufacturing method of the above-mentioned Invention Example F and Comparative Examples G and H will be described below.

(Invention Sample F)
(F1)-(f7) The same process as the corresponding process in Invention Example A was performed.
(F8) After that, a dividing process by etching was performed so as to obtain a predetermined shape, and a chip was obtained as a light emitting device. The obtained light emitting device has a regular hexagonal plan shape, and L _P0 = L _N0 = 5.05 mm, L _P1 = 5 mm, and D = 100 mm.
(F9)-(f11) The same process as the corresponding process in Invention Example A was performed.
(F12) Separately from the above (f11), after mounting the fluorescent material on the n-electrode side above the one mounted on the lead frame mount in (f9), resin sealing with epoxy resin is performed to emit white light. A lamp was also made. For this, a fluorescent material capable of obtaining 180 lm per watt of 450 nm light output was used.

(Comparative Example G)
(G1) An n-type GaN off-substrate shifted by 0.5 ° from the c-plane was used. A specific resistance of 0.6 Ω · cm and higher than the range of 0.5 Ω · cm in the present invention were selected. This G
The dislocation density of the single crystal region surrounded by the plate-like crystal inversion region 51 of the aN substrate was 1E6 / cm ² and the thickness was 400 μm.
(G2) to (g7) The same processes as those in Example F of the present invention were performed.
(G8) After that, a dividing process by etching was performed so as to obtain a predetermined shape, and a chip was obtained as a light emitting device. The obtained light emitting device has a regular hexagonal planar shape, and L _P0 = L _N0 = 0.8 mm, L _P1 = 0.75 mm, and D = 100 μm.
(G9)-(g12) The same process as the corresponding process in Invention Example F was performed.

(Comparative Example H)
(H1) An n-type GaN off-substrate shifted by 0.5 ° from the c-plane was used. A specific resistance of 0.6 Ω · cm and higher than the range of 0.5 Ω · cm in the present invention were selected. The dislocation density of the single crystal region surrounded by the plate-like crystal inversion region 51 of this GaN substrate was 1E6 / cm ² and the thickness was 400 μm.
(H2) to (h7) The same processes as those in Example F of the present invention were performed.
(H8) After that, a dividing process by etching was performed so as to obtain a predetermined shape, and a light-emitting device was obtained as a chip. The obtained light emitting device has a regular hexagonal plan shape, and L _P0 = L _N0 = 5.05 mm, L _P1 = 5 mm, and D = 4.3 mm.
(H9) to (h12) The same processes as those in Example F of the present invention were performed.

(Experiment and its results)
(1) For the inventive example F and comparative examples G and H, the current distribution in a range where the current spreads relatively uniformly from the n-electrode to the MQW layer was calculated by simulation. This simulation result is reflected in the element design of Example F of the present invention and Comparative Examples G and H. FIG. 44 shows an image diagram of current spreading. FIG. 45 is a diagram showing a current density ratio at a distance r, where r is a radial distance from the center of the MQW light-emitting layer 4. The current density is 1 at the center of the n electrode. (I) Result of Invention Example F: The current density was highest immediately below the n electrode, and the current density decreased as the distance from the n electrode was increased. In addition, the range in which a current density of 1/3 or more directly under the n electrode was obtained was 12 mm in diameter centering directly under the n electrode. Based on this result, the size of the light emitting device was set to a size included therein. On the N surface, which is the second main surface of the GaN substrate, an n-type electrode having a diameter of 100 μm was attached to the center of the chip every 8.78 mm by photolithography, vapor deposition, and lift-off method. In this case, the portion without the n-type electrode on the N surface of the GaN substrate, that is, the aperture ratio is almost 100% per element. The thickness, heat treatment, and contact resistance are the same as Example A of the present invention. (Ii) Results of Comparative Example G: The range in which a current density of 1/3 or more directly below the n electrode was obtained was 1.4 mm in diameter centering directly below the n electrode. Accordingly, the present invention example E and the size of the n-electrode were combined to a diameter of 100 μm, and the chip size was a regular hexagon with one side L _P1 included in the diameter of 1.4 mm = 0.75 mm. Therefore, an n-type electrode having a diameter of 100 μm was attached to the center of the chip every 1.42 mm by photolithography technique, vapor deposition, and lift-off method on the N surface of the GaN substrate. In this case, the aperture ratio is approximately 99% per element. The thickness, heat treatment, and contact resistance are the same as those of Examples A to E of the present invention. (Iii) In Comparative Example H, the chip size of the inventive example E and the chip size were combined to be the same as the chip size of the inventive example E. The electrical resistance of the GaN substrate is the same as that of Comparative Example G, and the current spread is 1.4 mm in diameter. Therefore, when the current is to flow uniformly through Comparative Example H (1/3 or more directly below the n-type electrode) ), The n electrode needs a diameter of 4.3 mm. Therefore, the second main surface (light emission surface) of the GaN substrate is formed with a diameter of 4.78 mm every 8.78 mm by photolithography technique, vapor deposition, and lift-off method in consideration of the etching allowance in the dividing step by etching. A 3 mm n-electrode was attached. In this case, the aperture ratio is approximately 77% per element.

  (2) The present invention F and Comparative Examples G and H, which are not mounted with a fluorescent material, are mounted in an integrating sphere, and then a predetermined current is applied to collect and output light from the detector. The values were compared. The results are shown in FIGS. 46 and 47.

  When a current of 20 mA was applied, Examples F and Comparative Examples G and H resulted in outputs of 8 mW, 8 mW, and 6.2 mW, respectively, so as to match the area ratio of the portion where no electrode was disposed. The highest light output was obtained in Invention Example F and Comparative Example G. Therefore, when 500 A of 10 A was further applied, the outputs of 4 W and 3.1 W were obtained in the invention example F and the comparative example H in accordance with the area ratio of the portion where no electrode was arranged.

In Comparative Example G, the output increased in proportion to the increase in applied current until the current density of the light emitting portion was 110 A / cm ² . However, the output was saturated as the temperature increased due to heat generation thereafter, and the light emitting device was broken by the application of the current 10A.

  Moreover, the result of having measured the brightness | luminance of said 3 types of test body is shown in FIG. 48 and FIG. FIG. 48 is a diagram showing the relationship between the applied current of the LED that is whitened by arranging the fluorescent material and the obtained luminance, and FIG. 49 is a diagram showing the relationship between the current density and the luminance similarly. In the present invention example F and comparative example H, even when the same fluorescent material is used, the luminance obtained varies depending on the area ratio of the portion where no electrode is arranged, so that the applied current of 10 A is 720 lm / chip, 234 lm / chip. became. Comparative Example G was damaged when a current of 10 A was applied. According to FIG. 48 and FIG. 49, only the present invention example F was able to obtain a high luminance at a high current.

  The reason why the current application is set to 10 A at the maximum in this embodiment is that if the current is increased further, the Joule heat generation density at the n electrode becomes too large and the heat generation may increase.

If the n-electrode is enlarged or the contact resistance is sufficiently lowered, the same effect can be obtained up to a maximum current of 70 A with respect to a current density of 110 A / cm ² .

(Invention Examples F-2 and F-3)
Therefore, the same processing as in Invention Example F was performed, and in Invention Example F-2, the diameter D of the n-electrode was set to 1 mm (area 0.785 mm ² ) and arranged at the center of the GaN substrate. Further, in Example F-3 of the present invention, the n-electrode was set to 450 μm □ and arranged at six corners of the GaN substrate (see FIGS. 39 and 40). As shown in FIGS. 39 and 40, the n electrodes located at the six corners are electrically connected to the lead frame by bonding wires, respectively. Au wire is used as the bonding wire, and the cross-sectional diameter is 300 μm. In this case, the aperture ratio is almost 100%. In addition, a reflection cup 37, which is a cup-shaped reflector, was disposed in the same manner as in the inventive example C1.

  As in Invention Example F, a non-fluorescent material-mounted one was inserted into an integrating sphere, and then light was emitted by applying a predetermined current. When the light output value output from the detector for condensing the light was measured, it was 8 mW when a current of 20 mA was applied, 4 W when the applied current was 10 times 500 times the above, and 28 W when 70 A was applied. The output could be obtained.

  In addition, in the case of an LED that was whitened by arranging a fluorescent material, a luminance of 5040 lm / chip could be obtained.

  Of course, it is possible to arrange a large number of light emitting devices with a small size and a relatively small applied current to obtain the same output, but there is a certain distance between the elements for the positional accuracy of the element arrangement and to avoid electrical shorts. This is not practical because the overall size becomes extremely large, or if each element is electrically connected, the cost becomes extremely high. According to the present invention, such a problem can be avoided, and the same number of manufacturing processes as in the prior art can be used to obtain a high light output with substantially the same cost and the minimum size.

Even if the emission wavelength or the layer structure is changed or if the substrate characteristics are equivalent, an Al _x Ga _1-x N substrate (where x is greater than 0 and less than or equal to 1) may be used instead of the GaN substrate. Needless to say, it is effective.

  As shown in FIGS. 39 and 40, by electrically connecting the n-electrode located at the corner of the GaN substrate and the lead frame with six Au wires having a radius of 150 μm, the electrodes and wires can obstruct light extraction. Therefore, it is possible to further increase the light output.

  In Example 4 of the present invention, the influence of the GaN substrate thickness on the light output will be described. The light absorption of the GaN substrate was measured using three specimens of Invention Examples I, J, and K having the same structure as the LED shown in FIG. A method for producing the test body will be described.

(Invention Sample I)
(I1) An n-type GaN off-substrate shifted by 0.5 ° from the c-plane was used. The specific resistance of this GaN substrate was 0.01 Ω · cm, and the dislocation density of the single crystal region surrounded by the plate-like crystal inversion region 51 was 1E6 / cm ² . This GaN substrate had a thickness of 100 μm. In the GaN substrate, plate-like crystal inversion regions 51 (see FIG. 8) distributed in parallel in the thickness direction of the GaN substrate are formed.
(I2) The following layers were formed in order on the first main surface of the GaN substrate by MOCVD. That is, (MQW layer in which two layers of GaN buffer layer / Si doped n-type GaN layer / Si doped n-type Al _0.2 Ga _0.8 N layer / GaN layer and In _0.05 Ga _0.95 N layer are stacked in three layers) A stacked structure of / clad layer Mg-doped p-type Al _0.2 Ga _0.8 N layer / Mg-doped p-type GaN layer) was formed. In addition, as shown in FIG. 8, the plate-like crystal inversion region 51 of the GaN substrate propagates in the laminated structure.
(I3) The emission wavelength was 380 nm, and the internal quantum efficiency calculated for convenience by comparing the PL intensity at a low temperature of 4.2K and the PL intensity at a room temperature of 298K was 50%.
(I4) The same process as the corresponding process in Invention Example A was performed.
(I5) First, the range in which the current spreads relatively uniformly from the dotted n-electrode to the MQW layer was calculated by simulation. As a result, the current density was the largest directly under the n electrode, and the current density decreased as the distance from the n electrode was increased. In addition, since the range in which a current density of 1/3 or more directly under the n electrode is obtained is 3 mm in diameter centering directly under the n electrode, the length of one side L _P0 = L so that the shape of the light emitting device is included therein. _A regular hexagon having _N0 = 1.55 mm was used. On the N surface of the GaN substrate, n-type electrodes having a diameter of 100 μm were attached every 2.8 mm by photolithography, vapor deposition, and lift-off method. In this case, the portion without the n-type electrode on the Ga surface of the GaN substrate, that is, the aperture ratio is approximately 100% per element. The thickness, heat treatment, and contact resistance are the same as Example A of the present invention.
(I6)-(i7) The same process as the corresponding process in Invention Example A was performed.
(I8) After that, a dividing process by etching was performed so as to obtain a predetermined shape, and a light-emitting device was formed as a chip. The planar shape of the obtained light-emitting device is a regular hexagon with one side length L _P0 = L _N0 = 1.6 mm.
(I9) to (i11) The same processes as those in Example A of the present invention were performed.

(Invention Sample J)
(J1) An off substrate of Al _x Ga _1-x N shifted by 0.5 ° from the c-plane was used. The specific resistance was 0.01 Ω · cm, and the dislocation density of the single crystal region surrounded by the plate-like crystal inversion region 51 was 1E6 / cm ² . The thickness of the n-type Al _x Ga _1-x N substrate was 100 μm. Three kinds of Al atomic ratios x = 0.2, 0.5, 1 were used. Further, on the substrate, plate-like crystal inversion regions 51 (see FIG. 8) distributed in parallel in the thickness direction of the GaN substrate are formed.
(J2) The following laminated structure was formed on the first main surface of the Al _x Ga _1-x N substrate by MOCVD. (Clad layer Si-doped n-type clad Al _0.2 Ga _0.8 N / GaN and In _0.05 Ga _0.95 N two-layer MQW layer / clad layer Mg-doped p-type Al _0.2 Ga _0.8 N layer / Mg A doped p-type GaN layer) is formed in order. In addition, as shown in FIG. 8, the plate-like crystal inversion region 51 of the GaN substrate propagates in the laminated structure.
(J3) to (j4) The same processing as that in Example I of the present invention was performed.
(J5) On the second main surface of the Al _1-x Ga _x N substrate, n-electrodes having a diameter of 100 μm were attached every 2.8 mm by photolithography, vapor deposition, and lift-off method. The n-electrode is in contact with the second main surface of the Al _1-x Ga _x N substrate to form a laminated structure of (Ti layer 20 nm / Al layer / 100 nm / Ti layer 20 nm / Au layer 200 nm) in order from the bottom. Configured. This was heat-treated in an inert atmosphere so that the contact resistance was 1E-4 Ω · cm ² or less.
(J6) to (j11) The same processing as that in Example I of the present invention was performed.

(Comparative Example K)
(K1) An n-type GaN off-substrate shifted by 0.5 ° from the c-plane was used. The specific resistance of this GaN substrate was 0.01 Ω · cm, and the dislocation density of the single crystal region surrounded by the plate-like crystal inversion region 51 was 1E6 / cm ² . The GaN substrate had a thickness of 1 mm (1000 μm). In the GaN substrate, plate-like crystal inversion regions 51 (see FIG. 8) distributed in parallel in the thickness direction of the GaN substrate are formed.
(K2) to (k4) The same processes as those in Example I of the present invention were performed.
(K5) The size of the light emitting element (chip) was the same as that of Example G of the present invention. On the second main surface of the GaN substrate, n-type electrodes having a diameter of 100 μm were attached every 2.8 mm by photolithography, vapor deposition, and lift-off method. In this case, the ratio of the second main surface (light emitting surface) of the GaN substrate where no n-electrode is present, that is, the aperture ratio is approximately 100% per element. The thickness, heat treatment, and contact resistance were the same as in Invention Example I.
(K6) to (k11) The same processing as that in Invention Example I was performed.

(Experiment and its results)
First, the substrates 1 of Invention Examples I and J and Comparative Example K having different substrate thicknesses were prepared, and the transmittance for incident light having a wavelength of 380 nm was measured. 50 and 51 show an outline of the light transmittance measurement test. The thickness of Comparative Example K is as thick as 1 mm (1000 μm) as compared to Inventive Examples I and J of 100 μm. The test results are shown in FIG.

  According to FIG. 52, the transmittances of Examples I and J of the present invention and Comparative Example K were 70%, 90% and 10%, respectively. In Example J of the present invention, three types of substrates were prepared: Al atomic ratio x = 0.2, 0.5, and 1, and the transmittance was 90%.

Therefore, the present invention Examples I and J and Comparative Example K, which are white LEDs with a fluorescent material, are mounted in an integrating sphere, and then a predetermined current is applied to collect and output from the detector. The values were compared. When a current of 20 mA was applied, outputs of 4.2 mW, 5.4 mW (all three types) and 0.6 mW were obtained in Invention Examples I and J and Comparative Example K. This difference is due to the difference in the transmittance of each substrate. In the case of a GaN substrate, the light transmittance is extremely small at a wavelength shorter than 400 nm. _{By using} xGa1 _-xN , high light extraction can be obtained.

  Also, high light extraction can be obtained by thinning the GaN substrate. Even if the thickness is too thin, the current spreading range from the n-electrode to the MQW becomes too small, and if it is too thick, the extraction efficiency deteriorates as described above, so that the thickness is preferably 50 μm to 500 μm, although it depends on the emission wavelength. . Further, by using a thin GaN substrate having a thickness of about 100 μm as in the present invention example, it is possible to reduce the manufacturing cost of the GaN substrate and to manufacture a light emitting device at a lower cost. It goes without saying that the cost can be reduced by reducing the substrate thickness regardless of the emission wavelength.

  In Example 5 of the present invention, the manufacturing yield of the thickness of the n-type GaN layer formed on the substrate will be described. The test bodies used are the present invention example L having the same structure as the present invention example A using the GaN substrate, and the comparative examples M and N having the same structure as the comparative example B using the sapphire substrate.

(Invention Sample L)
(L1) The same process as the corresponding process in Invention Example A is performed.
(L2) The following laminated structure is formed by MOCVD (see FIG. 2). (GaN substrate / GaN buffer layer / Si doped n-type GaN layer 2 / Clad layer Si-doped n-type Al _0.2 Ga _0.8 N layer / MQW layer in which two layers of GaN layer and In _0.1 Ga _0.9 N layer are stacked in three layers) / Mg-doped p-type Al _0.2 Ga _0.8 N layer / Mg-doped p-type GaN layer). Referring to FIG. 2, the thickness t of the Si-doped n-type GaN layer 2 was 100 nm.
(L3)-(l11) The same process as the corresponding process in Invention Example A was performed. At this time, if the etching groove 25 is formed for element isolation, the etching groove bottom 25a does not become completely flat as shown in FIG. In the case of the present invention example L, as described above, even if the central portion reaches the GaN substrate or the buffer layer, no electrode or the like is provided in this portion. However, the effect on manufacturing yield is small.

(Comparative Example M)
(M1) A process similar to the corresponding process in Comparative Example B was performed.
(M2) The following laminated structure was formed on the sapphire substrate by MOCVD (see FIG. 34). (Sapphire substrate / GaN buffer layer / Si doped n-type GaN layer / Si doped n-type Al _0.2 Ga _0.8 N layer / clad layer MQW layer in which two layers of GaN layer and In _0.1 Ga _0.9 N layer are stacked in three layers / Mg-doped p-type Al _0.2 Ga _0.8 N layer / Mg-doped p-type GaN layer). Referring to FIG. 34, the thickness of the Si-doped n-type GaN layer 102 was 3 μm.
(M3)-(m11) The same process as the corresponding process in Comparative Example B was performed. At this time, when the element isolation etching groove 125 is formed, the etching groove bottom portion 125a does not become completely flat as shown in FIG. However, in the case of the comparative example M, since the thickness of the Si-doped n-type GaN layer 102 is as thick as 3 μm, the central portion does not reach the buffer layer or the sapphire substrate as described above. As a result, even if the depth in this portion and the flatness of the bottom portion vary somewhat, the influence on the manufacturing yield is small.

(Comparative Example N)
(N1) The same process as the corresponding process in Comparative Example B was performed.
(N2) The following laminated structure was formed on the sapphire substrate surface by MOCVD (see FIG. 34). (GaN buffer layer / Si-doped n-type GaN layer / Clad layer Si-doped n-type Al _0.2 Ga _0.8 N layer / MQW layer / cladding layer in which two layers of a GaN layer and an In _0.1 Ga _0.9 N layer are stacked in three layers) The Mg-doped p-type Al _0.2 Ga _0.8 N layer / Mg-doped p-type GaN layer was formed with reference to Fig. 34. The thickness of the Si-doped n-type GaN layer 102 was 100 nm.
(N3)-(n4) The same process as the corresponding process in Comparative Example B was performed.
(N5) In the case of Comparative Example N, a GaN-based multilayer film having a lattice constant different from that of sapphire is grown on the sapphire substrate, so that a good-quality multilayer film can be obtained if the n-type GaN layer is too thin at 100 nm. The light emission output becomes extremely small.

In the case of Comparative Example N, since the sapphire substrate is an insulator, the n electrode needs to be provided on the same growth film side as the p electrode. Therefore, the n-type GaN layer is exposed to provide an n-type electrode by etching this wafer with Cl-based gas from the Mg-doped p-type layer side to the Si-doped n-type GaN layer by photolithography and RIE. I tried. However, as shown in FIG. 55, in this comparative example N, since the thickness of the Si-doped n-type GaN layer is as thin as 100 nm (0.1 μm), the n-type GaN layer cannot be uniformly exposed in the wafer. For this reason, the exposed surface was an n-type Al _x Ga _1-x N layer or a GaN buffer layer depending on the location. Wet etching was attempted using hot phosphoric acid, but the results were the same for any etchant.

(Experimental result)
As a result of measuring the optical output in the same manner as in Example 1, in Example L of the present invention, an output of 8 mW was obtained at an applied current of 20 mA. On the other hand, in the comparative example M, an output of 7.2 mW was obtained with the same applied current. In the structure of Invention Example L, the same output could be obtained even if the thickness of the n-type GaN layer was reduced from 3 μm to 100 nm. Further, since the n-electrode can be provided on the N surface of the conductive GaN substrate, it is not necessary to expose the Si-doped n-type GaN layer.

  The thickness of the light-emitting element grown on the substrate is usually 6 μm or less at most, although it depends on the target wavelength and output, and the thickness of the Si-doped n-type GaN layer occupying most of it is 3 μm in the present invention example. To 100 nm. As a result, according to the example of the present invention, the cost of film growth can be drastically reduced.

  As described in the processing step (n5) of the test body of Comparative Example N, when the n-type GaN layer is made as thin as 100 nm (0.1 μm), the yield of n-type GaN layer exposure is very poor and is not practical. Further, even if uniform exposure is realized by future technological advancement, since the thickness of the layer is too thin, the current flowing in the n-type GaN layer in a direction parallel to the layer as in Comparative Example B in Example 1 The current density becomes excessively large and heat generation increases, so that practical light output cannot be obtained (see FIG. 55). Of course, it goes without saying that the same effect can be obtained even when the fluorescent material is used in white or when the emission wavelength is changed.

In Example 6 of the present invention, the influence of the dislocation density of the GaN substrate on the light output will be described. The test specimens used are two bodies of the invention example O having the same structure as the invention example A, a dislocation density of 1E6 / cm ² , and a comparative example P having a dislocation density of 1E9 / cm ² .

(Invention Sample O)
(O1) An n-type GaN off-substrate shifted by 0.5 ° from the c-plane was used. The specific resistance of the GaN substrate is 0.01 Ω · cm. In the GaN substrate, plate-like crystal inversion regions 51 (see FIG. 8) distributed in parallel in the thickness direction of the GaN substrate are formed. The dislocation density of the regular hexagonal single crystal region surrounded by the plate crystal inversion region 51 was 1E6 / cm ² . The thickness of this GaN substrate was 400 μm.
(O2) to (o11) The same process as the corresponding process in Invention Example A was performed.

(Comparative Example P)
(P1) An n-type GaN off-substrate shifted by 0.5 ° from the c-plane was used. The specific resistance of the GaN substrate is 0.01 Ω · cm. In the GaN substrate, plate-like crystal inversion regions 51 (see FIG. 8) distributed in parallel in the thickness direction of the GaN substrate are formed. The dislocation density of the regular hexagonal single crystal region surrounded by the plate crystal inversion region 51 was 5E8 / cm ² . The thickness of the GaN substrate was 400 μm, which is the same as Example O of the present invention.
(P2) to (p11) The same processing as that in Example A of the present invention was performed.

(Experimental result)
As in Example 1, the optical output was measured. As a result, in Invention Example O and Comparative Example P, an output of 8 mW was obtained at an applied current of 20 mA, and outputs of 40 mW and 30 mW were obtained at an applied current of 100 mA, respectively. Thus, the inventive example O can obtain a higher light output when compared with the comparative example P.

  The invention example O and the comparative example P have the same specific resistance, thickness, and the like, and thus generate heat and release heat. In order to confirm that the difference in light output was not affected by heat, a pulse current of 100 μs cycle with a duty ratio of 1% and an application time of 1 μs was applied for comparison. This test result was the same as the above-mentioned result, and outputs of 40 mW and 30 mW were obtained at an applied current of 100 mA, respectively.

  Therefore, although the mechanism is not necessarily clear, a difference in light emission output at a high current density was obtained due to a difference in dislocation density rather than a thermal effect. Moreover, it has been confirmed by the inventors' experiment that the same effect can be obtained even when the emission wavelength or the layer structure is changed, or when the fluorescent material is white.

  In the seventh embodiment of the present invention, the influence of non-specularization of the surface and the end surface on the light output will be described. The specimens used are Examples Q and R of the present invention. Example Q of the present invention is the LED shown in FIG. 56 with the surface and end surfaces being made non-specular, and Example R of the invention is the LED shown in FIG. 57 without being made non-specular.

(Invention Sample Q)
(Q1)-(q6) The same process as the corresponding process in Invention Example F was performed.
(Q7) In order to make the N-face and element end face of the GaN substrate non-specular, the present invention example was carried out without carrying out the step (the step of forming a protective mask) shown in (f7) in the production method of the present invention example F The process shown in (f8) in the manufacturing method of F is performed. The non-mirror surface may be dry etching such as RIE or wet etching. A mechanical polishing method may be used in addition to such a non-mirror surface method by etching. In this embodiment, as described above, the wet etching method using a KOH aqueous solution as an etchant was applied. When wet etching is performed only for the non-specularization of the N surface of the GaN substrate, a 4 mol / l aqueous KOH solution is sufficiently stirred while maintaining the temperature at 40 ° C., and then the wafer is stirred for 30 minutes. You may use the method of immersing in. Even in this case, the N-face and the element end face of the GaN substrate can be made non-specular.
(Q8)-(q11) The same process as the corresponding process in Invention Example F was performed.

(Comparative Example R)
This is the same as Example F of the present invention.

(Experimental result)
As a result of measuring the optical output in the same manner as in Example 1, Examples Q and R of the present invention obtained outputs of 4.8 W and 4 W, respectively, at an applied current of 10 A. Further, when the fluorescent material was provided to be white, an output of 1150 lm was obtained in the invention example Q and 960 lm was obtained in the comparative example R at an applied current of 10 A. That is, in Example Q of the present invention, a higher light emission output could be obtained. Needless to say, the same effect can be obtained even when the emission wavelength is changed. This is because, when the surface and the end face of the substrate and the n-type GaN layer are in a mirror state, total reflection is likely to occur on the surface of GaN having a high refractive index as shown in FIG. . On the other hand, when it is made non-specular as shown in FIG. 57, the light emission efficiency to the outside can be increased.

  In addition, when using KOH aqueous solution for non-specularization, it is known from the experiment of the inventors that the same effect can be obtained if the concentration is 0.1 to 8 mol / l and the temperature is in the range of 20 to 80 ° C. .

  In Example 8 of the present invention, the influence of the reflectance of the p-type electrode on the light output will be described. The test bodies used were five examples S, T, U, V, and W of the present invention examples.

(Invention Sample S)
(S1) to (s5) The same processes as those in Example F of the present invention were performed.
(S6) The p-electrode is manufactured by the following method. A 4 nm thick Ni layer and a 4 nm thick Au layer are formed in this order from the lower layer in contact with the p-type GaN layer. Next, heat treatment is performed in an inert atmosphere. Thereafter, an Ag layer having a thickness of 100 nm is formed on the Au layer. The contact resistance of the p-electrode produced by the above method was 5E-4 Ω · cm ² .

Moreover, the transmittance | permeability was measured after performing the same heat processing to the p electrode which contacted on the glass plate and formed in order from the lower layer (4 nm-thickness Ni layer / 4 nm-thickness Au layer). As a result, the transmittance for incident light of 450 nm from the Ni layer side was 70%. Further, an Ag layer having a thickness of 100 nm was attached to a glass plate, and the reflectance was measured. As a result, a reflectance of 88% was obtained with respect to 450 nm incident light. Therefore, (4 nm thick Ni layer / 4 nm thick Au layer / 100 nm Ag layer) was formed on a glass plate with the Ni layer as the lower layer, and the reflectance was measured after the same heat treatment. As a result, a reflectivity of 44% was obtained for 450 nm incident light. This reflectivity is such that incident light with a wavelength of 450 nm is transmitted with a transmittance of 70% through the Ni layer with a thickness of 4 nm / Au electrode layer with a thickness of 4 nm and then reflected with a reflectance of 88% with the Ag layer. It corresponds to the reflectance that the (4 nm-thickness Ni layer and 4 nm-thickness Au electrode layer) are transmitted at 70% transmittance.
(S7)-(s11) The same process as the corresponding process in Invention Example F was performed.

(Invention Sample T)
(T1)-(t5) The same process as the corresponding process in Invention Example F was performed.
(T6) The p-electrode is manufactured by the following method. On the p-type GaN layer, a 4 nm thick Ni layer and a 4 nm thick Au layer are formed in order from the bottom. Thereafter, heat treatment is performed in an inert atmosphere. Next, an Al layer having a thickness of 100 nm and an Au layer having a thickness of 100 nm are formed on the Au layer. The contact resistance of the p-electrode produced by the above method was 5E-4 Ω · cm ² .

Of these electrodes, the transmittance was measured after applying the same heat treatment by attaching a laminated film of (Ni layer with a thickness of 4 nm / Au layer with a thickness of 4 nm) to a glass plate. 70%. Furthermore, the reflectance was measured by attaching an Al layer having a thickness of 100 nm to a glass plate. As a result, it was 84% with respect to incident light of 450 nm. Further, a laminated film (4 nm thick Ni layer / 4 nm thick Au layer / 100 nm thick Al layer) was formed on a glass plate in order from the bottom, and the reflectance was measured after the same heat treatment. As a result, a reflectance of 42% was obtained with respect to 450 nm incident light. This reflectivity is such that incident light with a wavelength of 450 nm is transmitted at a transmittance of 70% through (4 nm thick Ni layer / 4 nm thick Au electrode layer), then reflected at the Al layer with a reflectivity of 42%, and again This coincides with the reflectance calculated when the (4 nm thick Ni layer / 4 nm thick Au electrode layer) is transmitted at a transmittance of 70%.
(T7)-(t11) The same process as the corresponding process in Invention Example F was performed.

(Invention Sample U)
(U1)-(u5) The same process as the corresponding process in Invention Example F was performed.
(U6) As the p-electrode, Rh having a thickness of 100 nm was applied to the p-type GaN layer with a thickness of 100 nm, which is ohmic with respect to the p-type GaN layer and has a high reflectance. The contact resistance is 5e-4 Ω · cm ² . Further, the Rh of this electrode was attached to a glass plate and the transmittance was measured. As a result, it was 60% with respect to 450 nm incident light.
(U7) to (u11) The same processes as those in Example F of the present invention were performed.

(Invention Sample V)
(V1)-(v7) The same process as the corresponding process in Invention Example S was performed.
(V8) As in the manufacturing method of Invention Example Q, the dividing step by etching is performed without forming a protective mask. At this time, the second main surface of the substrate on which the n-electrode is formed is simultaneously subjected to non-specular treatment by etching.
(V9) to (v11) The same processing as that in the invention sample S was performed.

(Invention Sample W)
Invention Example W is the same as Invention Example F.

(Experimental result)
As a result of measuring the optical output in the same manner as in Example 1, the inventive examples S, T, U, V and W were 4.8 W, 4.8 W, 5.2 W, 5.8 W and An output of 4 W was obtained. FIG. 58 is a schematic diagram of reflection on the mounting side of Examples S and T of the present invention, FIG. 59 is a schematic diagram of reflection on the mounting side of Example U of the present invention, and FIG. A schematic diagram is shown in FIG. In the present invention examples S and T, the highly reflective layer 35 is disposed between the p electrode 12 and the conductive adhesive 14, whereas in the present invention example U, the p electrode 12 itself is made of a highly reflective material, In Example V of the present invention, it is further non-specular. Further, in the invention sample W, no special consideration is given to the reflection on the mounting side.

  In the present invention examples S, T, U, and V, when a fluorescent material was provided to form a white LED, outputs of 864 lm, 864 lm, 936 lm, and 1044 lm were obtained at an applied current of 10 A, respectively. According to these results, the p-electrode is formed of a high-reflectivity material, or a high-reflectivity material is disposed between the p-electrode and the conductive adhesive, so that the light can be effectively used and the light output can be improved. Can be improved. That is, it was possible to further improve the light emission output by incorporating a reflective film of Ag, Al, or Rh into the electrode layer, or between the p electrode and the conductive adhesive. Further, as in the present invention example V, the N surface and the end surface of the GaN substrate are made non-mirror surfaces, and further improvement is possible.

  When the emission wavelength is changed, the reflectivity in the Ag layer or Al layer and the absorption rate in the Au and Ni layers change, so the degree of effect cannot be generally stated, but it goes without saying that any wavelength is effective. . It is also possible to obtain an equivalent or better effect using an element having an equivalent or higher work function instead of Rh and having an equivalent or higher reflectance.

  In Example 9 of the present invention, the relationship between the oxygen concentration of the GaN substrate, the specific resistance, and the light transmittance was determined. Based on this relationship, p-down mounting, that is, in a light emitting device having a GaN substrate as a light emission surface, is characterized in that an optimum relationship between the GaN substrate thickness and the oxygen concentration is established for a predetermined light emission area. As described above, since the light emission surface is a GaN substrate in the p-down mounting, the oxygen concentration having a large influence on the specific resistance and the light transmittance is particularly important as described below.

FIG. 61 is a diagram showing the influence of the oxygen concentration on the specific resistance of the GaN substrate. From FIG. 61, a specific resistance of 0.5 Ωcm or less can be realized by setting the oxygen concentration to 1E17 / cm ³ or more. FIG. 62 is a diagram showing the influence of the oxygen concentration on the transmittance of light having a wavelength of 450 nm when the GaN substrate is 400 μm. From the figure, it can be seen that when the oxygen concentration exceeds 2E19 atoms / cm ³ , the transmittance of light having a wavelength of 450 nm rapidly decreases. From FIG. 61 and FIG. 62, it can be seen that increasing the oxygen concentration reduces the specific resistance of the GaN substrate and is effective for enlarging the light emitting surface, but reduces the light transmittance. Therefore, how to set the oxygen concentration, the thickness of the GaN substrate, and the planar size of light emission is very important for a GaN substrate used for a light-emitting element mounted in a p-down manner.

  FIG. 63 is a diagram showing the results of measuring the plane size in which the light output and current of the lamp uniformly flow when a lamp is manufactured from a GaN substrate with the thickness and oxygen concentration varied with respect to Example A of the present invention. Regarding the light output of the lamp, the light output tends to decrease as the thickness increases and the oxygen concentration increases. As for the maximum planar size through which current flows uniformly, the thickness tends to increase as the thickness increases and the oxygen concentration increases.

From FIG. 63, for example, when the plane size in which the current flows uniformly is a square with a side of 4 mm (side of 5 mm) (or a regular hexagon with a side of 2.8 mm (or side of 3.5 mm)), the present invention as an optical output. when it is desired to obtain a 8mW or equivalent at 20mA applied at a magnitude of example a, if 6E18 atoms / cm ³ or more an oxygen concentration in the GaN substrate having a thickness of 200μm (8E18 atoms / cm ³ or more in one side 5mm square), the present invention In the size of Example A, uniform light emission can be obtained after securing an optical output of 8 mW or more when 20 mA is applied. That is, when the current density is combined with 20 mA application in a regular hexagon having a side of 236 μm in the size of the invention example A, a square of 4 mm (5 mm on one side) corresponds to 3.6 A (5.6 A) application (2.8 mm on one side). (Regarding a regular hexagon with a side of 3.5 mm, this corresponds to applying 4.5 A (7 A).) When applying 3.6 A (5.6 A), the optical output is 1.4 W (2.3 W) or more in proportion to the applied current ( When the chip shape is a regular hexagon, it is possible to obtain uniform light emission after securing a light output of 1.8 mW (2.8 mW or more) when 4.5 A (7 A) is applied.

By addition, the GaN substrate having a thickness of 400 [mu] m, when the same target performance as that of the thickness 200 [mu] m, and 3E18 atoms / cm ³ or more in one side 4mm square (in the case of side 5mm square, oxygen concentration 4E18 / cm ³ or higher) That's fine. However, at a thickness of 400 μm, unless the oxygen concentration is 2E19 / cm ³ or less, the light output equivalent to 8 mW or more cannot be obtained when 20 mA is applied in the size of Example A of the present invention.

Furthermore, in the case of a GaN substrate having a thickness of 600 μm, compared with an oxygen concentration of 2.5E18 / cm ³ or more in which a current flows uniformly in a square area of 4 mm on a side, the light output is equivalent to 8 mW when 20 mA is applied in the size of the present invention example A. The limit value of the oxygen concentration is only slightly higher than 2.5E18 / cm ³ . Therefore, the oxygen concentration range that satisfies the above two conditions is only a narrow range. On the other hand, since the oxygen concentration is more than about 2E18 / cm ^{3 in} which current flows uniformly in a 3 mm square area, the allowable range of oxygen concentration is slightly wider than that of a 4 mm square.

In addition, according to FIG. 63, when the thickness of the GaN substrate is 200 μm to 400 μm, a current is uniformly passed through a square with a side of 10 mm, and an output equivalent to 8 mW or more is obtained when 20 mA is applied with the size of the present invention example A. It can be seen that the range of oxygen concentration that can be made is sufficiently wide in practice. It can be seen that a thickness of 200 μm is possible at an oxygen concentration lower than an oxygen concentration of 2E19 / cm ³ . Further, when the thickness is 400 μm, an oxygen concentration of 8E18 / cm ³ or more is possible.

  Next, specific examples will be described. In the examples, the following specimens were used.

(Invention Sample S1): A GaN substrate having a thickness of 400 μm that is n-type with an oxygen concentration of 1E19 / cm ³ was used. The specific resistance of this GaN substrate is 0.007 Ωcm, and the transmittance for light with a wavelength of 450 nm is 72%. In assembling a light emitting device using the GaN substrate, the other conditions were the same as those of Example A of the present invention. That is, the planar size of the GaN substrate is such that the light emission surface is a regular hexagon with a side length of 0.236 mm (see (a1) in Example 1), and (a2) the first GaN substrate of MOCVD is used. The following laminated structure was formed on the Ga surface which is the main surface. (SiW doped n-type GaN layer / Si doped n type Al _0.2 Ga _0.8 N layer / GaN layer and In _0.15 Ga _0.85 N layer, three layers of MQW / clad layer Mg doped p) Type Al _0.2 Ga _0.8 N layer / Mg-doped p-type GaN layer).

(Comparative Example T1): A GaN substrate having a thickness of 400 μm and being n-type with an oxygen concentration of 5E19 / cm ³ was used. The specific resistance of this GaN substrate is 0.002 Ωcm, and the transmittance for light with a wavelength of 450 nm is 35%. Conditions other than those described above are the same as in the present invention example S1.

(Comparative Example T2): A GaN substrate having a thickness of 400 μm and being n-type with an oxygen concentration of 2E16 / cm ³ was used. The specific resistance of the GaN substrate is 1.0 Ωcm, and the transmittance for light with a wavelength of 450 nm is 90%. Conditions other than those described above are the same as in the present invention example S1.

  (Test and results thereof): When the p-down mounted light emitting element of the above test body was assembled and a current of 20 mA was applied, an optical output of 8 mW could be obtained in Example S1 of the present invention. On the other hand, only a light output of 4 mW was obtained in Comparative Example T1, and 5 mW was obtained in Comparative Example T2. The light output of 4 mW in Comparative Example T1 can be said to be an output corresponding to the transmittance of the GaN substrate. In Comparative Example T2, when the state of light emission was observed from the second main surface side of the GaN substrate which is the light output surface, the intensity of light emission was observed in the surface. That is, the light emission intensity is extremely strong around the n electrode, and the light emission intensity rapidly decreases as the distance from the n electrode increases. This is because the current flowing through the n-electrode does not sufficiently spread in the plane of the light-emitting element due to the large specific resistance of the GaN substrate. For this reason, light emission occurred only around the p-electrode where the current is concentrated. As a result, the light emission output of the entire light emitting device of Comparative Example T2 was inferior to that of Invention Example S1.

  Example 10 of the present invention is characterized in that an n-type AlGaN buffer layer and an n-type GaN buffer layer are disposed between a GaN substrate and an n-type AlGaN cladding layer 3. Usually, the substrate is warped, but the GaN substrate is particularly warped. For this reason, in the GaN substrate, as shown in FIG. 64, the off-angle also varies greatly within the substrate surface. FIG. 64 shows an example of off-angle distribution from the c-plane of a 20 mm × 20 mm GaN substrate. When an epitaxial film is formed on this GaN substrate and separated into light emitting elements and the optical output is measured, the region R1 with an off angle as small as 0.05 ° level located at the corner and an off angle of 1.5 ° level. The light emitting device formed in the large region R2 cannot obtain an optical output of 8 mW or more with respect to an applied current of 20 mA. This is due to the poor crystallinity of the epitaxial film formed on the GaN substrate. Therefore, as shown in FIG. 65, an n-type AlGaN buffer layer 31 having an intermediate lattice constant between the GaN substrate 1 and the AlGaN cladding layer 3 and an n-type GaN buffer layer 2 are arranged. An attempt was made to alleviate the difference in lattice constant. More specifically, it is characterized in that the n-type AlGaN buffer layer 31 is arranged at the above position.

  The test specimens used are as follows.

(Invention Sample S3): As shown in FIG. 64, the GaN substrate used is continuous within a 20 mm × 20 mm plane from an area where the off angle from the c-plane is 0.05 ° to a region where the angle is 1.5 °. It has changed. The specific resistance of this GaN substrate is 0.01 Ω · cm, the dislocation density of the single crystal region surrounded by the plate-like crystal inversion region 51 is 1E6 / cm ² , and the thickness is 400 μm. Using such a GaN substrate having an off-angle distribution, a light emitting device was fabricated from each position of the 20 mm × 20 mm substrate according to the manufacturing steps (a1) to (a11) of Example A of the invention of Example 1. . At this time, as shown in FIG. 65, an Al _0.15 Ga _0.85 N buffer layer having a thickness of 50 nm was disposed between the GaN substrate 1 and the n-type GaN buffer layer 2.

(Comparative Example T4): A GaN substrate having a 20 mm × 20 mm plane and having an off angle from the c-plane ranging from 0.05 ° to 1.5 ° was used. The specific resistance of this GaN substrate is 0.01 Ω · cm, the dislocation density of the single crystal region surrounded by the plate-like crystal inversion region 51 is 1E6 / cm ² , and the thickness is 400 μm. In accordance with the manufacturing steps (a1) to (a11) of Invention Example A of Example 1, a plurality of light emitting elements were produced from each position. In Comparative Example T4, an n-type GaN layer was formed in contact with the GaN substrate 1, and no Al _0.15 Ga _0.85 N buffer layer was disposed between the GaN substrate and the n-type GaN layer.

  (Test and results): When a current of 20 mA was applied to the light emitting element, in Example S3 of the present invention, light was emitted in a 0.05 to 1.5 ° region including the regions R1 and R2 of the 20 mm × 20 mm GaN substrate. An output of 8 mW or more was obtained (see FIG. 66). However, in Comparative Example T4, it was possible to obtain an optical output of 8 mW or more only in a light emitting device formed on a region with an off angle of 0.1 ° to 1.0 °. At 0.05 ° and 1.5 ° off-angle levels, an optical output of 8 mW was not achieved.

This is because in the present invention example S3, an epitaxial layer having excellent crystallinity can be formed by arranging the Al _0.15 Ga _0.85 N buffer layer as described above, even if a GaN substrate whose off-angle varies greatly is used. is there.

  In the eleventh embodiment of the present invention, an n-type AlGaN buffer layer and an n-type GaN buffer layer are disposed between the GaN substrate and the n-type AlGaN cladding layer 3 as in the tenth embodiment. This is characterized in that the hole-shaped concave portion shown in FIG. 67 which is generated when an epitaxial film is formed in the dislocation bundle portion generated in the region is eliminated.

  When forming a GaN substrate, in order to increase the crystallinity of the single crystal region, a region where dislocation bundles are concentrated and a single crystal region surrounded by the region are formed. Dislocation bundles can exist with probability. The dislocation bundle in the single crystal region is inherited by the p-type GaN layer 6 such as a p-type GaN layer as shown in FIG. 68 and appears as a core 61 on the epitaxial film. Therefore, the dislocation bundle density and the core density are almost the same. The core 61 becomes a hole-shaped recess as shown in FIG. 67 depending on the film formation conditions of the epitaxial film. The density of the hole-like recesses dramatically affects the manufacturing yield in the p-down mounted light emitting device having the GaN substrate as the emission surface.

(Invention Sample S2): A GaN substrate having a diameter of 2 inches in which one dislocation bundle was distributed per 1 μm × 1 μm was used. This corresponds to a dislocation bundle density of 1E4 / cm ² . As shown in FIG. 65, an Al _0.15 Ga _0.85 N buffer layer having a thickness of 50 nm was disposed between the GaN substrate 1 and the n-type buffer layer 2. Other conditions were the same as those of Example S1 of the present invention.

(Test and results)
After producing the epitaxial layer, the inside of the wafer on the epitaxial layer side was observed with a differential interference microscope and SEM (scanning electron microscope). As a result, it was confirmed that there was no hole-shaped recess as shown in FIG. All of the above GaN substrates having a diameter of 2 inches were assembled into a light emitting device except for an edge of about 5 mm from the outer periphery. The yield of obtaining light output of 8 mW or more was examined by extracting 20 light-emitting elements at a ratio of 1 to 50, applying a current of 20 mA. The result was 100% yield. If the above-mentioned yield is increased, it is considered that a yield close to 100%, which is less than 100%, is obtained due to manufacturing factors other than the hole-shaped recess. However, according to the yield test result focused on the hole-shaped recess, a particularly good yield of 100% could be obtained.

  In Example 12 of the present invention, a p-type InGaN layer having enhanced conductivity is disposed outside the MQW4 / p-type AlGaN cladding layer 5 / p-type GaN layer 6, and only an Ag electrode layer having high reflectivity is used as a p-electrode. It is characterized by the fact that is placed on the entire surface. Therefore, no other metal electrode considering the work function is provided. Since this structure has a high reflectivity at the bottom of the down side, the absorption of light generated when other metal electrodes are used is reduced, and the light emission efficiency can be increased.

  The test specimens are as follows.

(Invention Sample S4 (see FIG. 69)): Like the Invention Sample A, the following laminated structure is formed on the Ga surface which is the first main surface of the GaN substrate. / MQW4 / Mg-doped p-type Al _0.2 Ga _0.8 N layer 5 of cladding layer / Mg-doped p-type GaN layer 6 / Mg-doped InGaN layer 32 of 5 nm thickness In the above laminated structure, the thickness is in contact with the Mg-doped p-type GaN layer 6 It is characterized by having a 5 nm Mg-doped InGaN layer 32. Further, in the invention example A of Example 1, the Ni / Au electrode layer was formed in the processing step (a6), but the processing step of (a6) was not performed, and instead an Ag electrode layer 33 having a thickness of 100 nm was formed. did.

  (Comparative Example T5): In the structure of Invention Example A of Example 1, an Ag electrode layer having a thickness of 100 nm was further disposed in contact with the Ni / Au electrode layer.

  (Test and results): In the present invention example S4, the acceptor level is low because the p-type InGaN layer 32 is in contact with the p-type GaN layer 6. For this reason, even if the Ag reflection film 33 whose carrier function is increased and the work function is not so large is disposed as a p-electrode in contact with the p-type InGaN layer 32, the contact resistance between the Ag reflection film 33 and the p-type InGaN layer 32 is Not so big. The drive voltage of the light emitting device of Invention Example S4 and the drive voltage of the light emitting device of Comparative Example T5 were compared, but the difference was less than 0.05 V, and no significant difference could be recognized.

  In the invention sample S4, the light output of 11.5 mW was obtained when a current of 20 mA was applied, and in the comparative example T5, it was 9.6 mW. In addition, Invention Example A was 8 mW.

  As described above, the light output from the light emitting layer toward the p semiconductor layer side is absorbed by the Ni / Au electrode layer because there is no Ni / Au electrode layer because the large light output is obtained in the present invention example S4. This is because the light is reflected by the Ag layer having a reflectance of 88%. On the other hand, in the comparative example T5, the reflectance of light in the p electrode layer = 70% absorption by Ni / Au × Ag reflectance × 70% reabsorption = 44%. As a result, in Example S4 of the present invention, the light output that could be taken out reached 1.2 times that in Comparative Example T5.

  In this embodiment, an Ag film is used for the p-electrode, but any other material may be used as long as the reflectivity is high and the contact resistance with the p-type InGaN layer 32 is not so high. Can be used.

  In Example 13 of the present invention, Ni / Au layers having low contact resistance with the p-type GaN layer were discretely arranged on the p-electrode, and the Ag film was coated so as to fill the gaps, thereby improving the light output. There is a feature in the point. FIG. 70 is a cross-sectional view focusing on the p-electrode. The Ni / Au electrode layers 12a are discretely arranged at a predetermined pitch on the bottom side of the epitaxial layer. Further, an Ag layer 33 is disposed so as to fill the gap and to cover the down-side bottom surface of the epitaxial layer and the Ni / Au electrode layer 12a. FIG. 71 is a plan view of the p electrode seen through the upper part of the p electrode.

  The typical pitch of the discrete Ni / Au electrode layers 12a is 3 μm. The pitch of 3 μm is based on the fact that in a normal p-type GaN layer or p-type AlGaN clad layer, the diameter in the range in which current spreads from the specific resistance is at most 6 μm. That is, by setting the pitch to 3 μm, a current reaches from one discrete electrode to an adjacent discrete electrode. In order to allow current to flow across the electrode layer, the pitch is preferably 3 μm or less. However, if the pitch is made too small, the effective extraction amount of light is reduced by the discretely arranged Ni / Au electrode layers.

  For example, when the area ratio of the discrete Ni / Au electrode is 20%, according to the structure of the p electrode shown in FIGS. 70 and 71, the light reflectance (calculation) = the reflectance 88% × the area ratio 80% + the reflection The ratio 40% × the area ratio 20% = 78% (calculation) is obtained. Based on this trial calculation, a p-electrode having the above structure was actually produced, and the light output was measured. The test specimens are as follows.

(Invention Sample S5): Prepared according to the same manufacturing process as Invention Example A of Example 1, but in the p-electrode manufacturing process (a6), a 4 nm thick Ni layer was formed in contact with the p-type GaN layer. An Au layer having a thickness of 4 nm was formed on the entire surface. Next, patterning was performed using a resist mask to form discretely distributed Ni / Au electrodes (see FIGS. 70 and 71). Subsequently, the contact resistance was set to 5E-4 Ω · cm ² by heat treatment in an inert gas atmosphere. Thereafter, an Ag layer was formed on the entire surface so as to fill the gap between the Ni / Au electrodes and cover the Ni / Au electrodes, thereby forming a reflective electrode. The occupation ratio of the discretely arranged Ni / Au layers in the p-type GaN layer was 20%, and the occupation ratio of Ag was 80%. The pitch of the Ni / Au electrode layers 12 was 3 μm (see FIG. 72).

  (Comparative Example T6): A laminated structure was formed on a GaN substrate in accordance with the same manufacturing process as Example A of the invention of Example 1. The p electrode was subjected to heat treatment by placing a Ni / Au layer over the entire surface in contact with the p-type GaN layer according to the production step (a6). Next, unlike the configuration of Invention Example A, an Ag layer was formed on the entire surface in contact with the Ni / Au layer (see FIG. 73).

  For comparison, FIG. 74 shows the reflection behavior of light directed to the down side with respect to the same light emitting element as Example A of the present invention.

  (Test and results): A current of 20 mA was applied to each of the light-emitting elements fabricated as described above, and the light output was measured. In the invention sample S5, an optical output of 11.5 mW was obtained, but in the comparative example T6, it was 9.6 mW. Further, the ratio of the light traveling from the active layer toward the mount side (down side) reflected by the p-electrode and emitted from the exit surface reaches 86% in the present invention example (see FIG. 72). On the other hand, it was 67% in Comparative Example T6 (FIG. 73). On the other hand, the ratio in the invention sample A was 40% (FIG. 74).

  In the present invention example S5, the light directed toward the down side is reflected with a reflectance of 88% by Ag occupying 80% of the p electrode, and a Ni / Au layer occupying 20% of the p electrode. Thus, 20% of the light is reflected with a reflectance exceeding 40% (simply not 40% reflectance). As a result, in the invention sample S5, the above ratio is 86%. In the comparative example T6, it is further reflected by the Ag layer located on the down side of the Ni / Au layer, and the ratio is larger than that of the inventive example A due to the reflection.

  Needless to say, the comparative example T6 belongs to the invention example most widely. In order to describe the present embodiment, it is only used as a comparative example for convenience.

  The Ni / Au electrode layer may be replaced with a Pt electrode layer or a Pd electrode layer. The reflective electrode Ag layer may be replaced with a Pt layer or an Rh layer.

  Similarly, when the area ratio of the Ni / Au electrode is 10%, the light output when 20 mA is applied is 11.8 mW, and when the area ratio of the Ni / Au electrode is 40%, the light output when 20 mA is applied is 10.6 mW. A light output larger than that of the comparative example T6 is obtained depending on the area ratio. However, when the area ratio of the Ni / Au electrode is 2%, which is less than 10%, the light output is only 9.6 mW, which is the same as that of the comparative example T6, and there is extremely strong uneven emission around the Ni / Au electrode. Has been confirmed by the inventors' experiments.

  Example 14 of the present invention removes a plurality of parallel plate-like crystal inversion regions propagated from the GaN substrate to the epitaxial layer, and each single crystal region whose plane shape that is a gap region of the plate-like crystal inversion regions is a quadrangle. This is characterized in that a p-electrode is disposed in The GaN substrate is distributed in parallel in the thickness direction of the GaN substrate and appears on the main surface of the GaN substrate in a stripe shape, and the crystal inversion region propagates to the epitaxial layers 2, 3, 4, 5, and 6. 75 and 72 are arranged in a lattice pattern on the main surface. When a nitride semiconductor substrate is manufactured, a region where dislocation bundles (= cores) are collected takes a crystal arrangement that is inverted with respect to the surrounding crystal arrangement. For this reason, the plate-like crystal inversion region and the dislocation bundle are the same in that the periphery and the crystal arrangement are inverted. The difference between the two is that the dislocation bundle collects dislocations in a string-like or thick line, and thus the crystal inversion region is a string, whereas in the plate-like crystal inversion region it is plate-like. is there. That is, in the plate crystal inversion region, dislocations are distributed at a high density in the planar region having a thickness.

  In this example, the crystal inversion region in the epitaxial layer was completely removed, and the crystal inversion region of the GaN substrate was removed up to a predetermined depth on the first main surface side, and the epitaxial layers were separated from each other. It is characterized in that a p-electrode is provided for each epitaxial layer (see FIG. 77). The plate-like crystal inversion region may be formed of a lattice-like crystal inversion region where the plate-like crystal inversion region intersects on the main surface as shown in FIG. 75, or may be constant on the main surface as will be described later. It may be a parallel arrangement distributed in the direction.

  (Invention Sample S6): In the GaN substrate shown in FIGS. 75 and 76, the first main surface on the epitaxial layer side has a (0001) plane, that is, a c-plane. The crystal inversion region having a plane symmetry relationship with the first main surface is the (000-1) plane, that is, the -c plane, and grows with the c-axis reversed. In the c plane, the surface is a Ga plane on which Ga atoms are arranged, and in the crystal inversion region, the surface is an N plane on which N atoms are arranged. In Invention Example S6, a GaN substrate was used in which crystal inversion regions having a width of 30 μm were arranged in a lattice pattern every 100 μm on the first main surface. The crystal inversion region propagates to the epitaxial film formed on the GaN substrate.

  Using the GaN substrate, a laminated structure was formed by the same manufacturing method as that of Invention Example A (see steps (a1) to (a5) of Invention Example A). In the step of forming the p-electrode, the following process is performed instead of (a6). That is, using the mask pattern that covers only the crystal inversion region propagated on the p-type GaN layer as shown in FIG. 76, the p electrode layer was formed only on the c-plane region of the mask gap, and then the mask pattern was removed.

  Next, the semiconductor substrate having the entire second main surface (back surface) of the GaN substrate covered with a mask is held in 8N (regular) 80 ° C. KOH so that the crystal inversion region on the first main surface side is p. A trench 52 was formed by etching and removing the GaN substrate through an epitaxial layer such as a type GaN layer. Since the plate-like crystal inversion region 51 is a dislocation dense portion having a high dislocation density, etching by KOH is easy. The etching depth in the GaN substrate is from the interface between the epitaxial layer and the GaN substrate to a position of 150 μm on the GaN substrate side. Thereafter, the mask was removed, and an insulating film was deposited so as to fill the groove 52 (FIG. 77).

  (Test and test results): When the above-described Invention Example S6 was assembled in a light emitting device and a current of 20 mA was applied, a light output of 9.6 mW could be obtained. This is 1.2 times the optical output 8 mW of Example A of the present invention.

  As described above, in the present invention example S6, the plate-like crystal inversion regions are arranged in a lattice shape, but the plate-like crystal inversion regions do not have to be in a lattice shape, and FIG. 78 (plan view) and FIG. As shown in the figure, it may be a plate-like crystal inversion region arranged only in parallel along a certain direction on the main surface of the GaN substrate. Even when a nitride semiconductor substrate in which dot-like (actually plane or small circular) crystal inversion regions are regularly present is used, the present invention is similar to the present invention example S6 depending on the size and depth of the etching hole. A light output larger than that of Invention Example A can be obtained.

  As shown in FIG. 80, the embodiment 15 of the present invention is characterized in that the fluorescent plate 46 is disposed above the semiconductor chip so as to face the GaN substrate 1 and sealed with the resin 15. There is a novelty in the configuration in which the fluorescent plate is disposed so as to face the GaN substrate that becomes the radiation surface in p-down mounting. The specimens used are examples S7 and S8 of the present invention and comparative example T7 shown in FIG.

  (Invention Sample S7): Invention Sample S7 is basically produced according to the production steps of Invention Example F shown in Example 3. As shown in FIG. 80, a fluorescent plate 46 is arranged on the p-down mounted chip so as to face the back surface of the GaN substrate 1 and sealed with an epoxy resin 15 to obtain a white light emitting device.

  The fluorescent plate 46 was produced by the following manufacturing method. A bulk ZnSSe crystal in which I (iodine) was diffused by a halogen transport method was prepared, and this bulk ZnSSe crystal was heated in a Zn and Cu atmosphere to diffuse Cu into the ZnSSe. Next, this massive ZnSSe crystal was polished to a thickness of 0.5 mm using a rough polishing disk, and then cut into a shape that fits in the lead frame. The roughness of the front and back surfaces of the fluorescent plate produced by the above method was Rmax = 1 μm.

  (Invention Sample S8): In Invention Sample S8, irregularities were formed on the surface 46a of the fluorescent plate 46 facing the GaN substrate (see FIG. 81). The height of the unevenness was 2 μm, and the average pitch of the unevenness was 5 μm. The other structure was the same as that of the present invention example S7.

  (Comparative Example T7): As shown in FIG. 82, the fluorescent plate 46 was disposed above the chip mounted on the p-top so as to face the chip, and sealed with the epoxy resin 15 to obtain a white light emitting device.

  (Test and test results): When a current of 10 A was applied to the light-emitting device assembled from the GaN substrate, the luminance of light emission obtained was as follows. In the present invention example S7, 800 lm was obtained, and in the present invention example S8, 880 lm was obtained. On the other hand, the luminance of Comparative Example T7 was 540 lm. The above results show that the phosphor plate facing the GaN substrate in p-down mounting can secure higher luminance than the phosphor plate disposed in the p-top mounting, and faces the GaN substrate of the phosphor plate. It has been found that the brightness is further improved by roughening the surface.

  In Example 16 of the present invention, for a relatively small LED, the blue light emission intensity and the white luminance of the LED according to the present invention and the LED as a comparative example were measured and compared. The examined specimens are Invention Examples S9 to S11 and Comparative Example T8. This will be described below.

(Invention Sample S9): A structure basically similar to that of Invention Example A is provided. The GaN substrate used has a thickness of 200 μm. The light emitting device formed into a chip has a regular hexagonal shape with a side of 236 μm on the outermost periphery of the chip, a regular hexagonal shape with a light emission surface of 186 μm on one side (light emitting area is 0.09 mm ² ), Takes the shape of a regular hexagon with a side of 186 μm.

  A white LED that emits white light, which is a modified example of the present invention example S9, was prepared using the fluorescent material capable of obtaining 180 lm per 1 watt (W) of 450 nm light output using the present invention example S9. The arrangement of the fluorescent material was the same as that of the LED shown in FIG.

Next, a method for producing the present invention example S9 will be described.
(S9-1) to (S9-11) The same processes as (a1) to (a11) in the production method of Invention Example A were performed. That is, the manufacturing method of Invention Example S9 is basically the same as that of Invention Example A.

  Further, the manufacturing method of the white LED which is a modified example of the present invention example S9 is basically the same as the manufacturing method of the present invention example F.

(Invention Sample S10): A structure basically similar to that of Embodiment 2 of the LED according to the present invention shown in FIGS. That is, the side surface 80 of the light emitting device formed into a chip is inclined with respect to the second main surface 1 a of the GaN substrate 1. As shown in FIG. 22, the p-electrode 12 has a regular hexagonal shape in which the length of one side of the outer periphery is L _P1 = 186 μm. For this reason, the light emitting surface is a regular hexagon having a side length of L _P1 = 186 μm (area is 0.09 mm ² ). Further, the planar shape of the layer (p-type GaN layer 6) closest to the p-electrode 12 in the stacked structure formed on the GaN substrate 1 is also a regular hexagon with one side length L _P0 = 236 μm. The planar shape of the p-type GaN layer 6 and the planar shape of the p-electrode 12 are similar. As shown in FIG. 23, the planar shape of the second main surface of the GaN substrate 1 is also a regular hexagon with one side length of L _N0 = 302 μm. A circular n-electrode 11 having a diameter D = 100 μm is disposed at the substantially central portion of the GaN substrate 1.

  A white LED that emits white light, which is a modified example of the present invention example S10, was produced using the fluorescent material capable of obtaining 180 lm per 1 watt (W) of 450 nm light output using the present invention example S10. The arrangement of the fluorescent material was the same as that of the LED shown in FIG.

Next, a method for producing the present invention example S10 will be described.
(S10-1) to (S10-7) The same processes as the corresponding processes (a1) to (a7) in the invention sample A were performed.
(S10-8) The plate crystal inversion region 51 (see FIGS. 7 and 8) is selectively removed by etching using a KOH solution as an alkaline solution as an etchant. At this time, as shown in FIGS. 25 to 27, the side surface of the chip is also removed by etching at the same time, so that the inclined side surface 80 is formed. Here, an 8N KOH solution was used as the alkaline solution. The temperature of the KOH solution was set to 150 ° C. This KOH solution is placed inside the sealed container 87 of the etching apparatus shown in FIG. FIG. 83 is a schematic diagram showing an etching apparatus used in the LED manufacturing method according to the present invention. In the etching apparatus shown in FIG. 83, a base plate 90 is disposed on the lower surface of the gantry 84, and an airtight container 87 is disposed on the base plate 90. An etchant 88 made of a KOH solution is disposed inside the sealed container 87, and the GaN substrate described above is immersed in the etchant 88. And the airtight container lid | cover 86 is arrange | positioned so that the upper opening part of the airtight container 87 may be plugged up. A presser plate 85 is disposed on the hermetic container lid 86. A presser bolt 89 is attached through a hole formed in the upper portion of the gantry 84 so as to press the presser plate 85 toward the sealed container 87. Then, the GaN substrate is dipped in the KOH solution (etchant 88) under the above conditions, and the etchant 88 is sealed and held for 1.5 hours using the etching apparatus shown in FIG. As a result, the structure as shown in FIGS. In addition, as a material which comprises the airtight container 87 and the airtight container lid | cover 86, Teflon (trademark) etc. can be used, for example.

In addition, the depth H ₁ of the V groove formed by etching shown in FIG. 26 was 150 μm, and the thickness (depth H ₂ ) of the unetched portion was 50 μm. And the chip | tip used for LED shown in FIG. 21 was obtained by implementing the process of cleaving the part which was not etched located in the bottom of V groove | channel, or removing partially by methods, such as an etching. . The obtained chip has a shape as shown in FIGS. Specifically, the p-electrode 12 has a regular hexagonal shape with a length L _P1 = 186 μm on one side of the outer periphery. Further, the planar shape of the layer (p-type GaN layer 6) closest to the p-electrode 12 in the laminated structure formed on the GaN substrate 1 is also a regular hexagon with one side length L _P0 = 236 μm. The planar shape of the p-type GaN layer 6 and the planar shape of the p-electrode 12 are similar. As shown in FIG. 23, the planar shape of the second main surface of the GaN substrate 1 is also a regular hexagon with one side length L _N0 = 302 μm. A circular n-electrode 11 having a diameter D = 100 μm is arranged at substantially the center of the GaN substrate 1.
(S10-9) to (S10-11) The same processes as the corresponding processes (a9) to (a11) in the invention sample A were performed.

  In addition, the white LED manufacturing method, which is a modification of the above-described invention example S10, is basically the same as the manufacturing method of the invention example F in the above-described manufacturing method of the invention example S10 (lead frame mounting). And a step of resin sealing after mounting a fluorescent material on the n-electrode side of the chip mounted on.

(Invention Sample S11): It has a structure basically similar to that of Embodiment 3 of the LED according to the present invention shown in FIG. That is, in the structure of the present invention example S11 described above, the second main surface 1a of the GaN substrate is subjected to non-specular treatment (an uneven portion is formed). In the light emitting device formed into a chip, the side surface 80 is inclined with respect to the second main surface 1 a of the GaN substrate 1. The p-electrode 12 has a regular hexagonal shape in which the length of one side of the outer periphery is L _P1 = 186 μm. For this reason, the light emitting surface is a regular hexagon having a side length of L _P1 = 186 μm (area is 0.09 mm ² ). Further, the planar shape of the layer (p-type GaN layer 6) closest to the p-electrode 12 in the stacked structure formed on the GaN substrate 1 is also a regular hexagon with one side length L _P0 = 236 μm. The planar shape of the second main surface of the GaN substrate 1 is also a regular hexagon with one side length of L _N0 = 302 μm. A circular n-electrode 11 having a diameter D = 100 μm is disposed at the substantially central portion of the GaN substrate 1. Concave and convex portions are formed on the surface of second main surface 1a.

  A white LED that emits white light, which is a modified example of the present invention example S11, was produced using the phosphor material capable of obtaining 180 lm per 1 watt (W) of 450 nm light output using the present invention example S11. The arrangement of the fluorescent material was the same as that of the LED shown in FIG.

Next, a method for producing the present invention example S11 will be described.
(S11-1) to (S11-6) The same processes as the corresponding processes (a1) to (a6) in the invention sample A were performed.
(S11-7) Then, without performing the process (a7) in the present invention example A, that is, without forming a protective mask on the second main surface 1a planting of the GaN substrate, the KOH solution as an alkaline solution is used as an etchant. The plate crystal inversion region 51 (see FIGS. 7 and 8) is selectively removed by the etching used. At this time, as shown in FIG. 29, the side surface of the chip is simultaneously removed by etching, thereby forming an inclined side surface 80. Further, since the protective mask is not formed, the second main surface 1a of the GaN substrate is also partially removed by etching. As a result, an uneven portion is formed on the second main surface 1a. The process conditions (etchant concentration, type, temperature, pressurized state (whether held by a sealed container), etc.) of the etching process are basically the same as those in the above-described processing of the invention example S10 (S10-8). It is. As a result of the etching, a structure as shown in FIG. 29 is obtained. Incidentally, as shown in FIG. 29, the depth H ₁ of the V groove formed by etching is 150 [mu] m, the thickness of the portion that has not been etched (depth H ₂₎ was 50 [mu] m. Then, similarly to the above processing (S10-8), the step of cleaving the unetched portion located at the bottom of the V-groove or partially removing it by a technique such as etching is performed, so that FIG. The chip | tip used for LED shown in was obtained.
(S11-8) to (S11-10) The same processes as the corresponding processes (a9) to (a11) in the invention sample A were performed.

  The white LED manufacturing method, which is a modification of the above-described invention example S11, is basically the same as the manufacturing method of the invention example F in the manufacturing method of the invention example S11 described above (lead frame mounting). And a step of resin sealing after mounting a fluorescent material on the n-electrode side of the chip mounted on.

  Next, Comparative Example T8 will be described.

(Comparative Example T8): Although basically provided with the same structure as that of the present invention A, the planar shape of the chip and the dislocation density in the GaN substrate are different. That is, in Comparative Example T8, the planar shape of the chip is a square having a side of 400 μm, and the dislocation density in the GaN substrate is 1E9 / cm ² . Further, the shape of the light emitting region is 300 μm □ (a square with one side of 300 μm), and the light emitting area is 0.09 mm ² .

  A white LED that emits white light, which is a modified example of the comparative example T8, was prepared using a fluorescent material that can obtain 180 lm per 1 watt (W) of 450 nm light output using the comparative example T8. The arrangement of the fluorescent material was the same as that of the LED shown in FIG.

Next, a manufacturing method of Comparative Example T8 will be described.
(T8-1) An n-type GaN off-substrate shifted by 0.5 ° from the c-plane was used. The specific resistance of this GaN substrate was 0.01 Ω · cm, and the dislocation density was 1E9 / cm ² . The thickness of this GaN substrate was 200 μm.
(T8-2) The following laminated structure was formed on the Ga surface, which is the first main surface of the GaN substrate, by MOCVD. (SiW n-type GaN layer / Si-doped n-type Al _0.2 Ga _0.8 N layer of cladding layer / MQW (Multi-Quantum Well) / two layers of In _0.15 Ga _0.85 N layer stacked on top of each other) (Clad layer Mg-doped p-type Al _0.2 Ga _0.8 N layer / Mg-doped p-type GaN layer)
(T8-3) The emission wavelength was 450 nm, and the internal quantum efficiency calculated for convenience by comparing the PL intensity at a low temperature of 4.2 K and the PL intensity at a room temperature of 298 K was 50%.
(T8-4) This wafer was activated to reduce the resistance of the Mg-doped p-type layer. The carrier concentration by hole measurement was 5E17 / cm ^{3 for} the Mg-doped p-type Al _0.2 Ga _0.8 N layer and 1E18 / cm ³ for the Mg-doped p-type GaN layer.
(T8-5) The wafer is further etched with a Cl-based gas from the Mg-doped p-type layer side to the Si-doped n-type layer by photolithography and RIE (Reactive Ion Etching). By this etching, a lattice-shaped element isolation groove 25 is formed between the square regions to be the individual chips and for dividing the individual chips, and the elements are separated. The width of the element isolation groove is 100 μm.
(T8-6) The N-face of the back surface, which is the second main surface of the GaN substrate, has a circular planar shape at the center of the chip every 400 μm by photolithography, vapor deposition, and lift-off method. (D) A 100 μm n-electrode was attached. As the n-electrode, a stacked structure (Ti layer 20 nm / Al layer 100 nm / Ti layer 20 nm / Au layer 200 nm) was formed in order from the bottom in contact with the GaN substrate. By heating this in a nitrogen (N ₂ ) atmosphere, the contact resistance was set to 1E-5 Ω · cm ² or less.
The (T8-7) p electrode had a square shape in plan view, and a Ni layer with a thickness of 4 nm was formed in contact with the p-type GaN layer, and an Au layer with a thickness of 4 nm was formed on the entire surface. This was heat-treated in an inert gas atmosphere, so that the contact resistance was 5E-4 Ω · cm ² .
(T8-8) Thereafter, scribing was performed so that the chip boundary appeared as a side surface, and the chip was made into a light emitting device. The light-emitting device formed into a chip has a light emission surface of a shape of 300 μm □ (a square having a side length of 300 μm) and a light-emitting layer of a shape of 300 μm □. The planar shape of the outer shape of the chip is a square having a side of 400 μm.
(T8-9) Similarly to the LED shown in FIG. 1, the chip was mounted so that the p-type GaN layer side of the chip was in contact with the mount 21a of the lead frame to form a light emitting device. The light emitting device and the mount are fixed by the conductive adhesive 14 applied to the mount portion, and conduction is obtained.
(T8-10) In order to improve the heat dissipation from the light emitting device, the p-type GaN layer of the light emitting device was mounted so as to be in contact with the entire mount portion. Also, an Ag-based adhesive with good thermal conductivity was selected, and a lead frame of CuW-based adhesive with high thermal conductivity was selected. Thereby, the obtained thermal resistance was 8 ° C./W.
(T8-11) Further, the n electrode and the lead portion of the lead frame were made conductive by wire bonding, and then resin sealing was performed with an epoxy resin to form a lamp.

  Further, the white LED manufacturing method, which is a modification of the above-described comparative example T8, is basically the same as the manufacturing method of the above-described comparative example T8 in the same process as the manufacturing method of the present invention example F (mounted on the lead frame mount). And a step of resin sealing after mounting a fluorescent material on the n-electrode side of the chip.

(Experimental result)
Blue emission intensity was measured for inventive examples S9 to S11 and comparative example T8. Specifically, the present invention examples S9 to S11 and comparative example T8 were mounted in an integrating sphere and then a predetermined current was applied to compare the light output values collected and output from the detector. At this time, a current of 20 mA was applied to each of the specimens of Invention Examples S9 to S11 and Comparative Example T8. As a result, the blue emission intensity (light output of blue light (wavelength 450 nm)) was 8 mW in the comparative example T8, whereas the invention examples S9 to S11 were 8 mW, 9.6 mW, and 11.5 mW, respectively. Met. Moreover, the blue luminescence intensity was also measured when a current of 100 mA was applied to each specimen. As a result, the blue light emission intensity was 30 mW in Comparative Example T8, while Inventive Examples S9 to S11 were 40 mW, 48 mW, and 57.6 mW, respectively.

  Thus, compared with Comparative Example T8, Invention Examples S9 to S11 showed higher emission intensity in both cases where a current of 20 mA was applied or a current of 100 mA was applied. Further, the present invention example S10 in which the side surface of the chip is inclined (tapered) in addition to the configuration of the present invention example S9 shows higher light emission intensity than the present invention example S9. Furthermore, the present invention example S11 in which the second main surface of the GaN substrate is roughened (non-specular treatment) in addition to the configuration of the present invention example S10 shows higher emission intensity than the present invention example S10. ing.

  Further, for the modified examples (white LEDs) of the inventive examples S9 to S11 and the comparative example T8, the white luminance was measured by the same method as the measuring method using the integrating sphere described above. At this time, a current of 20 mA was applied to the test specimens of the modified examples of Invention Examples S9 to S11 and Comparative Example T8. As a result, the white luminance was 1.0 lm in the modified example of the comparative example T8, whereas the modified examples in the inventive examples S9 to S11 were 1.0 lm, 1.2 lm, and 2.1 lm, respectively. It was. Also, white luminance was measured when a current of 100 mA was applied to each specimen. As a result, the white luminance was 5.4 lm in the modified example of the comparative example T8, whereas the modified examples in the present invention examples S9 to S11 were 7.2 lm, 8.6 lm, and 10.4 lm, respectively. It was.

  In Example 17 of the present invention, for a relatively large LED, the blue light emission intensity and the white luminance of the LED according to the present invention and the LED as a comparative example were measured and compared. The examined specimens are Invention Examples S12 to S14 and Comparative Example T9. This will be described below.

(Invention Sample S12): A structure basically similar to that of Invention Sample A is provided, but the chip size is larger than that of Invention Sample S9. The thickness of the GaN substrate used is also 400 μm. That is, the light emitting device formed into a chip has a regular hexagonal shape in which the planar shape of the outermost periphery of the chip is 1.30 mm per side and a regular hexagonal shape whose light emission surface is 1.25 mm per side (light emitting area is 4 mm ² ). Thus, the light emitting layer has a regular hexagonal shape with a side of 1.25 mm. The diameter D of the n electrode is 600 μm.

  As in the case of the present invention example S9, the present invention example S12 also uses a fluorescent material capable of obtaining 180 lm per 1 watt (W) of 450 nm light output, and is a modified example of the present invention example S12. A white LED emitting light was prepared. The arrangement of the fluorescent material was the same as that of the LED shown in FIG.

Next, the manufacturing method of Example S12 of the present invention will be described.
(S12-1) to (S12-11) The same processes as (a1) to (a11) in the production method of Invention Example A were performed. That is, the manufacturing method of Invention Example S12 is basically the same as that of Invention Example A.

  Further, the manufacturing method of the white LED which is a modification of the above-described invention example S12 is basically the same as the manufacturing method of the invention example F.

(Invention Sample S13): The LED has the same structure as that of Embodiment 3 of the LED according to the present invention shown in FIG. That is, in the light emitting device formed into a chip in the structure of the present invention example S12 described above, the side surface 80 is inclined with respect to the second main surface 1a of the GaN substrate 1 and is not in contact with the second main surface 1a of the GaN substrate. Mirror surface treatment is performed (uneven portions are formed). The p-electrode 12 has a regular hexagonal shape in which the length of one side of the outer periphery is L _P1 = 1.25 mm. For this reason, the light emitting surface has a regular hexagonal shape in which the length of one side is L _P1 = 1.25 mm (the area is 4 mm ² ). Further, the planar shape of the layer (p-type GaN layer 6) closest to the p-electrode 12 in the laminated structure formed on the GaN substrate 1 is also a regular hexagon with one side length L _P0 = 1.30 mm. The planar shape of the second main surface of the GaN substrate 1 is also a regular hexagon having a side length of L _N0 = 1.53 mm. A circular n-electrode 11 having a diameter D = 600 μm is disposed at the substantially central portion of the GaN substrate 1. As described above, the uneven portion is formed on the surface of the second main surface 1a.

  A white LED that emits white light, which is a modified example of the invention example S13, was produced using the phosphor material capable of obtaining 180 lm per 1 watt (W) of 450 nm light output using the invention example S13. The arrangement of the fluorescent material was the same as that of the LED shown in FIG.

Next, a method for producing the present invention example S13 will be described.
(S13-1) to (S13-6) The same processes as the corresponding processes (a1) to (a6) in the invention sample A were performed.
(S13-7) Then, without performing the process (a7) in the present invention example A, that is, without forming a protective mask on the second main surface 1a planting of the GaN substrate, the KOH solution as an alkaline solution is used as an etchant. The plate crystal inversion region 51 (see FIGS. 7 and 8) is selectively removed by the etching used. At this time, as shown in FIG. 29, the side surface of the chip is simultaneously removed by etching, thereby forming an inclined side surface 80. Further, since the protective mask is not formed, the second main surface 1a of the GaN substrate is also partially removed by etching. As a result, an uneven portion is formed on the second main surface 1a. The process conditions (etchant concentration, type, temperature, pressurized state (whether held by a sealed container), etc.) of the etching process are basically the same as those in the above-described processing of the invention example S10 (S10-8). It is. However, in the manufacturing process of Invention Example S13, the etching time is 3.5 hours, which is longer than the etching time in the manufacturing method of Invention Example S10. As a result of the etching, a structure as shown in FIG. 29 is obtained. The depth H ₁ of the V groove formed by etching shown in FIG. 29 was 350 μm, and the thickness (depth H ₂ ) of the unetched portion was 50 μm. Then, similarly to the above processing (S10-8), the step of cleaving the unetched portion located at the bottom of the V-groove or partially removing it by a technique such as etching is performed, so that FIG. The chip | tip used for LED shown in was obtained.
(S13-8) to (S13-10) The same processes as the corresponding processes (a9) to (a11) in the invention sample A were performed.

  The white LED manufacturing method, which is a modification of the above-described invention example S13, is basically the same as the manufacturing method of the invention example F in the manufacturing method of the invention example S13 described above (lead frame mounting). And a step of resin sealing after mounting a fluorescent material on the n-electrode side of the chip mounted on.

  (Invention Sample S14): A structure basically similar to that of Embodiment 4 of the LED according to the present invention shown in FIGS. 30 to 32 is provided. That is, a chip group in which nine (3 rows × 3 columns) light emitting devices formed into chips in the structure of the present invention example S13 are assembled is installed on the mount portion 21a of the lead frame as an LED chip. In the unit chip constituting the chip group, the side surface 80 is inclined with respect to the second main surface 1a of the GaN substrate 1, and the second main surface 1a of the GaN substrate is subjected to non-specular treatment (unevenness). Part is formed). A p-electrode 12 is formed on each of the unit chips constituting the chip group. The p-electrode 12 has a regular hexagonal shape with a side length of 415 μm. For this reason, the light emitting surface of each unit chip is a regular hexagon having a side length of 415 μm. Further, the planar shape of the layer (p-type GaN layer 6) closest to the p-electrode 12 in the laminated structure formed on the GaN substrate 1 is also a regular hexagon with one side length of 465 μm. In each unit chip, the planar shape of the second main surface of the GaN substrate 1 is also a regular hexagon. A circular n-electrode 11 having a diameter D = 600 μm is disposed at the substantially central portion of the GaN substrate 1. As described above, the uneven portion is formed on the surface of the second main surface 1a. The distance (pitch) between the centers of the p-electrodes 12 of each unit chip is 835 μm. Further, the depth H1 of the V-shaped groove having the inclined side surface 80 between the unit chips is 200 μm, and the thickness H2 of the remaining unetched portion located at the bottom of the V-shaped groove is 200 μm. .

  A white LED that emits white light, which is a modified example of the present invention example S14, was produced using the fluorescent material capable of obtaining 180 lm per 1 watt (W) of 450 nm light output using the present invention example S14. The arrangement of the fluorescent material was the same as that of the LED shown in FIG.

Next, a method for producing the present invention example S14 will be described.
(S14-1) to (S14-6) The same processes as the corresponding processes (a1) to (a6) in the invention sample A were performed.
(S14-7) Then, without performing the process (a7) in Example A of the present invention, that is, without forming a protective mask on the second main surface 1a of the GaN substrate, the KOH solution as an alkaline solution is used as an etchant. The plate crystal inversion region 51 (see FIGS. 7 and 8) is selectively removed by the etching used. At this time, as shown in FIG. 32, the side surface of the chip is also removed by etching, thereby forming an inclined side surface 80. Further, since the protective mask is not formed, the second main surface 1a of the GaN substrate is also partially removed by etching. As a result, an uneven portion is formed on the second main surface 1a. The process conditions (etchant concentration, type, temperature, pressurized state (whether held by a sealed container), etc.) of the etching process are basically the same as those in the above-described processing of the invention example S10 (S10-8). It is. However, in the manufacturing process of Invention Example S13, the etching time is 2 hours, which is longer than the etching time in the manufacturing method of Invention Example S10. As a result of the etching, the wafer is divided into unit chips by V-shaped grooves (also referred to as V-grooves) as shown in FIG.

As described above, the depth H ₁ of the V-shaped groove formed by etching was 200 μm, and the thickness (depth H ₂ ) of the unetched portion was 200 μm. Then, similarly to the above processing (S10-8), a step of cleaving the unetched portion located at the bottom of the V-shaped groove or partially removing it by a technique such as etching is performed. At this time, as shown in FIG. 30 to FIG. 32, a chip group consisting of nine unit chips of 3 rows × 3 columns is formed as one group so that a chip as a light emitting device is formed by nine unit chips. To divide. As a result, a chip used for the LED shown in FIG. 30 was obtained.
(S14-8) to (S14-10) The same processes as the corresponding processes (a9) to (a11) in the invention sample A were performed.

  The white LED manufacturing method, which is a modification of the above-described invention example S14, is basically the same as the manufacturing method of the invention example F in the manufacturing method of the invention example S14 (lead frame mounting). And a step of resin sealing after mounting a fluorescent material on the n-electrode side of the chip mounted on.

(Comparative Example T9): Basically, it has the same structure as Comparative Example T8, but the chip size is different. That is, in the comparative example T9, the planar shape of the chip is a square with a side of 2.1 mm, the shape of the light emitting region is 2 mm □ (a square with a side of 2 mm), and the light emitting area is 4 mm ² .

  A white LED that emits white light, which is a modified example of the comparative example T9, was prepared using a fluorescent material that can obtain 180 lm per 1 watt (W) of 450 nm light output using the comparative example T9. The arrangement of the fluorescent material was the same as that of the LED shown in FIG.

Next, a manufacturing method of Comparative Example T8 will be described.
(T9-1) to (T9-5) The same processes as the corresponding processes (T8-1) to (T8-5) in Comparative Example T8 were performed.
(T9-6) The N-face of the back surface, which is the second main surface of the GaN substrate, has a circular planar shape at the center of the chip every 2.1 mm by photolithography, vapor deposition, and lift-off method. An n-electrode having a diameter (D) of 600 μm was attached. As the n-electrode, a stacked structure (Ti layer 20 nm / Al layer 100 nm / Ti layer 20 nm / Au layer 200 nm) was formed in order from the bottom in contact with the GaN substrate. By heating this in a nitrogen (N ₂ ) atmosphere, the contact resistance was set to 1E-5 Ω · cm ² or less.
(T9-7) The p electrode has a square shape with a planar shape of 2 mm on a side, a Ni layer having a thickness of 4 nm is formed in contact with the p-type GaN layer, and an Au layer having a thickness of 4 nm is formed on the entire surface. . This was heat-treated in an inert gas atmosphere, so that the contact resistance was 5E-4 Ω · cm ² .
(T9-8) to (T9-11) The same processes as in the corresponding processes (T8-8) to (T8-11) in Comparative Example T8 were performed.

  Further, the white LED manufacturing method, which is a modification of the above-described comparative example T8, is basically the same as the manufacturing method of the above-described comparative example T8 in the same process as the manufacturing method of the present invention example F (mounted on the lead frame mount). And a step of resin sealing after mounting a fluorescent material on the n-electrode side of the chip.

(Experimental result)
For the inventive examples S12 to S14 and comparative example T9, the blue emission intensity was measured in the same manner as in Example 16. Specifically, the present invention examples S12 to S14 and comparative example T9 were mounted in an integrating sphere, and then a predetermined current was applied to compare the light output values collected and output from the detector. At this time, a current of 4.4 A was applied to each of the specimens of Invention Examples S12 to S14 and Comparative Example T9. As a result, the blue light emission intensity (output of light of blue (wavelength 450 nm)) was 1.32 W in Comparative Example T9, whereas the invention examples S12 to S14 were 1.76 W and 2.32 W, respectively. 2.55 W.

  Thus, compared with Comparative Example T9, Invention Examples S12 to S14 showed higher emission intensity when a current of 4.4 A was applied. Further, from Example S12 of the present invention, in addition to the configuration of Example S12 of the present invention, the side surface of the chip was inclined (tapered), and an uneven portion was formed on the second main surface of the GaN substrate ( Invention Example S13 (which has been subjected to non-specular surface treatment) shows a higher emission intensity. Furthermore, the present invention example S14 using a chip group in which nine unit chips are combined shows a higher light emission intensity than the present invention example S13.

  Further, for the modified examples (white LEDs) of the inventive examples S12 to S14 and the comparative example T9, white luminance was measured by the same method as the measuring method using the integrating sphere described above. At this time, a current of 4.4 A was applied to the test specimens of the modified examples of the inventive examples S12 to S14 and the comparative example T9. As a result, the white luminance was 330 lm in the modified example of the comparative example T9, whereas the modified examples in the inventive examples S12 to S14 were 440 lm, 580 m, and 638 lm, respectively.

  The effect of changing the etching process conditions on the wafer splitting process using etching was investigated. Hereinafter, the experiment conducted in the case of this examination is demonstrated.

  Here, an experiment under the four conditions described below was performed using a GaN substrate having a thickness of 400 μm. The step of preparing the GaN substrate is basically the same as the process (a1) in the manufacturing method of the invention example A described above.

(Experiment 1)
An 8N KOH solution was placed in a beaker until the height was 2 cm. And the sample of the GaN substrate mentioned above was immersed horizontally in this KOH solution. The solution temperature was room temperature. Then, the sample was kept for 2 hours while immersed in the KOH solution, and then the sample was taken out from the KOH solution. In the sample taken out, although the plate crystal inversion region 51 (see FIGS. 7 and 8) is selectively etched, the depth of the groove formed by etching is 1 μm with respect to the thickness of the substrate 400 μm. It was. In other words, the substrate could not be divided.

(Experiment 2)
As in Experiment 1, an 8N KOH solution was placed in a beaker until the height was 2 cm. And the sample of the GaN substrate mentioned above was immersed horizontally in this KOH solution. However, in Experiment 2, the temperature of the KOH solution was maintained at 80 ° C. Specifically, the temperature of the KOH solution was maintained at 80 ° C. by heating the beaker containing the KOH solution in which the substrate was immersed with a hot plate. In this state, the GaN substrate was etched. By this etching, the plate-like crystal inversion region 51 of the GaN substrate was selectively etched. The etching rate of the plate crystal inversion region 51 was measured and found to be 20 μm / h. However, since the KOH solution as the etchant was heated as described above, the KOH solution was volatilized during the etching, and the sample was exposed from the KOH solution after 1 hour. Therefore, the beaker was filled with the KOH solution up to a height of 40 cm, and the sample was held for 20 hours under the above-described temperature condition (80 ° C.) while being immersed in the KOH solution. After 20 hours, the amount of the KOH solution was reduced due to volatilization, but the sample (GaN substrate) was completely immersed in the KOH solution. Further, the division of the substrate has been completed (the plate-like crystal inversion region 51 is removed by etching so that the plate-like crystal inversion region 51 penetrates from the first main surface to the second main surface of the GaN substrate. The GaN substrate was divided for each region surrounded by 51).

(Experiment 3)
The 8N KOH solution was placed in a 6 cm high closed container until the height was 2 cm. And the sample of the GaN substrate mentioned above was immersed in this KOH solution in the state where it was placed horizontally. And the said airtight container was sealed. As the sealed container, the sealed container shown in FIG. 83 was used. The temperature of the KOH solution in the sealed container was kept at 80 ° C. Specifically, the temperature of the KOH solution was maintained at 80 ° C. by placing the sealed container containing the KOH solution in which the substrate was immersed in a constant temperature bath maintained at 80 ° C. In this state, the GaN substrate was etched. By this etching, the plate crystal inversion region 51 of the GaN substrate was selectively etched. When the etching rate of the plate crystal inversion region 51 was measured, it was 20 μm / h as in the case of Experiment 2. However, since the etching is performed in a state where the KOH solution is sealed in the sealed container, it is possible to prevent the KOH solution from volatilizing and reducing its capacity when heated.

  And it hold | maintained for 20 hours in the state which immersed the sample in the KOH solution in the said airtight container under the temperature conditions (80 degreeC) mentioned above. After 20 hours had elapsed, the KOH solution was sealed in a sealed container, so that the KOH solution was not volatilized by heating. Therefore, the sample (GaN substrate) was completely immersed in the KOH solution. Moreover, the division of the substrate was completed. As a result, in the case of Experiment 3, the amount of KOH solution necessary to divide one sample by etching was 1/20 of the amount of KOH solution required in Experiment 2.

(Experiment 4)
The sample was etched using basically the same conditions as in Experiment 3 described above. However, in Experiment 4, the temperature of the KOH solution during etching was set to 150 ° C. At this time, the pressure in the sealed container was 5 atm. As a result, the division of the sample GaN substrate was completed in 80 minutes. In Experiment 4, the amount of KOH solution required to divide the GaN substrate sample was 1/20 of the amount of KOH solution required in Experiment 2, as in Experiment 3.

  As described above, the temperature of the etchant used for etching (KOH solution in the above-described experiment) is set higher than room temperature (at least 80 ° C., which is the temperature condition of the above-mentioned experiment 2), or the pressure applied to the etchant is higher than the atmospheric pressure. By increasing the etching rate, the etching rate can be increased. As a result, the etching time required for dividing the substrate can be shortened. That is, by using a high-temperature or high-pressure etchant, the process time required for the substrate dividing step can be shortened, so that the process cost of the LED using the substrate can be reduced.

  The inventor conducted the same experiment even when the temperature of the etchant (KOH solution) held in the closed container exceeded 250 ° C. However, when the temperature of the etchant exceeds 250 ° C. as described above, the pressure in the above-described sealed container becomes about 40 atm, and it is difficult to maintain the hermeticity of the sealed container. For this reason, it is considered that making the temperature of the etchant over 250 ° C. is not practical in the actual LED manufacturing process.

  Next, examples of the present invention will be enumerated and described although there are some overlaps with the above embodiments and examples.

A light emitting device according to the present invention includes a nitride semiconductor substrate (GaN substrate 1) and a nitride semiconductor layer (n-type GaN epitaxial layer 2, n-type Al) laminated on the first main surface of the nitride semiconductor substrate. _x Ga _1-x N layer 3, quantum well 4, p-type Al _x Ga _1-x N layer 5, p-type GaN layer 6) and a first electrode (p-electrode 12) formed on the nitride semiconductor layer. And a second electrode (n electrode 11) formed on the second main surface 1a which is the main surface opposite to the first main surface of the nitride semiconductor substrate, The nitride semiconductor substrate includes a dislocation bundle in which dislocations are concentrated along the thickness direction from the first main surface to the second main surface of the nitride semiconductor substrate (plate-like crystal inversion region 51), a dislocation A single crystal region surrounded by a region where a bundle exists. The specific resistance of the single crystal region is 0.5 Ω · cm or less.

  In this way, dislocations in the nitride semiconductor substrate (GaN substrate 1) are concentrated in the plate-like crystal inversion region 51 where dislocation bundles exist, so that most of the GaN substrate 1 constituting the light emitting device Can be a single crystal region which is a region having a low defect (dislocation) density (low defect region). For this reason, it is possible to improve the light extraction efficiency particularly when a large current is applied.

  In this configuration, since the n electrode 11 is provided on the back surface (second main surface 1a) of the GaN substrate 1 having a low electrical resistance, the current is supplied to the GaN substrate even if the n electrode 11 is provided with a small coverage, that is, a large aperture ratio. It can be swept through the whole 1 and shed. For this reason, the rate of light absorption at the emission surface is reduced, and the light emission efficiency can be increased. Needless to say, light may be emitted not only from the second main surface 1a but also from the side surfaces. The same applies to the following light-emitting devices.

In the light emitting device, the nitride semiconductor substrate is a GaN single crystal substrate (GaN substrate 1), and the nitride semiconductor layer is a GaN-based semiconductor epitaxial thin film layer (n-type GaN epitaxial layer 2, n-type Al _x Ga _1-x N). The layer 3, the quantum well 4, the p-type Al _x Ga _1-x N layer 5 and the p-type GaN layer 6) may be used. In this case, since the GaN substrate 1 is excellent in conductivity, a surge voltage protection circuit (transient voltage applied between the nitride semiconductor substrate and the p-type Al _x Ga _1-x N layer side to be mounted down or It is not necessary to provide a protective circuit for protecting the light emitting device from electrostatic discharge, and the pressure resistance can be very excellent.

In the light emitting device, the nitride semiconductor substrate may be made of either GaN or Al _x Ga _1-x N (0 <x ≦ 1). In this case, if the GaN substrate 1 is used as the nitride semiconductor substrate, a large current density can be applied, so that light with high luminance (and a large luminous flux) can be emitted from the light emitting device. Further, if a nitride semiconductor substrate is composed of GaN or Al _x Ga _1-x N (0 ≦ x ≦ 1), a nitride semiconductor substrate having good thermal conductivity, that is, excellent heat dissipation can be used as a light emitting device. An LED can be constructed. For this reason, even if a large current density is applied, sufficient heat dissipation can be performed, so that the possibility of damage to the LED due to heat can be reduced. Therefore, it is possible to realize a light emitting device that can output light stably for a long time.

In the above light-emitting device, the dislocation density in the single crystal region (the region surrounded by the plate-like crystal inversion region 51 in FIGS. 7 and 8) may be 5E6 / cm ² or less. In this case, since the dislocation density in the single crystal region is sufficiently low, it is possible to reliably improve the light extraction efficiency when a large current is applied to the light emitting device.

  In the light emitting device described above, the region where the dislocation bundle exists (plate-like crystal inversion region 51) on the second main surface 1a of the nitride semiconductor substrate (GaN substrate 1) is a regular as shown in FIG. 78 and FIG. A stripe pattern having a regular interval may be formed. In this case, for example, when the nitride semiconductor substrate (GaN substrate 1) is divided by a region where dislocation bundles exist (plate-like crystal inversion region 51), since the region forms a stripe pattern, conventional methods such as dicing are used. The nitride semiconductor substrate can be easily divided by the machining process.

  In the above light emitting device, as shown in FIG. 7 and FIG. 25, the region where the dislocation bundle exists (plate-like crystal inversion region 51) on the second main surface 1a of the nitride semiconductor substrate (GaN substrate 1) is single. The single crystal region may be surrounded so that the planar shape of the crystal region is a polygonal shape. In this case, the nitride semiconductor substrate (GaN substrate 1) in the nitride semiconductor substrate (GaN substrate 1) is selectively removed by etching or the like in the region where the dislocation bundle exists (plate-like crystal inversion region 51). ) Can be used to form a light emitting device using a portion whose main plane is a polygonal single crystal region. That is, as shown in FIG. 3 and the like, a light-emitting device having a polygonal planar shape on the second main surface 1a of the nitride semiconductor substrate (GaN substrate 1) can be easily realized.

  In the above light emitting device, as shown in FIG. 7 and the like, a polygon (for example, a regular hexagon or a regular triangle) formed by a region where dislocation bundles exist (plate-like crystal inversion region 51) is, when n is a natural number, It may have an internal angle (for example, (120 ° ± 6 °) or (60 ° ± 3 °)) of ((60 ° ± 3 °) × n). In this case, when the planar shape of the nitride semiconductor substrate (GaN substrate 1) is a polygonal shape, the substrate can be efficiently arranged when the nitride semiconductor substrate is installed in a mount portion or the like. For example, when the interior angle is a small value such as 10 °, the planar shape of the nitride semiconductor substrate (GaN substrate 1) is a flat polygon. Therefore, when a circular mount portion or the like is used as the LED, The area of the substrate portion that actually emits light with respect to the size is extremely small. However, if the angle of the interior angle of the polygonal shape is defined as described above, the polygonal shape can be, for example, a regular triangle or a regular hexagon, and thus the area of the substrate portion ( It is possible to suppress the chip area) from becoming extremely small.

  In the light emitting device, the polygon formed by the region where the dislocation bundle exists (plate-like crystal inversion region 51) is an equilateral triangle (see FIG. 9), a rhombus (see FIG. 12), a parallelogram (see FIG. 15), One selected from the group consisting of a trapezoid (see FIG. 18) and a hexagon (see FIG. 3) may be used. In this case, the polygonal shape formed by the region where the dislocation bundle exists (plate-like crystal inversion region 51) in accordance with the use of the light emitting device (that is, the planar shape of the single crystal region surrounded by the region where the dislocation bundle exists). Polygon) can be selected.

  In the light emitting device, the nitride semiconductor substrate (GaN substrate 1) may be divided in a region where dislocation bundles exist (plate-like crystal inversion region 51). Here, the region where the dislocation bundle exists (the plate crystal inversion region 51 which is a crystal defect region) can be easily removed by selective wet etching using an alkaline solution. Therefore, the single crystal region of the nitride semiconductor substrate (GaN substrate 1) can be divided and used so as to become the substrate portion of the light emitting device without using machining or the like. And if the shape of the area | region (plate-like crystal inversion area | region 51) in which a dislocation bundle exists is changed, the planar shape of the light-emitting device obtained as a result can be changed. In addition, since etching can be used for dividing the substrate, the GaN substrate 1 can be divided so as to have a polygonal planar shape that is difficult to be formed by machining such as dicing.

  In the light emitting device, a region (a plate crystal inversion region 51) where dislocation bundles exist may be located at the outer edge of the nitride semiconductor substrate (GaN substrate 1) constituting the light emitting device. In this case, the single crystal region of the nitride semiconductor substrate (GaN substrate 1) can be used as the substrate portion of the light emitting device.

  In the light emitting device, as shown in FIGS. 30 to 32, the nitride semiconductor substrate (GaN substrate 1) is divided in a plurality of regions in the region where the dislocation bundle exists (plate-like crystal inversion region 51). May be. The light emitting device may include a plurality of single crystal regions surrounded by the region (plate crystal inversion region 51) where dislocation bundles exist. In this case, a light emitting device in which the area of the light extraction surface is increased using a plurality of single crystal regions can be easily realized.

  In the light emitting device, as shown in FIG. 3 and the like, the planar shape of the second main surface 1a of the nitride semiconductor substrate (GaN substrate 1) may be a polygonal shape. In this case, when the second main surface 1a of the nitride semiconductor substrate (GaN substrate 1) is a light extraction surface, the shape of the light extraction surface can be a polygonal shape. That is, the planar shape of the light extraction surface can be arbitrarily selected so as to suit the use of the light emitting device.

  In the above light emitting device, as shown in FIG. 3 or FIG. 9, the polygon formed by the second main surface 1a is an angle of ((60 ° ± 3 °) × n) where n is a natural number. (For example, (120 ° ± 6 °) or (60 ° ± 3 °)). In this case, when the planar shape of the second main surface 1a of the nitride semiconductor substrate (GaN substrate 1) is a polygonal shape, the planar shape can be prevented from becoming an extremely flat shape. In other words, if the inner angle of the polygonal shape is defined as described above, the polygonal shape can be, for example, a regular triangle or a regular hexagon, so that the area of the substrate portion with respect to the area of the lead frame mount portion 21a of the LED is reduced. It is possible to suppress the area (chip area) from becoming extremely small.

  In the light emitting device, the polygon formed by the second main surface 1a is an equilateral triangle (see FIG. 9), a rhombus (see FIG. 12), a parallelogram (see FIG. 15), a trapezoid (see FIG. 18), and It may be one selected from the group consisting of hexagons (see FIG. 3). In this case, in accordance with the use of the light emitting device, etc., the planar shape of the single crystal region surrounded by the polygon formed by the second main surface 1a (that is, the region where the dislocation bundle exists (plate-like crystal inversion region 51)). The shape of a certain polygon) can be selected.

  In the above light emitting device, as described in the dividing step (S40) by etching in FIG. 6, the region where the dislocation bundle exists (plate-like crystal inversion region 51) is etched using an etchant of an alkaline solution (KOH solution). By this, the nitride semiconductor substrate may be divided in the region where the dislocation bundle exists (plate-like crystal inversion region 51).

  In this case, since the nitride semiconductor substrate (GaN substrate 1) is divided by wet etching, the planar shape of the single crystal region is a pentagon or more polygon due to the region where the dislocation bundle exists (plate-like crystal inversion region 51). However, the substrate can be easily divided (a polygonal chip can be obtained).

  In the above light emitting device, when the region where the dislocation bundle exists (plate-like crystal inversion region 51) is etched, the temperature of the etchant of the alkaline solution may be set to 80 ° C. or higher. In this case, since the etching rate of wet etching can be sufficiently increased, the time required for the manufacturing process of the light emitting device (division step (S40) by etching shown in FIG. 6) can be shortened. As a result, the manufacturing cost of the light emitting device can be reduced.

  In the above light emitting device, when the region where the dislocation bundle exists (plate-like crystal inversion region 51) is etched, the temperature of the etchant of the alkaline solution may be set to 250 ° C. or lower. The etching is preferably performed in a sealed state where the etchant is held in a sealed container.

  In this case, if the temperature of the etchant is set to exceed 250 ° C., the etchant temperature becomes too high in the dividing step by etching, and the etchant volatilizes, so that the etching cannot be performed stably. Therefore, if the temperature of the etchant is set to 250 ° C. or less, the above-described problem can be suppressed to an allowable level in an actual light emitting device manufacturing process.

  In the light emitting device, the end surface (side surface 80) of the nitride semiconductor substrate (GaN substrate 1) may be inclined with respect to the first main surface (or second main surface 1a). In this case, since effective light can be extracted also from the inclined end surface (side surface 80) of the Gan substrate 1, the efficiency of extracting light from the light emitting device can be improved.

  In the above light emitting device, as shown in FIGS. 28 and 32, the second main surface 1a of the nitride semiconductor substrate (GaN substrate 1) may be subjected to non-specular treatment. In this case, on the second main surface 1a, that is, the light extraction surface (emission surface), the light generated in the light emitting layer in the nitride semiconductor layer is prevented from being confined in the substrate by total reflection and the efficiency is lowered. be able to. Needless to say, the side surfaces of the substrate and the nitride semiconductor layer may be subjected to non-specular treatment.

  In the method for manufacturing the light emitting device, the nitride semiconductor substrate is immersed in an etchant of an alkaline solution (step (S41) in FIG. 24), and the etchant in which the nitride semiconductor substrate is immersed is sealed in the nitrided state. A dividing step of dividing the nitride semiconductor substrate by etching the nitride semiconductor substrate (separating step (S42 in FIG. 24)). In this way, in the manufacturing process of the light emitting device according to the present invention, the GaN substrate 1 can be divided by etching. For this reason, even if the planar shape of the single crystal region surrounded by the region where the dislocation bundle exists (plate-like crystal inversion region 51) is a shape other than a square such as a regular triangle or a regular hexagon, the GaN substrate 1 can be easily formed. Division can be performed.

  In the method for manufacturing a light emitting device, the temperature of an etchant such as a KOH solution in the dividing step (separating step (S42 in FIG. 24)) may be set to 80 ° C. or higher and 250 ° C. or lower. In this way, the etching rate in the substrate separation step (S42) by etching can be increased to some extent, and the probability of occurrence of a problem that stable etching cannot be performed because the temperature of the etchant becomes too high can be reduced. For this reason, etching control can be stably performed while shortening the time required for the separation step (S42) in the manufacturing process of the light emitting device as much as possible.

  In the method for manufacturing a light emitting device, in the dividing step (separating step (S42)), the end surface (side surface 80) of the nitride semiconductor substrate (GaN substrate 1) is the first main surface (or second main surface 1a). The GaN substrate 1 may be etched so as to be inclined. Further, as described in the third embodiment of the present invention, in the separation step (S42), the second main surface 1a of the nitride semiconductor substrate (GaN substrate 1) is formed by the second electrode (n electrode 11). Non-specular treatment may be performed by etching the uncovered region. In this case, since the non-specular surface treatment and the end surface (side surface 80) can be inclined (tapered) simultaneously in the separation step (S42), the manufacturing process of the light emitting device can be simplified. As a result, the manufacturing cost of the light emitting device can be reduced.

Another light-emitting device according to the present invention includes a nitride semiconductor substrate (GaN substrate 1) and an n-type nitride semiconductor layer (n-type Al _x Ga ₁₋ ) on the first main surface side of the nitride semiconductor substrate. _x N layer 3), a p-type nitride semiconductor layer (p-type Al _x Ga _1-x N layer 5) located far from the n-type nitride semiconductor layer when viewed from the nitride semiconductor substrate, and an n-type nitride The light emitting device includes a light emitting layer (MQW: Multi-Quantum Well (MQW) 4) located between the semiconductor layer and the p-type nitride semiconductor layer. In this light emitting device, the specific resistance of the nitride semiconductor substrate is 0.5 Ω · cm or less, the p-type nitride semiconductor layer side is down-mounted, and the main surface opposite to the first main surface of the nitride semiconductor substrate is mounted. Light is emitted from the second main surface 1a which is the surface. The nitride semiconductor substrate has a dislocation bundle in which dislocations are concentrated along the thickness direction from the first main surface to the second main surface 1a of the nitride semiconductor substrate (plate-like crystal inversion region 51), And a single crystal region surrounded by a region where dislocation bundles exist.

  In this way, if the nitride semiconductor substrate is etched under conditions for selectively etching the region where the dislocation bundle exists (plate-like crystal inversion region 51), the substrate is divided in the region where the dislocation bundle exists. Can do. Since dislocations in the nitride semiconductor substrate are concentrated in a region where the dislocation bundle exists (plate-like crystal inversion region 51), most of the nitride semiconductor substrate constituting the light emitting device is a region having a low defect (dislocation) density. A single crystal region which is a (low defect region) can be obtained. For this reason, it is possible to improve the light extraction efficiency particularly when a large current is applied. Further, in this configuration, since the n-type electrode is provided on the back surface (second main surface) of the nitride semiconductor substrate having a low electric resistance, the current is supplied even if the n-electrode is provided with a small coverage, that is, a large aperture ratio. It can be made to flow over the entire substrate. For this reason, the rate of light absorption at the emission surface is reduced, and the light emission efficiency can be increased. Needless to say, light may be emitted not only from the second main surface but also from the side surface.

  In addition, since the p-type nitride semiconductor layer having a high electrical resistance does not serve as a light emitting surface, a p-type electrode layer can be formed on the entire surface of the p-type nitride semiconductor layer, and a large current is passed to suppress heat generation. However, it is also possible to adopt a structure that is convenient for releasing generated heat by conduction. That is, the constraints imposed by thermal requirements are greatly relaxed. For this reason, in order to reduce electrical resistance, it is not necessary to make it the comb-shaped shape etc. which interposed the p electrode and the n electrode.

  Furthermore, since the GaN substrate is excellent in conductivity, it is not particularly necessary to provide a protection circuit against a surge voltage, and the pressure resistance can be very excellent. In addition, since complicated processing steps are not performed, it is also easy to reduce manufacturing costs.

Another light-emitting device according to the present invention also includes a GaN substrate 1 of a nitride semiconductor substrate and an n-type Al _x Ga _1-x of an n-type nitride semiconductor layer on the first main surface side of the GaN substrate. N layer 3 (0 ≦ x ≦ 1) and p-type Al _x Ga _1-x N layer 5 (0 ≦ x ≦ 1) located farther from the n-type Al _x Ga _1-x N layer 3 when viewed from the GaN substrate ) And a light emitting layer (quantum well (MQW: Multi-Quantum Well) 4) located between the n-type Al _x Ga _{1 -x} N layer 3 and the p-type Al _x Ga _{1 -x} N layer 5 A light emitting device. In this light-emitting device, the dislocation density of the GaN substrate 1 is 5 × 10 ⁸ / cm ² or less, the p-type Al _x Ga _1-x N layer 5 side is down-mounted, Light is emitted from the second main surface 1a which is the main surface opposite to the surface. The GaN substrate 1 includes a dislocation bundle in which dislocation bundles in which dislocations are concentrated along the thickness direction from the first main surface to the second main surface 1a of the GaN substrate 1 (plate-like crystal inversion region 51), and a dislocation bundle. And a single crystal region surrounded by a region in which is present.

According to this configuration, the GaN substrate 1 in the present invention is premised on having conductivity, and it is easy to reduce the electrical resistance. Therefore, in addition to the operational effects in the light emitting device, the dislocation density of the GaN substrate is Since it is 5 × 10 ⁸ / cm ² or less, the light output from the second main surface can be increased due to the high crystallinity and the high aperture ratio. Light is also emitted from the side surface. Further, since the continuity of the refractive index is maintained, the above-described problem of total reflection does not occur.

Still another light emitting device according to the present invention includes a conductive AlN substrate as a nitride semiconductor substrate, and an n-type Al _x Ga ₁ n-type nitride semiconductor layer on the first main surface side of the AlN substrate. _-x N layer 3 (0 ≦ x ≦ 1) and a p-type Al _x Ga _1-x N layer 5 (0 ≦ _x) located farther from the n-type Al _x Ga _1-x N layer 3 when viewed from the AlN substrate. x ≦ 1) and a light emitting device (quantum well 4) positioned between the n-type Al _x Ga _1-x N layer 3 and the p-type Al _x Ga _1-x N layer 5. Then, the thermal conductivity of the AlN substrate is 100 W / (m · K) or more, the p-type Al _x Ga _1-x N layer 5 side is down-mounted, and the first main surface of the AlN substrate is Light is emitted from the second main surface 1a which is the opposite main surface. The AlN substrate has a single crystal region surrounded by a region where dislocation bundles in which dislocations are concentrated along the thickness direction from the first main surface to the second main surface of the AlN substrate and a region where dislocation bundles exist Including.

Since AlN has very high thermal conductivity and excellent heat dissipation, heat is transferred from the p-type Al _x Ga _1-x N layer 5 to the lead frame or the like to suppress temperature rise in the light emitting device. be able to. Also, heat can be dissipated from the AlN substrate to contribute to the suppression of temperature rise. The above AlN substrate is premised on a conductive AlN substrate into which impurities are introduced in order to provide conductivity.

The GaN substrate is n-type by oxygen doping, the oxygen concentration is in the range of 1E17 oxygen atoms / cm ^{3 to} 2E19 atoms / cm ³ , and the thickness of the GaN substrate can be 100 μm to 600 μm. .

By setting the oxygen concentration to 1E17 / cm ³ or more as described above, the specific resistance of the GaN substrate can be improved, the current introduced from the p-electrode can be sufficiently spread to the GaN substrate, and the active layer can be widened. This can be used to generate light emission. In addition, by setting the oxygen concentration to 2E19 / cm ³ or less, it is possible to secure a transmittance of 60% or more for light having a wavelength of 450 nm, and to enhance the transmittance of the GaN substrate serving as a radiation surface to ensure light output. can do. The above oxygen concentration range works particularly effectively when the thickness of the GaN substrate is 100 μm to 600 μm in a p-down mounted structure.

The oxygen concentration is in the range of 5E18 oxygen atoms / cm ^{3 to} 2E19 atoms / cm ³ , the thickness of the GaN substrate is in the range of 200 μm to 400 μm, and the second main surface emits light. Both sides of the shape surface can be in the range of 10 mm or less.

  With this configuration, light can be emitted over the entire light emitting surface, and sufficient light output can be obtained.

Furthermore, the oxygen concentration is in the range of 3E18 oxygen atoms / cm ^{3 to} 5E18 / cm ³ , the thickness of the GaN substrate is in the range of 400 μm to 600 μm, and the second main surface emits light. Both sides of the surface may be in a range of 3 mm or less. The oxygen concentration is in the range of 5E18 oxygen atoms / cm ^{3 to} 5E19 atoms / cm ³ , the thickness of the GaN substrate is in the range of 100 μm to 200 μm, and the second main surface emits light in a rectangular shape. Both sides of the surface can be in the range of 3 mm or less.

  By making the oxygen concentration and the chip size appropriate according to the thickness of the GaN substrate as described above, a more appropriate GaN substrate can be set in terms of performance (uniform light emission and light emission efficiency) according to the chip size. . In addition, the most desirable conditions can be set in terms of manufacturing cost.

Further, between the GaN substrate and the n-type Al _x Ga _1-x N layer (0 ≦ x ≦ 1), the n-type AlGaN buffer layer is in contact with the GaN substrate, and the n-type AlGaN buffer layer is also in contact with the GaN substrate. The n-type GaN buffer layer may be positioned, and the n-type Al _x Ga _1-x N layer (0 ≦ x ≦ 1) may be positioned in contact with the n-type GaN buffer layer.

In the case of the heteroepitaxial laminated structure as described above, the n-type AlGaN is interposed between the GaN substrate and the n-type Al _x Ga _1-x N layer (0 ≦ x ≦ 1) which is the cladding layer of the active layer as described above. A buffer layer and an n-type GaN buffer layer may be disposed.

  By adding not only the n-type GaN buffer layer but also the n-type AlGaN buffer layer between the GaN substrate and the clad layer as described above, a heteroepitaxial laminated structure with good crystallinity can be formed.

  In particular, the above laminated structure is preferably used when the GaN substrate has an off-angle region of 0.10 ° or less and a region of 1.0 ° or more.

  With this configuration, even when the GaN substrate is warped and the off angle fluctuates as described above, a heteroepitaxial laminated layer with excellent crystallinity can be obtained by arranging an n-type AlGaN buffer layer in addition to the n-type GaN layer. A structure can be obtained.

  Dislocation bundles may be distributed in the single crystal region of the GaN substrate, and in this case, the dislocation bundle is located on the n-type GaN buffer layer located in contact with the n-type AlGaN buffer layer and the n-type AlGaN buffer layer. The epitaxial layer may be configured such that dislocation bundles are not propagated.

  With this configuration, the manufacturing yield can be greatly increased. That is, by disposing the n-type AlGaN buffer layer and the n-type GaN buffer layer as described above, the dislocation bundle in the epitaxial multilayer structure including the light emitting layer can be substantially eliminated. That is, the n-type AlGaN buffer layer and the n-type AlGaN buffer layer can terminate the dislocation bundle in the vicinity of the GaN substrate or the layer immediately above it.

A p-type GaN buffer layer located on the down side in contact with the p-type Al _x Ga _1-x N layer (0 ≦ x ≦ 1), and a p-type InGaN contact layer located in contact with the p-type GaN buffer layer And may be provided.

  With the above configuration, a p-type InGaN contact layer having excellent electrical conductivity can be disposed on the lower layer on which the p-electrode layer is placed, and the material is selected with the work function as the most important p-electrode layer. The need is reduced. For this reason, for example, the material of the p-electrode can be selected with the highest importance on the reflectance.

The Mg concentration of the p-type InGaN contact layer can be in the range of 1E18 to 1E21 Mg atoms / cm ³ .

  With the above configuration, sufficient electrical conductivity can be secured, and the current introduced to the p-electrode can be spread over the entire epitaxial film.

  The p-type InGaN contact layer may be in contact with the p-type electrode layer composed of any one of the Ag, Al, and Rh layers.

  With the above configuration, the light output can be increased by increasing the reflectivity from the mounting portion, that is, the bottom of the light emitting element to reduce the loss of light.

  The GaN substrate has a plate-like crystal inversion region continuously extending over the thickness direction and in the plane of the GaN substrate, and the plate-like crystal inversion region in the GaN substrate and n formed on the GaN substrate. After the plate-like crystal inversion region propagating to the p-type nitride semiconductor layer and the p-type nitride semiconductor layer is removed from the p-type nitride semiconductor layer side to the position in the GaN substrate through the n-type nitride semiconductor layer. A p-electrode may be provided for each p-type nitride semiconductor layer in contact with the remaining p-type nitride semiconductor layer.

  According to this configuration, since the light extraction surface can be increased, the light output can be improved.

  In the above, the plate crystal inversion region may be removed to the position in the GaN substrate with a KOH aqueous solution.

  When the plate-like crystal inversion region is removed with an aqueous KOH solution, there is an advantage that a photomask is not necessary and that the second main surface of the nitride semiconductor substrate can be processed simultaneously with the non-mirror processing. For this reason, manufacturing cost can be reduced in said structure by using KOH aqueous solution.

  The p-type nitride semiconductor is filled with a gap between the first p-electrode, which is in contact with the p-type nitride semiconductor layer and is discretely arranged over the surface of the p-type nitride semiconductor layer, and the first p-electrode. You may provide the 2nd p electrode which consists of either Ag, Al, and Rh which coat | covers a physical semiconductor layer and a 1st p electrode.

  With this configuration, the current introduced into the p-electrode can be sufficiently spread over the surface, and the reflectance can be increased to improve the light output.

  The coverage of the surface of the p-type nitride semiconductor layer of the first p electrode that is discretely arranged may be in the range of 10 to 40%.

  With this configuration, it is possible to spread the current introduced over the surface while ensuring electrical conductivity. If the coverage is less than 10%, current cannot flow through the epitaxial layer without falling. On the other hand, if it exceeds 40%, the adverse effect on the light extraction efficiency by the p electrode layers arranged discretely cannot be ignored.

  The fluorescent plate may be arranged so as to face the second main surface of the nitride semiconductor substrate away from the nitride semiconductor substrate.

  By arranging the fluorescent plate directly on the nitride semiconductor substrate constituting the light emitting portion mounted on the p-down, the light reflected and returned from the back surface of the fluorescent plate is re-reflected on the nitride semiconductor surface and directed toward the fluorescent plate. Can be. As a result, the light output can be improved.

  The surface facing the second main surface of the nitride semiconductor substrate of the fluorescent plate can be processed to be roughened.

  With the above configuration, the light extraction efficiency can be further increased.

  The light emitting device may have an electrostatic withstand voltage of 3000 V or more.

  The nitride semiconductor substrate described above may function as a grounding member that releases its power to the ground against a transient voltage or electrostatic discharge.

A nitride semiconductor substrate having a high electrical conductivity has a light emitting element against a transient voltage or electrostatic discharge applied between the nitride semiconductor substrate and the p-type Al _x Ga _1-x N layer side mounted down. In order to protect against high voltages, it can function as a grounding member that releases these high voltages to ground. For this reason, in order to cope with the above transient voltage or electrostatic discharge, it is not necessary to provide a protection circuit such as a power shunt circuit including a Zener diode. Transient voltage and electrostatic discharge are major causes of circuit failure for group III nitride semiconductors. If the electrical conductivity of the nitride semiconductor substrate is high as described above, it can be used as a grounding member, greatly increasing the manufacturing process. And the manufacturing cost can be reduced.

  The light emitting element can emit light by applying a voltage of 4 V or less. By using a nitride semiconductor substrate having high electrical conductivity, that is, low electrical resistance, a current sufficient for light emission can be injected into the light emitting layer by applying a low voltage, and light can be emitted. For this reason, since it is sufficient to mount a smaller number of batteries, it is possible to contribute to size reduction, weight reduction, and cost reduction of a lighting device incorporating a light emitting element. It is also effective in reducing power consumption.

  The nitride semiconductor substrate may have a thickness of 50 μm or more.

  With this configuration, when electrons are allowed to flow from a point-like or small-area n-electrode, the electrons spread from the surface of the GaN substrate or n-type nitride semiconductor substrate toward the inside. For this reason, it is desirable that the GaN substrate or the n-type nitride semiconductor is thick. When the thickness of the substrate is less than 50 μm, when the area of the n-electrode is reduced, it does not spread sufficiently when it reaches the active layer of the quantum well structure, and a portion that does not emit light or a portion that does not emit light is generated in the active layer. By making the thickness of the substrate 50 μm or more, even if the area of the n-electrode is reduced due to low electrical resistance, the current can be sufficiently expanded in the substrate, and the light emitting portion in the active layer can be sufficiently expanded. Can do. More preferably, it is 75 μm or more. However, if it is too thick, absorption by the substrate cannot be ignored, so it is desirable that the thickness be 500 μm or less.

  An electrode may be provided on the second main surface of the nitride semiconductor substrate with an aperture ratio of 50% or more.

  With this configuration, the light emission efficiency from the second main surface can be increased. As the recovery efficiency increases, the amount of light absorbed by the n-electrode decreases, so that the light output can be increased. For this reason, the aperture ratio is more desirably 75% or more, and further desirably 90% or more.

The contact area between the electrode provided on the nitride semiconductor substrate and the nitride semiconductor substrate can be 0.055 mm ² or more.

  With this configuration, for example, a linear current-light output characteristic can be obtained up to about 70 A with an 8 mm square semiconductor chip without the influence of electrode heat generation.

Further, the cross-sectional area of the bonding wire that electrically connects the electrode and the lead frame may be 0.002 mm ² or more.

  With this configuration, it is possible to operate up to the current 2A without being affected by the heat generation of the wire portion.

The cross-sectional area of the bonding wire that electrically connects the electrode and the lead frame can be set to 0.07 mm ² or more.

  With this configuration, it is possible to operate up to a current of about 70 A without being affected by the heat generation of the wire portion.

The electrode is divided into two or more corners of the nitride semiconductor substrate, the total contact area between the electrode and the nitride semiconductor substrate is 0.055 mm ² or more, and the lead frame and the electrode located at the corner are electrically connected. The total cross-sectional area of the bonding wires to be connected can be 0.002 mm ² or more.

  With this configuration, it is possible to prevent a portion that becomes an obstacle to light in the light extraction of the semiconductor chip from being arranged.

The total cross-sectional area of the bonding wire that electrically connects the electrode located at the corner and the lead frame can be 0.07 mm ² or more.

  With this configuration, it is possible to increase the light output efficiency while eliminating almost all the obstacles to light extraction.

The area of the second main surface that emits light may be 0.25 mm ² or more.

With this configuration, by arranging a predetermined number of the light-emitting elements, a range that can be replaced with an existing lighting device is increased. When the area of the portion that emits light is less than 0.25 mm ² , the number of light-emitting elements to be used becomes too large to replace the existing lighting fixture. In the above-described embodiment of the present invention, the part that emits light. In the nitride compound semiconductor substrate, it is better that the current is large enough to spread. This means that the smaller the electrical resistance, the wider the light emission area. For example, if the specific resistance of the nitride compound semiconductor substrate is 0.01 Ω · cm, it is about 8 mm × 8 mm as in Example F of the present invention. be able to.

  The portion of the nitride semiconductor substrate that emits light on the second main surface may have a size of 1 mm × 1 mm or more. The portion of the nitride semiconductor substrate that emits light on the second main surface may have a size of 3 mm × 3 mm or more. Furthermore, the light emitting portion of the second main surface of the nitride semiconductor substrate may have a size of 5 mm × 5 mm or more.

  As described above, by increasing the area of the light emission surface, it is possible to reduce the number of light-emitting elements mounted on the lighting device, thereby realizing reduction in processing steps, reduction in the number of parts, reduction in power consumption, and the like. be able to. As a precaution, the size of 1 mm × 1 mm or more means a size including 1 mm × 1 mm.

  Including the light emitting element formed on the AlN substrate, the above light emitting element may be configured so that the thermal resistance is 30 ° C./W or less.

  The luminous efficiency of the light emitting element is lowered due to the temperature rise, and the light emitting element is damaged when the temperature rises excessively. For this reason, temperature or thermal resistance is an important design factor in a light emitting device. Conventionally, the thermal resistance has been approximately 60 ° C./W (Patent Document 1). However, as described above, by setting the thermal resistance to be 30 ° C./W or less, even if the input power to the light emitting element is sufficiently applied, the luminous efficiency is remarkably lowered or the light emitting element is damaged. No longer occurs. The above-described halving of the thermal resistance was realized for the first time by using a GnN substrate having a small specific resistance as described above.

  In the above light emitting element, the temperature of the portion where the temperature rises most in the continuous light emission state can be set to 150 ° C. or less.

  With this configuration, the portion where the temperature rises most, that is, the temperature of the light emitting layer can be set to 150 ° C. or less, and sufficiently high light emission efficiency can be ensured. Furthermore, it is possible to obtain a significant increase in lifetime as compared with conventional light emitting devices.

  The thickness of the n-type nitride semiconductor layer is preferably 3 μm or less.

  The n-type nitride semiconductor layer is epitaxially grown on the nitride semiconductor substrate. If the n-type nitride semiconductor layer is unnecessarily thick, the film forming process takes a long time and the raw material cost increases. As described above, when the thickness of the n-type nitride semiconductor layer is 3 μm or less, a large cost reduction can be obtained. More desirably, the thickness is 2 μm or less.

  On the second main surface of the nitride semiconductor substrate, a non-mirror surface treatment may be applied to a portion not covered with the electrode.

  With this configuration, it is possible to prevent the light generated in the light emitting layer from being confined in the substrate due to total reflection on the second main surface, that is, the emission surface, and the efficiency is lowered. Needless to say, the side surface of the laminated structure may be subjected to non-specular treatment.

The surface that has been subjected to the above non-mirror surface treatment is a surface that has been made non-specular using a potassium hydroxide (KOH) aqueous solution, a sodium hydroxide (NaOH) aqueous solution, an ammonia (NH ₃ ) aqueous solution or another alkaline aqueous solution. May be.

  By the non-specularization treatment, it is possible to efficiently obtain a surface with large irregularities only on the N surface of the GaN substrate. The Ga surface side is not etched.

In addition, the surface subjected to the non-mirror surface treatment is a sulfuric acid (H ₂ SO ₄ ) aqueous solution, hydrochloric acid (HCl) aqueous solution, phosphoric acid (H ₂ PO ₄ ) aqueous solution, hydrofluoric acid (HF) aqueous solution or other acid aqueous solution. It may be a non-specularized surface using at least one.

  In addition, the surface that has been subjected to the non-specular treatment may be a surface that has been made non-specular using reactive ion etching (RIE). Thereby, the non-mirror surface excellent in the dimensional accuracy of the area can be obtained by a dry process. Furthermore, a predetermined unevenness interval can be obtained by combining RIE with dry etching and wet etching with an alkaline aqueous solution in combination with a photolithography technique.

  The electrode provided in the p-type nitride semiconductor layer can be formed of a material having a reflectance of 0.5 or more.

  With this configuration, absorption of light on the mounting surface side can be prevented, and the amount of light reflected toward the second main surface of the substrate can be increased. The reflectance is preferably higher, and is preferably 0.7 or more.

  A phosphor may be arranged so as to cover the second main surface of the nitride semiconductor substrate. In the light emitting device, the fluorescent plate may be disposed so as to face the second main surface of the nitride semiconductor substrate away from the nitride semiconductor substrate. Furthermore, the surface facing the second main surface of the nitride semiconductor substrate of the fluorescent plate may be subjected to an uneven process. Further, the nitride semiconductor substrate may include at least one of impurities that emit fluorescence and defects.

  With the above configuration, both white LEDs can be formed.

  The light-emitting element of the present invention may include two or more of any of the light-emitting elements listed above, and these light-emitting elements may be connected in series.

  With the above configuration, it is possible to obtain a lighting component in which a plurality of the high-efficiency light-emitting elements described above are mounted on a lead frame or the like using a high-voltage power supply. For example, since an automobile battery is about 12V, it can emit light by connecting four or more light emitting elements of the present invention in series.

  Another light-emitting element of the present invention may include two or more of the above-described light-emitting elements, and the light-emitting elements may be connected in parallel.

  With the above configuration, it is possible to obtain a lighting component including the above-described high-efficiency light-emitting element using a high-current power supply.

  Further including another light emitting element of the present invention and a power supply circuit for causing the light emitting elements to emit light, and in the power supply circuit, two or more parallel portions in which two or more light emitting elements are connected in parallel are connected in series. A configuration may be adopted.

  With this configuration, it is possible to match the illumination component capacity and the power supply capacity while satisfying the light emission conditions of the individual light emitting elements. Note that, in the above power supply circuit, when the capacity of the lighting device is variable, a parallel switching unit may be provided, and the wiring applied to the light emitting element may be switched by the parallel switching unit.

  Although the embodiments and examples of the present invention have been described above, the embodiments and examples of the present invention disclosed above are merely examples, and the scope of the present invention is the implementation of these inventions. It is not limited to the form. The scope of the present invention is indicated by the description of the scope of claims, and further includes meanings equivalent to the description of the scope of claims and all modifications within the scope.

  The light-emitting element of the present invention uses a highly conductive nitride semiconductor substrate, uses etching that selectively removes a portion where dislocation bundles exist in the chip division in the nitride semiconductor substrate, and is further p-down mounted. As a result of using the structure, (1) excellent heat dissipation, no need to provide a complicated electrode structure, enabling high output light emission, (2) excellent electrical conductivity, light emitting element from transient voltage and electrostatic discharge There is no need to provide a protective circuit for protection, and it excels in large area light emission and electrostatic withstand voltage. Total reflection is unlikely to occur between the surfaces, and therefore there is no reduction in efficiency or resin degradation due to total reflection, and (4) light is emitted at a low voltage, so a large-capacity power supply is not required. Suitable for lighting equipment And, for (5) it is simple its structure, is inexpensive easy to manufacture, is excellent in maintainability. For this reason, it is expected that it will be widely used in various lighting products including automotive lighting devices in the future.

It is a figure which shows Embodiment 1 of LED by this invention. It is a figure which shows the laminated structure containing the light emitting layer of LED of FIG. It is a top view of LED of FIG. It is the top view which looked at the chip | tip which comprises LED shown in FIG. 1 from the side in which the p electrode was formed. It is the top view which looked at the chip | tip which comprises LED shown in FIG. 1 from the side in which the n electrode was formed. It is a flowchart for demonstrating the manufacturing method of LED shown in FIGS. FIG. 6 is a schematic plan view showing a state of the wafer when the LED chip shown in FIGS. 1 to 5 is taken from the wafer. It is a cross-sectional schematic diagram in line segment VIII-VIII of FIG. FIG. 6 is a plan view showing a first modification of the first embodiment of the LED according to the present invention shown in FIGS. 1 to 5. It is the top view which looked at the chip | tip which comprises LED shown in FIG. 9 from the side in which the p electrode was formed. It is the top view which looked at the chip | tip which comprises LED shown in FIG. 9 from the side in which the n electrode was formed. FIG. 6 is a plan view showing a second modification of the first embodiment of the LED according to the present invention shown in FIGS. 1 to 5. It is the top view which looked at the chip | tip which comprises LED shown in FIG. 12 from the side in which the p electrode was formed. It is the top view which looked at the chip | tip which comprises LED shown in FIG. 12 from the side in which the n electrode was formed. FIG. 6 is a plan view showing a third modification of the first embodiment of the LED according to the present invention shown in FIGS. It is the top view which looked at the chip | tip which comprises LED shown in FIG. 15 from the side in which the p electrode was formed. It is the top view which looked at the chip | tip which comprises LED shown in FIG. 15 from the side in which the n electrode was formed. FIG. 6 is a plan view showing a fourth modification of the first embodiment of the LED according to the present invention shown in FIGS. 1 to 5. It is the top view which looked at the chip | tip which comprises LED shown in FIG. 18 from the side in which the p electrode was formed. It is the top view which looked at the chip | tip which comprises LED shown in FIG. 18 from the side in which the n electrode was formed. It is a figure which shows Embodiment 2 of LED as a light-emitting device according to this invention. It is the top view which looked at the chip | tip which comprises LED shown in FIG. 21 from the side in which the p electrode was formed. It is the top view which looked at the chip | tip which comprises LED shown in FIG. 21 from the side in which the n electrode was formed. It is a flowchart for demonstrating the manufacturing method of LED shown in FIGS. FIG. 24 is a schematic plan view showing a state of the wafer when the LED chips shown in FIGS. 21 to 23 are taken from the wafer. It is a cross-sectional schematic diagram in line segment XXVI-XXVI of FIG. FIG. 26 is an enlarged schematic view showing a region corresponding to one chip in the wafer shown in FIG. 25. It is a figure which shows Embodiment 3 of LED as a light-emitting device according to this invention. It is a plane schematic diagram which shows the state of a wafer when the chip | tip of LED shown in FIG. 28 is extract | collected from a wafer. It is a top view which shows Embodiment 4 of LED as a light-emitting device according to this invention. It is the top view which looked at the chip | tip which comprises LED shown in FIG. 30 from the side in which the p electrode was formed. FIG. 32 is a schematic cross-sectional view taken along line XXXII-XXXII in FIG. 31. 10 is a diagram showing a comparative example B. FIG. It is a figure which shows the laminated structure containing the light emitting layer of LED of the comparative example B. It is a figure which shows the state of a wafer when the chip | tip of the laminated structure of the comparative example B is extract | collected from a wafer. It is a figure which shows arrangement | positioning of the electrode in FIG. It is a figure which shows the relationship between the applied electric current of this invention example A and the comparative example B, and optical output. It is a figure which shows the relationship between the current density in the light emitting layer of this invention example A and the comparative example B, and a light output. It is a figure which shows LED of this invention example C1 in Example 2 of this invention. It is a top view of LED of invention example C1 of FIG. It is a figure which shows LED of the comparative example E. It is a top view of LED of the comparative example E shown in FIG. It is a figure which shows LED of the example F of this invention in Example 3 of this invention. It is a figure which shows typically the flow of the electric current in the LED chip by calculation simulation. It is a figure which shows the current density ratio in the light emitting layer of LED in Example 3 of this invention. It is a figure which shows the relationship between the applied current and light output of LED (without fluorescent material) in Example 3 of this invention. It is a figure which shows the relationship between the current density and light output in the light emitting layer of LED (without fluorescent material) in Example 3 of this invention. It is a figure which shows the relationship between the applied electric current and light output of LED (with fluorescent material: white) in Example 3 of this invention. It is a figure which shows the relationship between the current density and light output in the light emitting layer of LED (with fluorescent material: white) in Example 3 of this invention. It is a figure which shows the outline | summary of the transmittance | permeability measurement test of LED in Example 4 of this invention. It is a figure which shows the condition where light permeate | transmits a board | substrate in the transmittance | permeability measurement test shown in FIG. It is a figure which shows the influence of the thickness of the board | substrate which has on the transmittance | permeability. In Example 5 of this invention, it is a figure which shows the state after performing the isolation | separation etching in order to extract | collect LED of this invention example L from a wafer. In Example 5 of this invention, in order to extract | collect LED of the comparative example M from a wafer, it is a figure which shows the state when etching of element isolation is performed and it is going to form n electrode in the bottom part of an etching groove | channel. In Example 5 of this invention, it is a figure which shows a state when etching of element isolation is performed in order to extract | collect LED of the comparative example N from a wafer, and it is going to form n electrode in the bottom part of an etching groove | channel. It is a figure which shows LED of this invention example Q of Example 7 of this invention. It is a figure which shows LED of this invention example R of Example 7 of this invention. It is a figure which shows LED of invention example S and T of Example 8 of this invention. It is a figure which shows LED of the example U of this invention of Example 8 of this invention. It is a figure which shows LED of this invention example W of Example 8 of this invention. It is a figure which shows the influence of the oxygen concentration which acts on the specific resistance of a GaN board | substrate in Example 9 of this invention. It is a figure which shows the influence of the oxygen concentration which acts on the transmittance | permeability of the light (wavelength 450nm) of a GaN substrate in Example 9 of this invention. It is a figure which shows the plane size through which the light output of the light emitting element and an electric current flow uniformly, when producing a light emitting element from the GaN substrate which changed thickness and oxygen concentration. In Example 10 of this invention, it is a figure which shows off-angle distribution from c surface of a 20 mm x 20 mm GaN substrate. It is a figure in Example 10 of this invention which shows the structure which has arrange | positioned the buffer layer between the GaN substrate and the AlGaN clad layer. In Example 10 of this invention, it is a figure which shows the result of having extended the off angle range which can obtain 8 mW or more of optical outputs. It is a figure which shows the core inherited by the epitaxial layer used as the hole-shaped recessed part. It is a figure which shows the state in which the core in the GaN substrate in Example 11 of this invention was inherited by the epitaxial layer. It is a figure which shows the light emitting element in Example 12 of this invention. It is sectional drawing which paid its attention to the p electrode of the light emitting element in Example 13 of this invention. FIG. 71 is a plan view seen through a p-electrode of the light emitting device of FIG. 70. It is a figure which shows light emission and reflection in this invention example S5 of Example 13. FIG. It is a figure which shows light emission and reflection in comparative example T6 of Example 13. FIG. It is a figure which shows the light emission and reflection in this invention example A quoted as a comparative example of Example 13. FIG. In Example 14 of this invention, it is a figure which shows the main surface of the GaN substrate in which the plate-shaped crystal reflective area | region has appeared in the grid | lattice form. FIG. 76 is a cross-sectional view of a GaN substrate showing the plate-like crystal reflection region of FIG. 75. It is sectional drawing which shows this invention example S6 of Example 14 of this invention. It is a top view which shows the plate-shaped crystal | crystallization area | region of the parallel arrangement different from FIG. 75 included in Example 14 of this invention. FIG. 79 is a cross-sectional view of FIG. 78. It is sectional drawing which shows light emission and reflection in this invention example S7 of Example 15 of this invention. It is sectional drawing which shows light emission and reflection in this invention example S8 which is another Example in Example 15 of this invention. It is sectional drawing which shows light emission and reflection in comparative example T7. It is a schematic diagram which shows the etching apparatus used in the manufacturing method of LED by this invention. It is a figure which shows the conventional LED.

Explanation of symbols

1 GaN substrate, 1a light emission surface (second main surface), 2 n-type GaN layer, 3 n-type Al _x Ga _1-x N layer, 4 MQW (light emitting layer), 5 p-type Al _x Ga _1-x N layer, 6 p-type GaN layer, 11 n electrode, 12 p electrode, 12a discretely arranged Ni / Au p electrode, 13 wires, 14 conductive adhesive, 15 epoxy resin, 21a lead frame mount, 21b Lead part of lead frame, 25 element isolation groove, 25a bottom part of element isolation groove, 26 fluorescent material, 31 n-type AlGaN buffer layer, 32 p-type InGaN layer, 33 Ag electrode layer, 35 highly reflective film, 46 fluorescent plate, 46a fluorescent plate Surface, 50 chip boundary, 51 plate crystal inversion region, 52 trench, 61 core (hole recess), 80 side surface, 82 boundary line, 84 frame, 85 presser plate, 86 airtight container lid, 87 airtight container, 88 D Chant, 89 presser bolt, 90 base plate, Dn electrode diameter, L1 p electrode side length, L2 scribe line interval (chip side length), L3 element isolation groove width, L4 etching groove side length, R1 off angle 0. 05 ° region, R2 off-angle 1.44 ° region, distance from the center of the light emitting layer, and thickness of the tn-type GaN layer.

Claims (17)

A nitride semiconductor substrate; a nitride semiconductor layer stacked on a first main surface of the nitride semiconductor substrate; a first electrode formed on the nitride semiconductor layer; and the nitride semiconductor substrate. A light emitting device including a second electrode formed on a second main surface which is a main surface opposite to the first main surface,
The nitride semiconductor substrate is
A region in which dislocation bundles in which dislocations are concentrated along the thickness direction from the first main surface to the second main surface of the nitride semiconductor substrate exist;
A single crystal region surrounded by a region where the dislocation bundle exists,
The light emitting device, wherein the single crystal region has a specific resistance of 0.5 Ω · cm or less. The light-emitting device according to claim 1, wherein a dislocation density in the single crystal region is 5E6 / cm ² or less.   3. The light emitting device according to claim 1, wherein a region where the dislocation bundle exists in the second main surface of the nitride semiconductor substrate forms a stripe pattern having a regular interval.   The region where the dislocation bundle exists on the second main surface of the nitride semiconductor substrate surrounds the single crystal region so that a planar shape of the single crystal region is a polygonal shape. The light emitting device according to 1.   5. The light emitting device according to claim 4, wherein the polygon formed by the region where the dislocation bundle exists has an inner angle of ((60 ° ± 3 °) × n) where n is a natural number.   The light emitting device according to claim 4 or 5, wherein the polygon formed by the region where the dislocation bundle is present is one selected from the group consisting of a regular triangle, a rhombus, a parallelogram, a trapezoid, and a hexagon. .   The light emitting device according to claim 1, wherein the nitride semiconductor substrate is divided in a region where the dislocation bundle exists.   The light-emitting device according to claim 7, wherein the nitride semiconductor substrate is divided in every other region among the regions where the dislocation bundle exists.   The light-emitting device according to claim 7 or 8, wherein a planar shape of the second main surface of the nitride semiconductor substrate is a polygonal shape.   10. The light emitting device according to claim 9, wherein the polygon formed by the second main surface has an interior angle of ((60 ° ± 3 °) × n) where n is a natural number.   The light emitting device according to claim 9 or 10, wherein the polygon formed by the second main surface is one selected from the group consisting of a regular triangle, a rhombus, a parallelogram, a trapezoid, and a hexagon.   The nitride semiconductor substrate is divided in a region where the dislocation bundle exists by etching the region where the dislocation bundle exists using an etchant of an alkaline solution. The light emitting device according to 1.   The light emitting device according to claim 12, wherein when etching the region where the dislocation bundle exists, the temperature of the etchant of the alkaline solution is set to 80 ° C. or higher.   The light emitting device according to claim 12 or 13, wherein when etching the region where the dislocation bundle exists, the temperature of the etchant of the alkaline solution is set to 250 ° C or lower.   The light emitting device according to claim 7, wherein an end surface of the nitride semiconductor substrate is inclined with respect to the first main surface.   The light-emitting device according to claim 7, wherein the second main surface of the nitride semiconductor substrate is subjected to non-mirror surface treatment. A method of manufacturing a light emitting device according to claim 7 or claim 8,
Immersing the nitride semiconductor substrate in an etchant of an alkaline solution;
And a dividing step of dividing the nitride semiconductor substrate by etching the nitride semiconductor substrate in a state where the etchant in which the nitride semiconductor substrate is immersed is sealed.

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