JP2006202989A - Soi wafer and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method for an SOI wafer being capable of forming an SOI layer on a thermal conductive substrate having a thermal conductivity larger than silicon without generating a thermal strain, a peeling, a cracking or the like and having the high film-thickness uniformity of the SOI layer. <P>SOLUTION: In the manufacturing method for the SOI wafer, the SOI layer is formed on the thermal conductive substrate by joining a single-crystal silicon wafer and the thermal conductive substrate, and thinning the single-crystal silicon wafer. In the manufacturing method, at least one of hydrogen ions or rare-gas ions is implanted from the surface of the single-crystal silicon wafer and an ion implanting layer is formed in the wafer, and the ion-implanting surface of the single-crystal silicon wafer and/or the surface of the thermal conductive substrate is treated by a plasma and/or ozone. In the manufacturing method, the ion-implanting surface of the single-crystal silicon wafer and the surface of the thermal conductive substrate are stuck fast and joined at a room temperature while using the treated surface as a joint surface, and an impact is applied to the ion implanting layer. Resultantly, the single-crystal silicon wafer is peeled mechanically, and the SOI layer is formed on the thermal conductive substrate. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an SOI wafer manufacturing method and an SOI wafer, and more particularly to an SOI wafer manufacturing method and an SOI wafer for forming an SOI layer on a thermally conductive substrate having a thermal conductivity higher than that of a single crystal silicon wafer. It is.

  An SOI wafer having an SOI (Silicon On Insulator) structure in which a silicon single crystal layer is formed on an insulator is suitable for manufacturing a high-speed and high-density semiconductor integrated circuit, and is used for manufacturing various devices.

  However, as the density increases, there is a problem in that the temperature of the SOI layer rises due to heat generated by elements such as transistors formed in the SOI layer, which hinders improvement in characteristics. Another problem is that if the current is increased for speeding up, the device generates heat and the speeding up is hindered.

  In order to solve the problem of heat generation due to such high density and high speed, by forming an SOI layer on an insulating thermal conductive substrate made of aluminum nitride or the like having a higher thermal conductivity than silicon, An SOI wafer is disclosed that has excellent heat dissipation from the substrate and can solve the problem of heat generation (see, for example, Patent Document 1). In this case, since the insulating property of the substrate is high, the mobility of carriers in the SOI layer is not affected by the substrate and becomes extremely high, and the effect when driven at a high frequency is remarkable.

  On the other hand, depending on the use of the SOI wafer, the SOI layer is thinned to a thickness of about 0.5 μm or less. At this time, the thermally conductive substrate and the SOI layer are firmly bonded so as to withstand the thermal and mechanical stress applied to the SOI layer during the fabrication and polishing of the SOI layer to reduce the thickness of the SOI layer. Therefore, it was necessary to increase the bonding strength by high-temperature heat treatment.

  However, since the coefficient of thermal expansion is different between the aluminum nitride substrate and the SOI layer, stress due to thermal strain is generated during the heat treatment for bonding, during cooling after bonding, during grinding, or polishing, and thus the aluminum nitride substrate or SOI layer. Cracks may occur in the layer, or they may be peeled off and damaged. Such a problem is not limited to the case where the thermally conductive substrate is an aluminum nitride substrate, but is a problem that inevitably arises when a single crystal silicon wafer is bonded to a substrate having a different thermal expansion coefficient.

  In order to solve this problem, in a method for manufacturing an SOI wafer using a hydrogen ion implantation delamination method, there is a technique for performing the bonding heat treatment step and the thinning step alternately in a stepwise manner to alleviate the influence of thermal stress generated during the heat treatment. It is disclosed (see, for example, Patent Document 2).

JP-A-10-223870 JP-A-11-145438

  The present invention relates to a method for manufacturing an SOI wafer in which an SOI layer is formed on a thermally conductive substrate having a thermal conductivity higher than that of a single crystal silicon wafer, resulting from a difference in thermal expansion coefficient between the thermally conductive substrate and the SOI layer. An object of the present invention is to provide an SOI wafer manufacturing method and an SOI wafer that can prevent the occurrence of thermal distortion, peeling, cracking, and the like by a simple process and that have a highly uniform SOI layer thickness.

In order to achieve the above object, the present invention relates to the heat conduction by thinning the single crystal silicon wafer after bonding the single crystal silicon wafer and a thermally conductive substrate having a higher thermal conductivity than the single crystal silicon wafer. In a method for manufacturing an SOI wafer by forming an SOI layer on a conductive substrate, at least,
Implanting at least one of hydrogen ions or rare gas ions from the surface of the single crystal silicon wafer to form an ion implantation layer in the wafer;
The step of treating the ion implantation surface of the single crystal silicon wafer and / or the surface of the thermally conductive substrate with plasma and / or ozone. The ion implantation surface of the single crystal silicon wafer and the surface of the thermally conductive substrate. A step of bringing the treated surface into close contact with each other at room temperature and bonding,
Impacting the ion-implanted layer to mechanically peel off the single crystal silicon wafer, and forming an SOI layer on the thermally conductive substrate;
A method for manufacturing an SOI wafer is provided.

  Thus, if the ion implantation surface of the single crystal silicon wafer and / or the surface of the thermally conductive substrate is treated with plasma and / or ozone, OH groups increase on the ion implantation surface of the wafer and / or the surface of the substrate. Activated. Therefore, in this state, if the single crystal silicon wafer and the thermally conductive substrate are bonded closely at room temperature with the treated surface as a bonding surface, the bonded surface is firmly bonded by hydrogen bonding, After that, sufficiently strong bonding can be achieved without performing high-temperature heat treatment for increasing the bonding force. In addition, since the joint surfaces are firmly joined in this way, it is possible to mechanically peel off the single crystal silicon wafer by applying an impact to the ion implantation layer and form a thin SOI layer on the thermally conductive substrate. Therefore, the film thickness can be reduced without performing heat treatment for peeling. Therefore, an SOI wafer can be manufactured without causing thermal distortion, peeling, cracking, or the like due to a difference in thermal expansion coefficient between the thermally conductive substrate and the single crystal silicon wafer. In addition, since a method of peeling after implanting hydrogen ions is used, an SOI wafer having an SOI layer that is thin and has excellent film thickness uniformity and excellent crystallinity can be manufactured.

In this case, after performing the bonding step, it is preferable to perform a step of increasing the bonding force by heat-treating the bonded wafer at 100 to 300 ° C., and then performing the peeling step.
In this way, the bonded single crystal silicon wafer and the thermally conductive substrate are heat-treated at a low temperature of 100 to 300 ° C. so as not to generate thermal strain, and the bonding force is further increased, and then the ion-implanted layer is impacted. By performing a mechanical peeling process, it is possible to more reliably prevent the occurrence of peeling, cracking, and the like of the joint surface due to mechanical stress, thereby manufacturing an SOI wafer.

Moreover, it is preferable to perform mirror polishing on the SOI layer surface of the SOI wafer obtained by the peeling step.
In this way, if the surface of the SOI layer of the SOI wafer obtained by the peeling process is mirror-polished, the surface roughness of the SOI layer generated in the peeling process or crystal defects generated in the ion implantation process can be removed, and the surface can be removed. An SOI wafer having a mirror-polished smooth SOI layer can be manufactured.

Alternatively, it is also preferable to subject the SOI wafer obtained by the peeling step to a heat treatment for flattening the surface of the SOI layer in an atmosphere of an inert gas, a hydrogen gas, or a mixed gas thereof (Claim 4).
Thus, even if the SOI wafer obtained by the peeling process is subjected to a heat treatment for planarizing the surface of the SOI layer in an inert gas, hydrogen gas, or mixed gas atmosphere thereof, the SOI layer generated by the peeling process is obtained. And surface defects near the surface of the SOI layer and damage caused by ion implantation can be removed.

In this case, after the step of performing a heat treatment for planarizing the SOI layer surface,
Thermally oxidizing the heat-treated SOI wafer to form a thermal oxide film on the surface of the SOI layer;
Reducing the thickness of the SOI layer by removing the thermal oxide film;
(Claim 5).
Thus, by performing thermal oxidation on the SOI wafer subjected to the heat treatment for planarizing the surface of the SOI layer to form a thermal oxide film on the surface of the SOI layer, and removing this to reduce the thickness of the SOI layer, It is possible to manufacture an SOI wafer having an SOI layer that is thinner and has good film thickness uniformity, and further has a rough surface and crystal defects and damages are sufficiently removed.

Moreover, it is preferable that the temperature of the heat treatment for flattening the surface of the SOI layer is 1100 to 1350 ° C. (Claim 6).
Thus, if the temperature of the heat treatment for flattening the SOI layer surface is 1100 ° C. or higher, the surface roughness can be improved in a relatively short time, and if it is 1350 ° C. or lower, contamination by heavy metal impurities occurs during the heat treatment. In addition, the SOI wafer can be manufactured without causing the durability problem of the heat treatment furnace.

Moreover, it is preferable that the thermally conductive substrate contains any of aluminum nitride, silicon carbide, boron nitride, and diamond.
Thus, if the thermally conductive substrate contains any of aluminum nitride, silicon carbide, boron nitride, and diamond, these are materials having a significantly higher thermal conductivity than silicon. It is possible to manufacture an SOI wafer that is excellent in heat dissipation and can solve the problem of heat generation.

In addition, the present invention provides an SOI wafer manufactured by any one of the above manufacturing methods.
As described above, if the SOI wafer is manufactured by any one of the manufacturing methods described above, thermal strain, peeling, cracking, etc. are not generated during manufacturing, and it is thinner and more useful for manufacturing various devices. Thus, an SOI wafer having an SOI layer on a thermally conductive substrate having excellent film thickness uniformity, excellent heat dissipation, crystallinity, and high carrier mobility.

  In the method for manufacturing an SOI wafer according to the present invention, before bonding a single crystal silicon wafer and a thermally conductive substrate, the surface to be bonded is treated with plasma and / or ozone to increase the OH groups on the surface and activate. Therefore, when the single crystal silicon wafer and the thermally conductive substrate are brought into close contact at room temperature and bonded in such a state, the bonded surfaces are firmly bonded by hydrogen bonding. Therefore, a sufficiently strong bond can be obtained without subsequent high-temperature heat treatment for increasing the bonding strength. In addition, since the joint surfaces are firmly joined in this way, it is possible to mechanically peel off the single crystal silicon wafer by applying an impact to the ion implantation layer and form a thin SOI layer on the thermally conductive substrate. it can. Accordingly, a thin film can be formed without performing heat treatment for peeling. In this manner, an SOI wafer can be manufactured without causing thermal strain, peeling, cracking, or the like due to the difference in thermal expansion coefficient between the thermally conductive substrate and single crystal silicon.

  In addition, the SOI wafer of the present invention is free from thermal distortion, delamination, cracks, etc. during manufacture, and has a thinner and better film thickness uniformity that is useful for manufacturing various devices. This is an SOI wafer having an SOI layer on a thermally conductive substrate having excellent properties, crystallinity, and high carrier mobility.

As described above, in the method for manufacturing an SOI wafer in which an SOI layer is formed on an insulating substrate, the occurrence of thermal strain, peeling, cracking, etc. due to the difference in thermal expansion coefficient between the insulating substrate and the SOI layer is solved. Therefore, in a method for manufacturing an SOI wafer using a hydrogen ion implantation delamination method, a technique is disclosed in which the bonding heat treatment step and the thinning step are alternately performed in steps to reduce the influence of thermal stress generated during the heat treatment. .
However, in order to improve the productivity of SOI wafers, there has been a demand for a technique that can reduce the number of processes and solve the above problems in a short time.

Therefore, the present inventors increase the bonding strength without performing heat treatment by performing plasma and / or ozone treatment on the surfaces to be bonded in advance, and perform heat treatment by performing mechanical peeling even during peeling. The present invention was completed by conceiving that it was peeled off.
Hereinafter, embodiments of the present invention will be described in detail, but the present invention is not limited thereto.

FIG. 1 is a process diagram showing an example of an SOI wafer manufacturing method according to the present invention.
First, a single crystal silicon wafer and a thermally conductive substrate having a thermal conductivity higher than that of the single crystal silicon wafer are prepared (step A).
The single crystal silicon wafer is not particularly limited. For example, the single crystal silicon wafer is obtained by slicing a single crystal grown by the Czochralski method. For example, the diameter is 100 to 300 mm, the conductivity type is P type or N type, and the resistivity. Can be about 10 Ω · cm.
Also, the heat conductive substrate is not particularly limited, but if it includes any of aluminum nitride, silicon carbide, boron nitride, and diamond, the substrate has a significantly higher thermal conductivity than the single crystal silicon wafer. . That is, the thermal conductivity of silicon is 148 W / mK, while aluminum nitride is 330 W / mK, silicon carbide (SiC) is 450 W / mK, and boron nitride is 600 W in cubic boron nitride (c-BN). / MK and diamond are 2000 W / mK, which is sufficiently large, so that an SOI wafer excellent in heat dissipation from the substrate can be manufactured using this.

Next, at least one of hydrogen ions or rare gas ions is implanted from the surface of the single crystal silicon wafer to form an ion implantation layer in the wafer (step B).
For example, the temperature of the single crystal silicon wafer is set to 250 to 450 ° C., and the implantation energy is such that the ion implantation layer can be formed from the surface to a depth corresponding to a desired SOI layer thickness, for example, a depth of 0.5 μm or less. Then, at least one of a predetermined dose of hydrogen ions or rare gas ions is implanted. As conditions at this time, for example, the implantation energy can be 50 to 100 keV, and the implantation dose can be 1 × 10 ¹⁶ to 1 × 10 ¹⁷ / cm ² . Further, if an insulating film such as a thin silicon oxide film is formed in advance on the surface of the single crystal silicon wafer and ion implantation is performed therethrough, an effect of suppressing channeling of implanted ions can be obtained.

Next, the ion implantation surface of this single crystal silicon wafer and / or the surface of the thermally conductive substrate are treated with plasma and / or ozone (step C).
When processing with plasma, a single crystal silicon wafer and / or a thermally conductive substrate cleaned by RCA cleaning or the like is placed in a vacuum chamber, a plasma gas is introduced, and a high frequency plasma of about 100 W is applied to a high frequency plasma of 5 The surface is subjected to plasma treatment for about 10 seconds. As a gas for plasma, when processing a single crystal silicon wafer, when oxidizing the surface, plasma of oxygen gas, when not oxidizing, hydrogen gas, argon gas, or a mixed gas thereof or hydrogen gas and helium gas A mixed gas can be used. When processing a thermally conductive substrate, any gas may be used.

  When processing with ozone, a single crystal silicon wafer and / or a thermally conductive substrate that has been cleaned by RCA cleaning or the like is placed in a chamber in which air is introduced, and a plasma gas such as nitrogen gas or argon gas is introduced. After that, the surface is subjected to ozone treatment by generating high-frequency plasma and converting atmospheric oxygen into ozone. Either or both of plasma treatment and ozone treatment can be performed.

  By treating with this plasma and / or ozone, organic substances on the surface of the single crystal silicon wafer and / or the thermally conductive substrate are oxidized and removed, and the OH groups on the surface are increased and activated. A surface to be processed is a bonding surface, and a single crystal silicon wafer is an ion implantation surface. The treatment is preferably performed on both the single crystal silicon wafer and the thermally conductive substrate, but only one of them may be performed.

Next, the ion-implanted surface of the single crystal silicon wafer and the surface of the thermally conductive substrate are bonded to each other at a room temperature using a surface treated with plasma and / or ozone as a bonding surface (step D).
In step C, at least one of the ion-implanted surface of the single crystal silicon wafer and the surface of the thermally conductive substrate is subjected to plasma treatment and / or ozone treatment. It is possible to bond strongly with the strength that can withstand mechanical peeling in the subsequent process simply by making it adhere underneath. Therefore, a high-temperature bonding heat treatment such as 1200 ° C. or higher is not necessary, and there is no fear of occurrence of thermal strain, cracking, peeling or the like due to a difference in thermal expansion coefficient that is a problem due to heating.

In addition, after this, you may perform the process which heat-processes the joined wafer at the low temperature of 100-300 degreeC, and raises bond strength (process E).
For example, when the thermally conductive substrate is a SiC substrate, the thermal expansion coefficient is larger than that of silicon (Si: 2.33 × 10 ⁻⁶ , SiC: 3.7 to 4.7 × 10 ⁻⁶ ), and the same thickness. If the silicon wafer is pasted and heated, the silicon wafer will break if it exceeds 300 ° C. However, such a relatively low-temperature heat treatment is preferable because there is no fear of thermal distortion, cracking, peeling due to a difference in thermal expansion coefficient. In the case of using a batch processing type heat treatment furnace, a sufficient effect can be obtained if the heat treatment time is about 0.5 to 24 hours.

Next, an impact is applied to the ion implantation layer to mechanically peel off the single crystal silicon wafer, and an SOI layer is formed on the thermally conductive substrate (step F).
In the hydrogen ion implantation separation method, the bonded wafer is heat-treated at about 500 ° C. in an inert gas atmosphere, and thermal separation is performed by the effect of crystal rearrangement and the aggregation effect of the injected hydrogen bubbles. In the invention, impact is applied to the ion-implanted layer to perform mechanical peeling, so that there is no possibility that thermal strain, cracking, peeling, etc. due to heating occur.
In order to give an impact to the ion-implanted layer, for example, a jet of a fluid such as a gas or a liquid may be sprayed continuously or intermittently from the side surface of the wafer. There is no particular limitation.

Thus, an SOI wafer in which an SOI layer is formed on a thermally conductive substrate is obtained by the peeling process, and it is preferable to perform mirror polishing on the surface of the SOI layer of the SOI wafer thus obtained (process G).
By this mirror polishing, surface roughness called haze generated in the peeling process can be removed, and crystal defects near the SOI layer surface caused by ion implantation can be removed. As this mirror polishing, for example, polishing called “touch polish” with a polishing margin of 5 to 400 nm being extremely small can be used.

The SOI wafer manufactured by the processes A to G is free from thermal distortion, peeling, cracking, etc. during manufacturing, and has a thin and good film thickness uniformity that is useful for manufacturing various devices. Thus, an SOI wafer having an SOI layer on a thermally conductive substrate having excellent crystallinity and high carrier mobility can be obtained.
In addition, since such an SOI wafer has an SOI layer formed on a thermally conductive substrate, it has excellent heat dissipation from the substrate and is particularly suitable for increasing the density and speed of devices.

FIG. 2 is a process diagram showing another example of a method for manufacturing an SOI wafer according to the present invention.
About process A '-process F', it carries out similarly to process AF shown in FIG. Through these steps, an SOI wafer having an SOI layer formed on a thermally conductive substrate is obtained.

  Next, the SOI wafer thus obtained is preferably subjected to a heat treatment for flattening the surface of the SOI layer as a separation surface in an inert gas, hydrogen gas, or mixed gas atmosphere thereof (step G). ').

In the case where mirror polishing is performed using polishing with an extremely small polishing allowance of 5 to 400 nm, for example, called touch polishing, as in the above-described process G, if polishing including such a machining element in the SOI layer is performed. The film thickness uniformity of the SOI layer may also be reduced.
Even in such a case, if the heat treatment for flattening the surface of the SOI layer is performed in an inert gas, hydrogen gas, or a mixed gas atmosphere thereof as in step G ′, it is caused by the peeling step. Thus, surface roughness and crystal defects and damage in the vicinity of the SOI layer surface caused by ion implantation can be removed while maintaining film thickness uniformity.

  Note that the heat treatment temperature for planarizing the SOI layer surface is preferably set to 1100 to 1350 ° C. If the heat treatment temperature is 1100 ° C. or higher, the surface roughness can be improved in a relatively short time. If the heat treatment temperature is 1350 ° C. or lower, there is no problem with contamination by heavy metal impurities or heat treatment furnace durability. . Note that since the SOI layer has already been sufficiently thinned, there is no fear of occurrence of thermal strain, peeling, cracking, etc. even if such high-temperature heat treatment is performed.

  Further, the heat treatment time depends on the heat treatment temperature, but when performing heat treatment in a normal heater-heating type heat treatment furnace (batch type), in order to exhibit a sufficient heat treatment effect without reducing the productivity, 10 minutes to A range of 8 hours is appropriate. On the other hand, when this heat treatment is performed using an RTA (Rapid Thermal Annealing) apparatus, it is preferable that the heat treatment temperature is 1200 ° C. or higher and the heat treatment time is 1 to 120 seconds. Also, the heat treatment by these batch furnaces and the heat treatment by the RTA apparatus can be performed in combination.

  The heat treatment atmosphere may be an inert gas, hydrogen gas, or a mixed gas atmosphere thereof. However, if the proportion of hydrogen gas is large, corrosion at the bonding interface is likely to occur, and slip dislocation occurs due to the heat treatment. Therefore, the hydrogen gas content is preferably 25% or less. Furthermore, from the viewpoint of safety, it is preferable that the hydrogen gas has a content not more than the explosion limit (4%). As the inert gas, the most inexpensive and highly versatile argon gas is suitable, but helium or the like may be used.

If necessary, after the heat treatment for flattening the surface of the SOI layer in the step G ′, the surface may be slightly polished (touch allowance of 70 nm or less, particularly 50 nm or less) by touch polishing or the like (step H ′ ).
As a result, the long-period component of the surface roughness (for example, a period of about 1 to 10 μm) can be improved. That is, the short-period component (for example, a period of 1 μm or less) having a rough surface is sufficiently removed by the heat treatment in the process G ′, but in order to more reliably remove the long-period component, it is removed by slight polishing. Is preferred. In this way, once the heat treatment is performed, the surface roughness and surface damage are greatly improved, so the polishing allowance can be greatly reduced compared to the conventional one, and in particular, it can be reduced to less than half. This is possible, and it is possible to reliably improve the long-period component of the surface roughness while minimizing the influence on the film thickness uniformity of the thin film.

Next, if necessary, the heat-treated SOI wafer is thermally oxidized to form a thermal oxide film, a so-called sacrificial oxide film on the surface of the SOI layer (step I ′).
By forming a thermal oxide film on the surface of the SOI layer in this way, crystal defects and damage that could not be removed in step G ′ can be taken into the thermal oxide film, and the film thickness uniformity is hardly lowered. The SOI layer can be thinned to a predetermined thickness. The thermal oxide film can be formed, for example, by performing pyrogenic oxidation at a temperature of 950 ° C., but the method for forming the oxide film is not particularly limited.

Finally, the thickness of the SOI layer can be reduced by removing the formed thermal oxide film (step J ′).
The removal of the thermal oxide film can be performed, for example, by immersing the wafer in an aqueous solution containing HF.
In this way, an SOI wafer having an SOI layer formed on a thermally conductive substrate is obtained.

And, the SOI wafer manufactured by the processes A ′ to J ′ is free from thermal distortion, peeling, cracking, etc. during the production, and is thin and has a good uniform film thickness that is useful for manufacturing various devices. And an SOI wafer having an SOI layer on a thermally conductive substrate having excellent crystallinity and high carrier mobility.
In particular, since the touch polishing can be omitted or can be performed only with a very small polishing allowance, it is possible to obtain an SOI wafer in which a decrease in film thickness uniformity due to polishing including a machining element does not occur with certainty.
In addition, since such an SOI wafer has an SOI layer formed on a thermally conductive substrate, it has excellent heat dissipation from the substrate and is particularly suitable for increasing the density and speed of devices.

  The present invention is not limited to the above embodiment. The above embodiment is merely an example, and the present invention has any configuration that has substantially the same configuration as the technical idea described in the claims of the present invention and that exhibits the same operational effects. It is included in the technical idea of the invention.

It is process drawing which shows an example of the manufacturing method of the SOI wafer which concerns on this invention. It is process drawing which shows another example of the manufacturing method of the SOI wafer which concerns on this invention.

Claims (8)

After bonding a single crystal silicon wafer and a thermally conductive substrate having a thermal conductivity larger than that of the single crystal silicon wafer, an SOI layer is formed on the thermally conductive substrate by thinning the single crystal silicon wafer. In a method for manufacturing an SOI wafer, at least:
Implanting at least one of hydrogen ions or rare gas ions from the surface of the single crystal silicon wafer to form an ion implantation layer in the wafer;
The step of treating the ion implantation surface of the single crystal silicon wafer and / or the surface of the thermally conductive substrate with plasma and / or ozone. The ion implantation surface of the single crystal silicon wafer and the surface of the thermally conductive substrate. A step of bringing the treated surface into close contact with each other at room temperature and bonding,
Impacting the ion-implanted layer to mechanically peel off the single crystal silicon wafer, and forming an SOI layer on the thermally conductive substrate;
A method for manufacturing an SOI wafer, comprising:   2. The method for manufacturing an SOI wafer according to claim 1, wherein after the bonding step, the bonding wafer is heat-treated at 100 to 300 ° C. to increase the bonding strength, and then the peeling step is performed. A method for manufacturing an SOI wafer.   3. The method for manufacturing an SOI wafer according to claim 1, wherein the surface of the SOI layer of the SOI wafer obtained by the peeling step is subjected to mirror polishing.   3. The SOI wafer manufacturing method according to claim 1, wherein the SOI layer surface is planarized in an inert gas, hydrogen gas, or a mixed gas atmosphere of the SOI wafer obtained by the peeling step. A method of manufacturing an SOI wafer, characterized by performing a heat treatment. 5. The method for manufacturing an SOI wafer according to claim 4, wherein a heat treatment for flattening the surface of the SOI layer is performed.
Thermally oxidizing the heat-treated SOI wafer to form a thermal oxide film on the surface of the SOI layer;
Reducing the thickness of the SOI layer by removing the thermal oxide film;
A method for manufacturing an SOI wafer, comprising:   6. The method for manufacturing an SOI wafer according to claim 4, wherein a temperature of heat treatment for flattening the surface of the SOI layer is set to 1100 to 1350 ° C. 6.   7. The method for manufacturing an SOI wafer according to claim 1, wherein the thermally conductive substrate includes any one of aluminum nitride, silicon carbide, boron nitride, and diamond. Manufacturing method of SOI wafer.   An SOI wafer manufactured by the manufacturing method according to claim 1.

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