JP2006202897A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
JP2006202897A
JP2006202897A JP2005011568A JP2005011568A JP2006202897A JP 2006202897 A JP2006202897 A JP 2006202897A JP 2005011568 A JP2005011568 A JP 2005011568A JP 2005011568 A JP2005011568 A JP 2005011568A JP 2006202897 A JP2006202897 A JP 2006202897A
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Prior art keywords
wiring pattern
semiconductor device
bonding
chip
bump
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JP2005011568A
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Japanese (ja)
Inventor
Toshiyuki Hori
利之 堀
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Seiko Epson Corp
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Seiko Epson Corp
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Priority to JP2005011568A priority Critical patent/JP2006202897A/en
Publication of JP2006202897A publication Critical patent/JP2006202897A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

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  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device wherein the joint reliability between a bump provided on an IC chip and a wiring pattern formed on a substrate is sufficiently secured. <P>SOLUTION: The method is used to mount an IC chip 20 having a bump 22 on its circuit surface onto a film substrate 10 with a wiring pattern 12 from the inside of a bonding area to the outside thereof, and to manufacture a semiconductor device 100. The method includes steps of: applying an NCP resin 30 on the bonding area of the film substrate 10; and pressing the circuit surface of the IC chip 20 onto the bonding area where the NCP resin 30 is applied, and joining the bump 22 of the IC chip 20 with the wiring pattern 12 of the film substrate 10. In the joint step to join the bump 22 with the wiring pattern 12, the joint temperature is set at 200°C or more, namely, the heat resistance temperature value or less of the semiconductor device 100, and the joint load is set at 25 kgf/mm<SP>2</SP>or more, namely, the pressure-resistance load value or less of the semiconductor device 100. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体装置の製造方法に関し、特に、ＩＣチップの回路面に設けられたバンプと、基板に設けられた配線パターンとの接合強度を高める技術に関するものである。   The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique for increasing the bonding strength between a bump provided on a circuit surface of an IC chip and a wiring pattern provided on a substrate.

ＮＣＰ（ｎｏｎ ｃｏｎｄｕｃｔｉｖｅ ｐａｓｔｅ）方式のＣＯＦ（ｃｈｉｐ ｏｎ Ｆｌｅｘｉｂｌｅ Ｔａｐｅ）に関する従来技術としては、例えば特許文献１に開示されたものがある。
この特許文献１では、その第１図に示されているように、半導体素子に形成された金属突起を、ＮＣＰ樹脂が塗布された配線基板の配線パターン上に圧接して（即ち、接触させて）、当該間を電気的に接続するようになっている。また、この圧接と共に、ＮＣＰ樹脂に光もしくは熱を加えてＮＣＰ樹脂を硬化させて、半導体素子を配線基板に固定するようになっている。つまり、金属突起と配線パターンとの電気的接続は圧接で行われ、半導体素子と配線基板との固定は硬化したＮＣＰ樹脂によってなされている。 As a conventional technique related to a non-conductive paste (NCP) type COF (chip on Flexible Tape), there is one disclosed in, for example, Patent Document 1.
In Patent Document 1, as shown in FIG. 1, a metal protrusion formed on a semiconductor element is pressed against (ie, brought into contact with) a wiring pattern of a wiring board coated with NCP resin. ), Which is electrically connected. In addition, along with this press contact, light or heat is applied to the NCP resin to cure the NCP resin, thereby fixing the semiconductor element to the wiring board. That is, the electrical connection between the metal protrusion and the wiring pattern is performed by pressure contact, and the semiconductor element and the wiring board are fixed by the cured NCP resin.

このような構成であると、半導体素子の金属突起と配線基板の配線パターンとは単に圧接しているのみであるから、配線パターンの材質を特定の材料に限定したり、多層構成にしたりする必要がない、という効果を得ることができた。
特公平０２−００７１８０号公報 With such a configuration, the metal protrusions of the semiconductor element and the wiring pattern of the wiring board are merely in pressure contact with each other. Therefore, it is necessary to limit the material of the wiring pattern to a specific material or a multilayer structure. I was able to get the effect that there was no.
Japanese Patent Publication No. 02-007180

ところで、上記公報に開示されたような従来技術、即ち、従来のＮＣＰ方式のＣＯＦにあっては、半導体素子の配線基板に対する固定はＮＣＰ樹脂によってなされており、このＮＣＰ樹脂の収縮応力によって、半導体素子（以下、「ＩＣチップ」という。）の金属突起が配線基板の配線パターン上に押し付けられていた。
ここで、ＮＣＰ樹脂としては、通常、エポキシ樹脂が使用されるが、エポキシ樹脂は他の構成部材と比較し線膨張係数が大きく、加熱・冷却時に伸び縮みが大きい。このため、従来技術では、エポキシ樹脂が伸縮すると、エポキシ樹脂に押されて（又は、引っ張られて）金属突起と配線パターンとが相対的に位置ずれしてしまい、当該間の電気的接続が損なわれてしまうおそれがあった。つまり、金属突起（以下、「バンプ」という。）と配線パターンとの接合信頼性が十分でない可能性があった。 By the way, in the conventional technique disclosed in the above publication, that is, in the conventional NCP type COF, the semiconductor element is fixed to the wiring substrate by the NCP resin. The metal protrusion of the element (hereinafter referred to as “IC chip”) was pressed onto the wiring pattern of the wiring board.
Here, as the NCP resin, an epoxy resin is usually used, but the epoxy resin has a larger coefficient of linear expansion than other components, and has a large expansion and contraction during heating and cooling. For this reason, in the prior art, when the epoxy resin expands and contracts, the metal protrusion and the wiring pattern are relatively displaced by being pushed (or pulled) by the epoxy resin, and the electrical connection therebetween is impaired. There was a risk of being lost. That is, there is a possibility that the bonding reliability between the metal protrusion (hereinafter referred to as “bump”) and the wiring pattern is not sufficient.

本発明は、このような従来の技術の有する未解決の課題に着目してなされたものであって、ＩＣチップに設けられたバンプと、基板に設けられた配線パターンとの接合信頼性を十分に確保することができるようにした半導体装置の製造方法の提供を目的とする。   The present invention has been made paying attention to such an unsolved problem of the conventional technology, and has sufficient bonding reliability between the bumps provided on the IC chip and the wiring pattern provided on the substrate. It is an object of the present invention to provide a method of manufacturing a semiconductor device that can be ensured for a long time.

〔発明１〕 上記目的を達成するために、発明１の半導体装置の製造方法は、回路面にバンプを有するＩＣチップを、所定領域の内側から外側にかけて配線パターンを有する基板上に取り付けて半導体装置を製造する方法であって、前記基板の前記所定領域上に樹脂を塗布する工程と、前記樹脂が塗布された前記所定領域上に前記ＩＣチップの前記回路面を押し当てて、前記ＩＣチップの前記バンプを前記基板の前記配線パターンに接合する工程と、を含み、前記バンプを前記配線パターンに接合する工程では、前記バンプと前記配線パターンとの間の接合温度を２００［℃］以上、前記半導体装置の耐熱温度値以下とし、かつ、当該間に加えられる接合荷重を２４５［Ｎ／ｍｍ２］（＝２５［ｋｇｆ／ｍｍ２］）以上、前記半導体装置の耐圧荷重値以下とすることを特徴とするものである。
このような構成であれば、従来技術と比べて、バンプと配線パターンとの接合部分に一定の大きさ以上の接合強度を持たせることができ、十分な接合信頼性を確保することができる。 [Invention 1] In order to achieve the above object, a method of manufacturing a semiconductor device according to Invention 1 includes attaching an IC chip having bumps on a circuit surface to a substrate having a wiring pattern from the inside to the outside of a predetermined region. A step of applying a resin on the predetermined area of the substrate, and pressing the circuit surface of the IC chip on the predetermined area on which the resin is applied. Bonding the bump to the wiring pattern of the substrate, and in the step of bonding the bump to the wiring pattern, a bonding temperature between the bump and the wiring pattern is 200 [° C.] or more, heat resistance temperature value or less and to a semiconductor device and a bonding load applied between the 245 [N / mm 2] ( = 25 [kgf / mm 2]) or more, the semiconductor device It is characterized in that less pressure load value.
With such a configuration, compared with the prior art, the bonding strength between the bump and the wiring pattern can be given a certain level of bonding strength, and sufficient bonding reliability can be ensured.

〔発明２〕 発明２の半導体装置の製造方法は、発明１の半導体装置の製造方法において、前記配線パターンの表面には錫（Ｓｎ）メッキが施され、前記バンプを前記配線パターンに接合する工程では、前記バンプと前記配線パターンとの間の接合温度を２７０［℃］以上、前記半導体装置の耐熱温度値以下とし、かつ、当該間に加えられる接合荷重を２９４［Ｎ／ｍｍ２］（＝３０［ｋｇｆ／ｍｍ２］）以上、前記半導体装置の耐圧荷重値以下とすることを特徴とするものである。
このような構成であれば、バンプと配線パターンとの接合部分に４０［ｇｆ／ｍｍ２］以上の接合強度を持たせることができる。 [Invention 2] The method of manufacturing a semiconductor device of Invention 2 is the method of manufacturing a semiconductor device of Invention 1, wherein the surface of the wiring pattern is subjected to tin (Sn) plating, and the bump is bonded to the wiring pattern. Then, the bonding temperature between the bump and the wiring pattern is set to 270 [° C.] or more and the heat resistance temperature value of the semiconductor device or less, and the bonding load applied between the bumps and the wiring pattern is 294 [N / mm 2 ] (= 30 [kgf / mm 2 ]) to a pressure load value of the semiconductor device or less.
With such a configuration, a bonding strength of 40 [gf / mm 2 ] or more can be given to the bonding portion between the bump and the wiring pattern.

〔発明３〕 発明３の半導体装置の製造方法は、発明１の半導体装置の製造方法において、前記配線パターンの表面には金（Ａｕ）メッキが施されていることを特徴とするものである。
このような構成であれば、配線パターンにＳｎメッキを施されている場合と比べて、同一の接合温度、かつ同一の接合荷重で、配線パターンとバンプとにより大きな接合強度を持たせることができる。
本発明は、ＮＣＰ方式のＣＯＦに適用して極めて好適である。 [Invention 3] The semiconductor device manufacturing method of Invention 3 is characterized in that, in the semiconductor device manufacturing method of Invention 1, the surface of the wiring pattern is gold (Au) plated.
With such a configuration, the wiring pattern and the bump can have a higher bonding strength at the same bonding temperature and the same bonding load as compared with the case where the wiring pattern is Sn plated. .
The present invention is extremely suitable when applied to an NCP COF.

以下、図面を参照しながら、本発明に係る半導体装置の製造方法について説明する。
（１）実施形態
図１は本発明の実施形態に係る半導体装置１００の構成例を示す断面図である。図１に示すように、この半導体装置１００は、フィルム基板１０と、ＩＣチップ２０と、ＮＣＰ樹脂３０と、を含んだ構成となっている。 Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings.
(1) Embodiment FIG. 1 is a cross-sectional view showing a configuration example of a semiconductor device 100 according to an embodiment of the present invention. As shown in FIG. 1, the semiconductor device 100 includes a film substrate 10, an IC chip 20, and an NCP resin 30.

フィルム基板１０は、例えばポリイミド基材１１と、このポリイミド基材１１の表面に形成された配線パターン１２等から構成されている。配線パターン１２は、ポリイミド基材１１の表面に画定されたＩＣチップ２０のボンディング領域の内側から外側にかけて形成されている。この配線パターン１２は、例えば銅パターンの表面上に錫（Ｓｎ）メッキが施されたものである。Ｓｎメッキの総厚は例えば０．２μｍ以上であり、その内の純Ｓｎ層は０．０５μｍ以上である。   The film substrate 10 includes, for example, a polyimide base material 11 and a wiring pattern 12 formed on the surface of the polyimide base material 11. The wiring pattern 12 is formed from the inside to the outside of the bonding region of the IC chip 20 defined on the surface of the polyimide base material 11. For example, the wiring pattern 12 is obtained by performing tin (Sn) plating on the surface of a copper pattern. The total thickness of the Sn plating is, for example, 0.2 μm or more, and the pure Sn layer therein is 0.05 μm or more.

ＩＣチップ２０は、その回路面をフィルム基板１０に向けた状態で、フィルム基板１０のボンディング領域上に取り付けられており、その回路面に設けられたバンプ２２は、ボンディング領域内側の配線パターン１２上に接合されている。また、ＮＣＰ樹脂３０は、ＩＣチップ２０の回路面を封止するための絶縁性樹脂であり、例えばエポキシ樹脂からなるものである。このＮＣＰ樹脂３０は、ＩＣチップ２０とフィルム基板１０との間に充填されている。このような形態の半導体装置１００は、ＮＣＰ方式のＣＯＦとも呼ばれている。次に、この半導体装置１００の製造方法について説明する。   The IC chip 20 is mounted on the bonding region of the film substrate 10 with its circuit surface facing the film substrate 10, and the bumps 22 provided on the circuit surface are on the wiring pattern 12 inside the bonding region. It is joined to. The NCP resin 30 is an insulating resin for sealing the circuit surface of the IC chip 20, and is made of, for example, an epoxy resin. The NCP resin 30 is filled between the IC chip 20 and the film substrate 10. The semiconductor device 100 having such a configuration is also called an NCP type COF. Next, a method for manufacturing the semiconductor device 100 will be described.

図２（Ａ）〜（Ｄ）は、半導体装置１００の製造方法を示す工程図である。
図２（Ａ）に示すように、まず始めに、配線パターン１２を上方向に向けた状態で、フィルム基板１０をボンディング装置の基板固定台（ステージ）１５０上に固定する。固定方法は、例えば真空吸着である。次に、図２（Ｂ）に示すように、フィルム基板１０表面のボンディング領域上にＮＣＰ樹脂３０を塗布する。ＮＣＰ樹脂３０の塗布は、例えば、ステージ１５０上に配置された図示しないノズルから、ステージ１５０上に固定されたフィルム基板１０のボンディング領域上に、ＮＣＰ樹脂３０を滴下させることにより行う。この時点では、ＮＣＰ樹脂３０は所定の流動性を有している。 2A to 2D are process diagrams illustrating a method for manufacturing the semiconductor device 100.
As shown in FIG. 2A, first, the film substrate 10 is fixed on the substrate fixing stage (stage) 150 of the bonding apparatus with the wiring pattern 12 facing upward. The fixing method is, for example, vacuum adsorption. Next, as shown in FIG. 2B, an NCP resin 30 is applied on the bonding region on the surface of the film substrate 10. The NCP resin 30 is applied by, for example, dropping the NCP resin 30 onto a bonding area of the film substrate 10 fixed on the stage 150 from a nozzle (not shown) disposed on the stage 150. At this time, the NCP resin 30 has a predetermined fluidity.

また、このＮＣＰ樹脂３０の滴下と前後して、または同時に、図２（Ｃ）に示すように、ボンディング装置のＩＣ固定治具（ツール）１６０で、ＩＣチップ２０の回路面の反対側（即ち、ミラー面）を吸着支持する。このとき、ツール１６０の温度を例えば２８０［℃］に設定しておく。そして、図２（Ｄ）に示すように、ＩＣチップ２０を吸着したツール１６０をステージ１５０側に下降させて、ＩＣチップ２０の回路面をフィルム基板１０のボンディング領域上に接触させる。そして、そのまま荷重を加える。   Also, before or after the dropping of the NCP resin 30 or simultaneously, as shown in FIG. 2C, the IC fixing jig (tool) 160 of the bonding apparatus is used to oppose the circuit surface of the IC chip 20 (that is, the opposite side). , Mirror surface). At this time, the temperature of the tool 160 is set to 280 [° C.], for example. Then, as shown in FIG. 2D, the tool 160 that sucks the IC chip 20 is lowered to the stage 150 side, and the circuit surface of the IC chip 20 is brought into contact with the bonding area of the film substrate 10. Then, the load is applied as it is.

ここで、ＩＣチップ２０はツール１６０によって１、２秒程度の短時間の内に加熱され、バンプ２２の温度は例えば２８０［℃］程度となっている。つまり、ツール１６０と同程度の温度まで加熱されている。また、ツール１６０からＩＣチップ２０及びフィルム基板１０に加える荷重は、例えば３２．５［ｋｇｆ／ｍｍ２］程度である。ステージ１５０の温度は例えば１００［℃］であり、接合時間は例えば３秒である。 Here, the IC chip 20 is heated by the tool 160 within a short time of about 1 or 2 seconds, and the temperature of the bump 22 is about 280 [° C.], for example. That is, it is heated to the same temperature as the tool 160. The load applied from the tool 160 to the IC chip 20 and the film substrate 10 is, for example, about 32.5 [kgf / mm 2 ]. The temperature of the stage 150 is, for example, 100 [° C.], and the bonding time is, for example, 3 seconds.

このような熱と荷重とを加えたボンディングにより、フィルム基板１０の配線パターン１２上にＩＣチップ２０のバンプ２２を接合して、図１に示した半導体装置１００を完成させる。図２（Ｄ）に示す工程では、ツール１６０からＩＣチップ２０を介してＮＣＰ樹脂３０にも熱が伝わる。そして、この熱によってＮＣＰ樹脂３０は流動性を失い、収縮して硬化する。そのため、図２（Ｄ）の工程以降で、ＮＣＰ樹脂３０を固めるためのプリキュア工程は不要である。   The bump 22 of the IC chip 20 is bonded onto the wiring pattern 12 of the film substrate 10 by bonding applying such heat and load, and the semiconductor device 100 shown in FIG. 1 is completed. In the step shown in FIG. 2D, heat is also transferred from the tool 160 to the NCP resin 30 via the IC chip 20. The NCP resin 30 loses fluidity due to this heat and shrinks and hardens. Therefore, the pre-cure process for hardening the NCP resin 30 is unnecessary after the process of FIG.

このように本発明の実施形態に係る半導体装置１００の製造方法によれば、バンプ２２を配線パターン１２に接合する工程では、バンプ２２と配線パターン１２との間の接合温度を２００［℃］以上、半導体装置１００の耐熱温度値以下としている。かつ、バンプ２２と配線パターン１２との間に加えられる接合荷重を２５［ｋｇｆ／ｍｍ２］以上、半導体装置１００の耐圧荷重値以下としている。耐熱温度値は例えば５００［℃］であり、耐圧荷重値は例えば本評価仕様では１３８［ｋｇｆ／ｍｍ２］（総荷重５００［Ｎ］）である（耐熱温度値、耐圧荷重値は、半導体装置のバンプや配線パターンの構造及びその材質等によってそれぞれ異なる。）。 As described above, according to the method for manufacturing the semiconductor device 100 according to the embodiment of the present invention, in the step of bonding the bump 22 to the wiring pattern 12, the bonding temperature between the bump 22 and the wiring pattern 12 is 200 ° C. or higher. The heat resistance temperature value of the semiconductor device 100 is set to be equal to or lower. In addition, the bonding load applied between the bump 22 and the wiring pattern 12 is set to 25 [kgf / mm 2 ] or more and equal to or less than the pressure load value of the semiconductor device 100. The heat-resistant temperature value is, for example, 500 [° C.], and the pressure-resistant load value is, for example, 138 [kgf / mm 2 ] (total load 500 [N]) in this evaluation specification. Depending on the structure of bumps and wiring patterns and the material of each.)

このような構成であれば、従来技術と比べて、バンプ２２と配線パターン１２との接合部分に一定の大きさ以上の接合強度を持たせることができ、十分な接合信頼性を確保することができる。
また、〔実験１〕及び〔実験２〕で後述するように、特に、配線パターン１２の表面にＳｎメッキが施されている場合には、接合温度を２７０［℃］以上、半導体装置１００の耐熱温度値以下とし、かつ、接合荷重を３０［ｋｇｆ／ｍｍ２］以上、半導体装置１００の耐圧荷重値以下とすることで、バンプ２２と配線パターン１２との接合部分に４０［ｇｆ／ｍｍ２］以上の接合強度を持たせることができる。 With such a configuration, the bonding portion between the bump 22 and the wiring pattern 12 can have a bonding strength of a certain size or more, and sufficient bonding reliability can be ensured as compared with the prior art. it can.
Further, as will be described later in [Experiment 1] and [Experiment 2], particularly when the surface of the wiring pattern 12 is Sn-plated, the junction temperature is 270 [° C.] or more, and the heat resistance of the semiconductor device 100 is increased. By setting the bonding load to 30 [kgf / mm 2 ] or more and not more than the pressure resistance load value of the semiconductor device 100 by setting the bonding value between the bump 22 and the wiring pattern 12 to 40 [gf / mm 2 ]. The above bonding strength can be provided.

この実施形態では、フィルム基板１０が本発明の「基板」に対応し、ＮＣＰ樹脂３０が本発明の「樹脂」に対応している。また、ボンディング領域が本発明の「所定領域」に対応している。
なお、この実施形態では、配線パターン１２の表面にＳｎメッキを施している場合について説明したが、この表面に施しているメッキはＳｎに限られることはなく、例えば金（Ａｕ）メッキでも良い。〔実験３〕で後述するように、Ａｕメッキの場合には、Ｓｎメッキの場合と比べて、同一の接合温度、かつ同一の接合荷重で、配線パターン１２とバンプ２２とにより大きな接合強度を持たせることができる。 In this embodiment, the film substrate 10 corresponds to the “substrate” of the present invention, and the NCP resin 30 corresponds to the “resin” of the present invention. The bonding area corresponds to the “predetermined area” of the present invention.
In this embodiment, the case where the surface of the wiring pattern 12 is Sn plated has been described. However, the plating applied to the surface is not limited to Sn, and may be gold (Au) plating, for example. As will be described later in [Experiment 3], in the case of Au plating, the wiring pattern 12 and the bump 22 have higher bonding strength at the same bonding temperature and the same bonding load than in the case of Sn plating. Can be made.

（２）実験及び、その結果
〔実験１〕 本発明の実施形態で説明した配線パターン１２と、バンプ２２との接合温度、接合荷重をそれぞれ変えて、ボンディング後の接合強度を測定した。実験条件は、以下の通りである。
（条件）
ａ）測定方法：図３に示すように、接合後の半導体装置１００において、そのフィルム基板１０を基板固定台（ステージ）１５０に固定しておき、ＩＣチップ２０をＩＣ固定治具（ツール）１６０に固定して、ＩＣチップ２０を上方向に引き上げる。そして、ＩＣチップ２０がフィルム基板１０から離れる（又は、フィルム基板１０が破断する）ときの強度、即ち、接合強度（引き剥がし強度）を測定する。この実験１で得られた測定値はバンプ２２の単位面積当たり［１ｍｍ２］の接合強度であり、ＩＣチップ２０の重量を含まない値である。 (2) Experiment and Result [Experiment 1] The bonding strength after bonding was measured by changing the bonding temperature and bonding load between the wiring pattern 12 and the bump 22 described in the embodiment of the present invention. The experimental conditions are as follows.
(conditions)
a) Measuring method: As shown in FIG. 3, in the semiconductor device 100 after bonding, the film substrate 10 is fixed to a substrate fixing base (stage) 150, and the IC chip 20 is fixed to an IC fixing jig (tool) 160. The IC chip 20 is pulled upward. Then, the strength when the IC chip 20 moves away from the film substrate 10 (or the film substrate 10 breaks), that is, the bonding strength (peeling strength) is measured. The measurement value obtained in Experiment 1 is a bonding strength of [1 mm 2 ] per unit area of the bump 22 and does not include the weight of the IC chip 20.

ｂ）測定装置：ＰＴＲ−０１（（株）レスカ製）
ｃ）実験条件：ツール設定温度 １５０〜３８０［℃］（可変）
ステージ温度 １００［℃］
接合時間 ３秒
接合荷重 ２２．５〜６２．５［ｋｇｆ／ｍｍ２］（可変）
――――――――――――――――――
引き剥がし速度 １．０ｍｍ／ｓ
――――――――――――――――――
配線パターンのメッキ Ｓｎメッキ
（結果）
図４（Ａ）及び（Ｂ）は、実験１の結果を示す表図である。図４（Ｂ）は、図４（Ａ）に示した数値をグラフ化したものであり、横軸はツール１６０の設定温度（ツール設定温度）、縦軸は接合強度を示す。図４（Ａ）及び（Ｂ）に示すように、ツール設定温度が大きいほど、また、接合荷重が大きいほど、接合強度は大きかった。 b) Measuring device: PTR-01 (manufactured by Resuka Co., Ltd.)
c) Experimental conditions: Tool set temperature 150 to 380 [° C] (variable)
Stage temperature 100 [℃]
Joining time 3 seconds
Bonding load 22.5 to 62.5 [kgf / mm 2 ] (variable)
――――――――――――――――――
Stripping speed 1.0mm / s
――――――――――――――――――
Wiring pattern plating Sn plating (result)
4A and 4B are table diagrams showing the results of Experiment 1. FIG. FIG. 4B is a graph of the numerical values shown in FIG. 4A. The horizontal axis indicates the set temperature of the tool 160 (tool set temperature), and the vertical axis indicates the bonding strength. As shown in FIGS. 4A and 4B, the greater the tool set temperature and the greater the bonding load, the greater the bonding strength.

また、図４（Ａ）において、接合強度０は、ツール１６０によってＩＣチップ２０が持ち上がる前にＩＣチップ２０がフィルム基板１０から離れてしまった（つまり、接合強度は、ＩＣチップ２０の重量よりも小さく、測定不能である）ことを意味している。空欄は未測定を意味している。
このような結果から、接合温度が２００［℃］未満であり、かつ接合荷重が２５［ｋｇｆ／ｍｍ２］未満の場合には、接合強度はＩＣチップ２０の重量よりも小さく、接合強度が十分でないことが分かった。逆に言えば、接合強度を測定可能なレベルまで高めるためには、接合温度は少なくとも２００［℃］以上、接合荷重は２５［ｋｇｆ／ｍｍ２］以上必要であることが分かった。 In FIG. 4A, the bonding strength of 0 is that the IC chip 20 is separated from the film substrate 10 before the IC chip 20 is lifted by the tool 160 (that is, the bonding strength is larger than the weight of the IC chip 20). Small and unmeasurable). Blank indicates unmeasured.
From these results, when the joining temperature is less than 200 [° C.] and the joining load is less than 25 [kgf / mm 2 ], the joining strength is smaller than the weight of the IC chip 20 and the joining strength is sufficient. I understood that it was not. In other words, it has been found that in order to increase the bonding strength to a measurable level, it is necessary that the bonding temperature is at least 200 [° C.] or higher and the bonding load is 25 [kgf / mm 2 ] or higher.

〔実験２〕
実験１と同一の実験サンプルを用いて、温度サイクル試験と、高温放置試験との各試験を行った。これらの試験の条件は、以下の通りである。
（条件）
温度サイクル試験：−６５［℃］⇔＋１５０［℃］ ３００サイクル
高温放置試験 ：＋１５０［℃］ １０００時間
（結果）
図５は、実験２の結果を示す表である。図５の太線が信頼性試験に合格した条件と、不合格である条件とを区別している。即ち、太線枠内の条件（ツール設定温度、接合荷重）でボンディングされた半導体装置１００は、上記温度サイクル試験と、上記高温放置試験とにそれぞれ合格したものである。図５の表内の数値は、実験１で得られた数値をそのまま記載したものである。 [Experiment 2]
Using the same experimental sample as that in Experiment 1, a temperature cycle test and a high temperature storage test were performed. The conditions for these tests are as follows.
(conditions)
Temperature cycle test: −65 [° C.] ⇔ + 150 [° C.] 300 cycles High temperature standing test: +150 [° C.] 1000 hours (result)
FIG. 5 is a table showing the results of Experiment 2. The thick line in FIG. 5 distinguishes between conditions that pass the reliability test and conditions that fail. That is, the semiconductor device 100 bonded under the conditions within the bold line frame (tool set temperature, bonding load) has passed the temperature cycle test and the high temperature standing test, respectively. The numerical values in the table of FIG. 5 are the numerical values obtained in Experiment 1 as they are.

このような結果から、接合強度が凡そ４０［ｇｆ／ｍｍ２］以上あれば、上記両信頼性試験に合格することができることがわかった。配線パターン１２のメッキがＳｎの場合には、接合温度を２７０［℃］以上、半導体装置１００の耐熱温度値以下とし、かつ、接合荷重を３０［ｋｇｆ／ｍｍ２］以上、半導体装置１００の耐圧荷重値以下とすることで、バンプ２２と配線パターン１２との接合部分に４０［ｇｆ／ｍｍ２］以上の接合強度を持たせることができる。 From such a result, it was found that if the bonding strength is about 40 [gf / mm 2 ] or more, the both reliability tests can be passed. When the plating of the wiring pattern 12 is Sn, the junction temperature is set to 270 [° C.] or higher and the heat resistance temperature value of the semiconductor device 100 or lower, and the junction load is set to 30 [kgf / mm 2 ] or higher. By setting the load value or less, the bonding strength between the bump 22 and the wiring pattern 12 can be given a bonding strength of 40 [gf / mm 2 ] or more.

〔実験３〕
本発明の実施形態で説明した半導体装置１００において、その表面にＡｕメッキを施した場合について、その接合強度を測定した。実験条件は、以下の通りである。
（条件）
ａ）測定方法：実験１と同様に、接合後の半導体装置１００において、そのフィルム基板１０をステージ１５０に固定しておき、ＩＣチップ２０をツール１６０に固定して、ＩＣチップ２０を上方向に引き上げる。そして、ＩＣチップ２０がフィルム基板１０から離れる（又は、フィルム基板１０が破断）するときの強度を測定する。（図３参照。）。この実験３で得られた測定値は、ＩＣチップ２０の重量を含まない値である。 [Experiment 3]
In the semiconductor device 100 described in the embodiment of the present invention, the bonding strength was measured when Au plating was applied to the surface. The experimental conditions are as follows.
(conditions)
a) Measurement method: As in Experiment 1, in the semiconductor device 100 after bonding, the film substrate 10 is fixed to the stage 150, the IC chip 20 is fixed to the tool 160, and the IC chip 20 is moved upward. Pull up. And the intensity | strength when the IC chip 20 leaves | separates from the film board | substrate 10 (or the film board | substrate 10 fracture | ruptures) is measured. (See FIG. 3). The measured value obtained in Experiment 3 is a value that does not include the weight of the IC chip 20.

ｂ）測定装置：ＰＴＲ−０１（レスカ）
ｃ）実験条件：ツール設定温度 ２５〜３８０［℃］（可変）
ステージ温度 １００［℃］
接合時間 ３秒
接合荷重 ３２．５［ｋｇｆ／ｍｍ２］（固定）
――――――――――――――――――
引き剥がし速度 １．０ｍｍ／ｓ
――――――――――――――――――
配線パターンのメッキ：Ｓｎメッキ、Ａｕメッキ
（結果）
図６は、実験３の結果を示す図である。図６の横軸はツール設定温度、縦軸は接合強度を示す。図６に示すように、Ａｕメッキの場合も、Ｓｎメッキの場合と同様に、ツール温度が大きいほど、また、接合荷重が大きいほど、接合強度（引き剥がし強度）は大きかった。 b) Measuring device: PTR-01 (Resca)
c) Experimental conditions: Tool set temperature 25-380 [° C] (variable)
Stage temperature 100 [℃]
Joining time 3 seconds
Bonding load 32.5 [kgf / mm 2 ] (fixed)
――――――――――――――――――
Stripping speed 1.0mm / s
――――――――――――――――――
Wiring pattern plating: Sn plating, Au plating (result)
FIG. 6 is a diagram showing the results of Experiment 3. The horizontal axis in FIG. 6 indicates the tool set temperature, and the vertical axis indicates the bonding strength. As shown in FIG. 6, in the case of Au plating, as in the case of Sn plating, the bonding strength (peeling strength) was larger as the tool temperature was higher and the bonding load was larger.

また、少なくともツール設定温度が２８０〜３８０［℃］の範囲では、Ｓｎメッキと比べて、Ａｕメッキの方が、同一のツール設定温度（接合温度）、かつ同一の接合荷重で、接合強度が大きかった。例えば、ツール設定温度が２８０［℃］のときには、Ａｕメッキの接合強度はＳｎメッキの約８倍であった。
このような結果から、ＳｎメッキよりもＡｕメッキの方が、接合強度の向上に効果的であると言える。 In addition, at least in the tool setting temperature range of 280 to 380 [° C.], the Au plating has a higher bonding strength at the same tool setting temperature (bonding temperature) and the same bonding load than Sn plating. It was. For example, when the tool set temperature is 280 [° C.], the bonding strength of Au plating is about 8 times that of Sn plating.
From these results, it can be said that Au plating is more effective in improving bonding strength than Sn plating.

実施形態に係る半導体装置１００の構成例を示す断面図。FIG. 3 is a cross-sectional view illustrating a configuration example of a semiconductor device 100 according to the embodiment. 半導体装置１００の製造方法を示す工程図。10 is a process diagram illustrating a method for manufacturing the semiconductor device 100. FIG. 半導体装置１００における接合強度の測定方法を示す図。FIG. 4 is a view showing a method for measuring the bonding strength in the semiconductor device 100. 実験１の結果を示す表図。FIG. 6 is a table showing the results of Experiment 1. 実験２の結果を示す表。A table showing the results of Experiment 2. 実験３の結果を示す図。The figure which shows the result of the experiment 3. FIG.

符号の説明Explanation of symbols

１０ フィルム基板、１１ ポリイミド基材、１２ 配線パターン、２０ ＩＣチップ、２２ バンプ、３０ ＮＣＰ樹脂、１００ 半導体装置、１５０ ステージ、１６０ ツール   10 film substrate, 11 polyimide substrate, 12 wiring pattern, 20 IC chip, 22 bump, 30 NCP resin, 100 semiconductor device, 150 stage, 160 tool

Claims (3)

回路面にバンプを有するＩＣチップを、所定領域の内側から外側にかけて配線パターンを有する基板上に取り付けて半導体装置を製造する方法であって、
前記基板の前記所定領域上に樹脂を塗布する工程と、
前記樹脂が塗布された前記所定領域上に前記ＩＣチップの前記回路面を押し当てて、前記ＩＣチップの前記バンプを前記基板の前記配線パターンに接合する工程と、を含み、
前記バンプを前記配線パターンに接合する工程では、
前記バンプと前記配線パターンとの間の接合温度を２００［℃］以上、前記半導体装置の耐熱温度値以下とし、かつ、
当該間に加えられる接合荷重を２４５［Ｎ／ｍｍ２］以上、前記半導体装置の耐圧荷重値以下とすることを特徴とする半導体装置の製造方法。 A method of manufacturing a semiconductor device by attaching an IC chip having bumps on a circuit surface to a substrate having a wiring pattern from the inside to the outside of a predetermined region,
Applying a resin on the predetermined area of the substrate;
Pressing the circuit surface of the IC chip onto the predetermined area coated with the resin, and bonding the bumps of the IC chip to the wiring pattern of the substrate,
In the step of bonding the bump to the wiring pattern,
The bonding temperature between the bump and the wiring pattern is 200 [° C.] or more and the heat resistance temperature value of the semiconductor device, and
A method for manufacturing a semiconductor device, characterized in that a bonding load applied in the meantime is not less than 245 [N / mm 2 ] and not more than a pressure load value of the semiconductor device. 前記配線パターンの表面には錫（Ｓｎ）メッキが施され、
前記バンプを前記配線パターンに接合する工程では、
前記バンプと前記配線パターンとの間の接合温度を２７０［℃］以上、前記半導体装置の耐熱温度値以下とし、かつ、
当該間に加えられる接合荷重を２９４［Ｎ／ｍｍ２］以上、前記半導体装置の耐圧荷重値以下とすることを特徴とする請求項１に記載の半導体装置の製造方法。 The surface of the wiring pattern is tin (Sn) plated,
In the step of bonding the bump to the wiring pattern,
The bonding temperature between the bump and the wiring pattern is set to 270 [° C.] or more and the heat resistance temperature value of the semiconductor device, and
2. The method of manufacturing a semiconductor device according to claim 1, wherein a bonding load applied during the period is 294 [N / mm 2 ] or more and not more than a pressure load value of the semiconductor device. 前記配線パターンの表面には金（Ａｕ）メッキが施されていることを特徴とする請求項１に記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein a surface of the wiring pattern is plated with gold (Au).
JP2005011568A 2005-01-19 2005-01-19 Method for manufacturing semiconductor device Pending JP2006202897A (en)

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