JPS63237426A - Mounting of semiconductor - Google Patents
Mounting of semiconductorInfo
- Publication number
- JPS63237426A JPS63237426A JP62072245A JP7224587A JPS63237426A JP S63237426 A JPS63237426 A JP S63237426A JP 62072245 A JP62072245 A JP 62072245A JP 7224587 A JP7224587 A JP 7224587A JP S63237426 A JPS63237426 A JP S63237426A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- insulating resin
- resin
- electrode
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- 229920005989 resin Polymers 0.000 claims abstract description 65
- 239000011347 resin Substances 0.000 claims abstract description 65
- 238000000034 method Methods 0.000 claims abstract description 34
- 239000004020 conductor Substances 0.000 claims abstract description 23
- 229920001187 thermosetting polymer Polymers 0.000 claims abstract description 4
- 238000003825 pressing Methods 0.000 claims description 4
- 230000008602 contraction Effects 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 abstract description 24
- 238000005476 soldering Methods 0.000 abstract description 12
- 239000004850 liquid epoxy resins (LERs) Substances 0.000 abstract description 2
- 238000000576 coating method Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000004806 packaging method and process Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000011521 glass Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 101100117236 Drosophila melanogaster speck gene Proteins 0.000 description 1
- 239000004809 Teflon Substances 0.000 description 1
- 229920006362 Teflon® Polymers 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 229920006015 heat resistant resin Polymers 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 230000002747 voluntary effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野〕
この発明は半導体装方法に関し、特に回路基板への半導
体素子、例えばフリップチップＩＣの実装方法に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor mounting method, and more particularly to a method for mounting a semiconductor element, such as a flip-chip IC, onto a circuit board.
近年、電子機器の回路部には多くのＩＣが使用される。 In recent years, many ICs are used in circuit sections of electronic devices.
これらのＩＣは各種の形態で供給され、特に実装の高密
度化を達成するために、フリップチップＩＣの使用が増
加してきている。These ICs are available in various forms, and in particular, flip-chip ICs are increasingly being used to achieve higher packaging densities.
半導体素子の実装方法としては、従来は特開昭５７−４
５９９６号公報（チップ部品の装着方法に記載されるよ
うに、はんだ付は方法が用いられている。Conventionally, the method for mounting semiconductor elements was disclosed in Japanese Patent Application Laid-open No. 57-4.
As described in Japanese Patent No. 5996 (Chip component mounting method), a method is used for soldering.
フリップチップＩＣのはんだ付は方法としては、はんだ
ペーストの印刷、又ははんだボール等の成形はんだの配
置等により、はんだ材料を供給した後、ホットプレート
にのせて加熱する方法が広く行われていた。A commonly used method for soldering flip-chip ICs is to supply solder material by printing solder paste or arranging shaped solder such as solder balls, and then heating the solder material by placing it on a hot plate.
また、この方法に改良を加えた方法として第６図に示す
リフロー装置による方法が提案された。Further, as an improved method of this method, a method using a reflow apparatus shown in FIG. 6 has been proposed.
第６図は、リフロー装置を示す断面図で銅製のヒートブ
ロック（８）にヒータ（９）が埋設されており、その外
周にグラスファイバーと耐熱製樹脂（例えばデュポン社
のテフロン）との複合材料でできたベルト（１０）を配
置してものである。このように構成することにより、ベ
ルト（１０）上の温度分布は、中央部のヒータ （９）
に近い部分が最高となり、両端に行くに従って低くなる
。このベルト（１０）にはんだ付けすべ″き回路基板（
図示せず）を載せて移動させると、回路基板はベル）
（１０）の端部がら中央部に移動するにつれて、はんだ
付は温度まで次第に昇温される。ベルト（１０）の中央
部ではんだ付けがなされ、さらにベルト（１０）の中央
部から端部へ移動するにつれて徐々に冷やされる。Figure 6 is a cross-sectional view of the reflow equipment, in which a heater (9) is embedded in a copper heat block (8), and a composite material of glass fiber and heat-resistant resin (such as DuPont's Teflon) is used around the outer circumference of the heater (9). A belt (10) made of With this configuration, the temperature distribution on the belt (10) is controlled by the heater (9) in the center.
The area closest to is the highest, and it decreases towards the ends. This belt (10) should be soldered to the circuit board (
(not shown) and move the circuit board (not shown).
As we move from the ends of (10) to the center, the soldering temperature is gradually increased. Soldering is performed at the center of the belt (10) and gradually cooled as it moves from the center to the ends of the belt (10).
（発明が解決しようとする問題点〕
従来の半導体の実装方法では、以下に述べる問題点があ
った０回路基板はその底面から全体がはんだの融点（例
えばＳｎ／Ｐｂ＝６０／４０の場合、２３０ ’Ｃ程度
）を超えるまで加熱されることになり、回路基板上には
んだ付は温度での耐熱性を持たない回路素子や樹脂コー
ティング等が存在する時には適用できず、また、回路基
板が加熱されるため回路基板にそりが発生するなどの問
題点があった。さらに、はんだ付けを行うため、はんだ
が付着可能で、かつ強度的にも十分な導体材料を選定す
る必要があった。このため、工程が複雑になったり、コ
スト面や信頼性において好ましくない場合があった。(Problems to be Solved by the Invention) Conventional semiconductor mounting methods have had the following problems:0 The entire circuit board from its bottom surface is exposed to the melting point of the solder (for example, in the case of Sn/Pb=60/40, Soldering onto a circuit board cannot be applied when there are circuit elements or resin coatings that do not have heat resistance at that temperature, and the circuit board may be heated to over 230'C (approximately 230'C). This caused problems such as warping of the circuit board.Furthermore, since it was soldered, it was necessary to select a conductor material that would allow solder to adhere and was strong enough. As a result, the process may become complicated or may be unfavorable in terms of cost or reliability.
この発明はかかる問題点を解消するためになされたもの
で、はんだ付は温度での耐熱性を持たない回路素子、電
子部品や樹脂コーティング等を存する回路基板にも適用
でき、また加熱により発生する回路基板のそりが起こら
ず、信頼性、生産性が高く、かつ低コストで、回路基板
に半導体素子を実装できる半導体装方法を提供すること
を目的°とする。This invention was made to solve this problem, and soldering can be applied to circuit boards that have circuit elements, electronic components, resin coatings, etc. that do not have heat resistance at high temperatures, and also can be applied to circuit boards that have circuit elements, electronic components, and resin coatings that do not have heat resistance. It is an object of the present invention to provide a semiconductor mounting method that can mount semiconductor elements on a circuit board without causing warping of the circuit board, with high reliability and productivity, and at low cost.
この発明に係る半導体装方法は、電極が形成された半導
体素子と導体パターンが形成された回路基板を、導体パ
ターンと電極とが接触するように位置合わせして配置す
る工程、位置合わせされた半導体素子の一部または全体
を被覆し、かつ回路基板の表面と接触するように絶縁−
性樹脂を供給する工程、及び導体パターンと電極との接
触部を圧接状態で、供給された絶縁性樹脂を硬化する工
程を施し、半導体素子の電極と回路基板の導体パターン
を電気的に接続するものである。A semiconductor packaging method according to the present invention includes a step of aligning and arranging a semiconductor element on which an electrode is formed and a circuit board on which a conductor pattern is formed so that the conductor pattern and the electrode are in contact with each other; Insulate the element so that it covers part or all of the element and comes into contact with the surface of the circuit board.
The electrodes of the semiconductor element and the conductor pattern of the circuit board are electrically connected by supplying the insulating resin and curing the supplied insulating resin while the contact portion between the conductor pattern and the electrode is in pressure contact. It is something.
（作 用〕
この発明における絶縁性樹脂ははんだ付けのように高温
に加熱しなくても、硬化可能であり、回路基板と位置合
わせして配置された半導体素子を、半導体素子と回路基
板との間に圧力が加わった状態で固定し、半導体素子の
電極と回路基板上の導体パターンとを圧接し、電気的接
続を達成する作用を有する。(Function) The insulating resin of the present invention can be cured without being heated to a high temperature as in the case of soldering. The electrodes of the semiconductor element and the conductor pattern on the circuit board are fixed in a state where pressure is applied between them, and the electrodes of the semiconductor element are brought into pressure contact with the conductor pattern on the circuit board, thereby achieving an electrical connection.
以下、この発明の一実施例による半導体装方法を第１図
及び第２図に基づいて説明する０図において、（１）は
半導体素子で、例えばフリ、ブチツブＩＣ，（２）はフ
リップチップＩＣ（１）の表面に形成されたはんだ突起
電極、（３）はフリップチップＩＣ（１）を搭載する回
路基板、（４）は回路基１ （３）に形成された導体パ
ターンでフリップチップＩＣ（１）のはんだ突起電極（
２）と接続される回路基板電極、（５）は絶縁性樹脂、
（６）は絶縁性樹脂（５）を供給する絶縁性樹脂供給管
である。まず、第１図に示すように、フリップチップＩ
Ｃ（１）のはんだ突起電極（２）と回路基板電極（４）
を位置合わせして配置する。Hereinafter, a semiconductor mounting method according to an embodiment of the present invention will be explained based on FIGS. 1 and 2. In FIG. (1) is a solder protrusion electrode formed on the surface of the flip chip IC (3), (3) is a circuit board on which the flip chip IC (1) is mounted, (4) is a conductor pattern formed on the circuit board 1 (3), and the flip chip IC ( 1) Solder protrusion electrode (
2) is a circuit board electrode connected to, (5) is an insulating resin,
(6) is an insulating resin supply pipe that supplies the insulating resin (5). First, as shown in FIG.
C (1) solder protrusion electrode (2) and circuit board electrode (4)
Align and place.
次に第２図に示すように、フリップチップｒｃ（１）に
絶縁性樹脂供給管（６）により、回路基板（３）を接触
し、かつ、フリップチップＩＣ＜１）の一部、又は全体
を被覆するように絶縁性樹脂（５）を供給する。Next, as shown in FIG. 2, the circuit board (3) is brought into contact with the flip chip rc (1) through the insulating resin supply pipe (6), and a part or the whole of the flip chip IC<1) is contacted. Insulating resin (5) is supplied so as to cover.
この絶縁性樹脂（５）は樹脂硬化の際に体積収縮をおこ
すものを用いており、この場合は熱硬化型−液性エポキ
シ樹脂である。次にこの絶縁性樹脂（Ｓ）を硬化させる
ことにより、フリップチップｒｃ（１）が回路基板（４
）上に固定され、かつ絶縁性樹脂（５）が硬化時に収縮
する。この実施例で使用したエポキシ樹脂（５）の硬化
収縮率は０．７％程度であり、このため絶縁性樹脂（５
）がフリップチップＩＣ（１）を第２図における矢印入
方向に押し付ける収縮力が発生する。この収縮力により
フリップチップＩＣ（１）のはんだ突起電極（２）が回
路基板電極（４）に圧接され、回路基板（３）とフリッ
プチップＩｃ （１）の電気的接続がｉ：ｔられ、実装
が達成される。この場合、上記絶縁性樹脂（５）がフリ
ップチップＩＣ（１）の保護モールドの役割も果たすの
で、信頼性を向上できる効果も有する。以上述べたよう
に、回路ノ１駒板（３）とフリップチップＩｃ（１）を
樹脂硬化温度で実装でき、適当な硬化温度の樹脂を選択
すればはんだ付は温度での耐熱性を持たない回路素子や
樹脂コーティングを有する回路基板にも適用できるなど
適用の範囲が広（なる。This insulating resin (5) is one that causes volumetric contraction during resin curing, and in this case is a thermosetting liquid epoxy resin. Next, by curing this insulating resin (S), the flip chip rc (1) is attached to the circuit board (4).
), and the insulating resin (5) contracts when cured. The curing shrinkage rate of the epoxy resin (5) used in this example was about 0.7%, so the insulating resin (5)
) generates a contractile force that presses the flip chip IC (1) in the direction indicated by the arrow in FIG. This contraction force presses the solder projection electrode (2) of the flip chip IC (1) to the circuit board electrode (4), and the electrical connection between the circuit board (3) and the flip chip IC (1) is established. Implementation is achieved. In this case, since the insulating resin (5) also serves as a protective mold for the flip chip IC (1), it also has the effect of improving reliability. As mentioned above, the first circuit board (3) and the flip chip IC (1) can be mounted at a resin curing temperature, and if a resin with an appropriate curing temperature is selected, soldering can be performed on a circuit that does not have heat resistance at that temperature. The range of applications is wide, as it can be applied to elements and circuit boards with resin coatings.
さらに、回路基板（３）上の導体パターンを構成する導
体は通常のはんだ付けの困難なアルミニウム、 Ｉ
Ｔ Ｏ（Ｉｎｄｉｕ＋ｗ−Ｔｉｎ−Ｏｘｉｄｅ） ＋
クロムなど多くの材料を使用できる。Furthermore, the conductors constituting the conductor pattern on the circuit board (3) are made of aluminum, which is difficult to solder, and I
T O (Indiu+w-Tin-Oxide) +
Many materials can be used, including chrome.
１以下、更にこの一実施例を詳しく説明する。４ｍｍＸ
４ｍｍのチップに４０個の、例えば電極サイズは１６０
μｍφ程ＪＸのはんだ突起電極が形成されたフリップチ
ップＩｃ（１）のはんだ突起電極（２）と回路基）反と
して例えばガラス基板（３）上に、導体パターンとして
蒸着法により形成された銅の薄膜電極（４）を位置決め
し、エポキシ系絶縁性樹脂（５）をフリップチップＩＣ
（１）に供給した後硬化させ、回路基板（３）とフリッ
プチップＩＣ（１）を電気的に接続した試験片を作った
。比較品として上記と同一のフリップチップＩＣ（１）
と回路基板（３）を用いて、回路基板（３）にフリップ
チップＩｃ（１）をはんだ付けした試験片を作った。こ
れらの試験片をオープンで室温から１００℃まで加熱し
た時の１つの回路基板電極（４）とフリップチップＩＣ
のはんだ突起電極（２）の導通抵抗の変化を測定した。1, this embodiment will be further explained in detail below. 4mmX
40 electrodes on a 4mm chip, for example, the electrode size is 160
The solder protrusion electrode (2) of the flip chip Ic (1) on which the solder protrusion electrode of about μmφ JX is formed and the circuit board) is made of copper, which is formed as a conductor pattern by vapor deposition on, for example, a glass substrate (3). Position the thin film electrode (4) and attach the epoxy insulating resin (5) to the flip chip IC.
(1) and then cured to produce a test piece in which the circuit board (3) and the flip chip IC (1) were electrically connected. As a comparison product, the same flip chip IC as above (1)
A test piece was prepared by soldering a flip chip IC (1) to the circuit board (3) using the circuit board (3) and the circuit board (3). One circuit board electrode (4) and a flip-chip IC when these specimens were heated in the open from room temperature to 100°C.
The change in conduction resistance of the solder protrusion electrode (2) was measured.
横軸に温度（℃）、縦軸に導通抵抗（Ω）として第３図
に示し、直線Ｂははんだ付けによるもの、直Ｈｃはこの
発明の一実施例によるものである。第３図に示されるよ
うに、上記実施例（Ｃ）の方がはんだ付け（Ｂ）よりも
接続抵抗が低く、良好な結果が得られた。以上のように
、この発明の一実施例によれば、信頬性の高い、回路基
板とフリップチップＩＣの実装方法を得ることができる
。FIG. 3 shows the temperature (° C.) on the horizontal axis and the conduction resistance (Ω) on the vertical axis, where the straight line B is due to soldering and the straight line Hc is due to one embodiment of the present invention. As shown in FIG. 3, the connection resistance of Example (C) was lower than that of soldering (B), and good results were obtained. As described above, according to one embodiment of the present invention, it is possible to obtain a highly reliable mounting method for a circuit board and a flip chip IC.
また、この発明の他の実施例を第４図に示す。Further, another embodiment of the present invention is shown in FIG.
第４図において（７）はフリップチップＩＣ（１）を加
圧する加圧具であり、（１）〜（６）は第２図と同様文
略よ相当のものである。上記実施例と同様に、フリップ
ナツプＩＣ（１）を回路基板（３）上にはんだ突起電極
（２）と回路基板電極（４）とが接触するように位置決
めした後、加圧具（７）によってフリップチップＩＣ（
１）を回路基板（３）に押圧する。このはんだ突起電極
（２）と回路基板電極（４）とを圧接した状態で、絶縁
性樹脂供給管（６）で絶縁性樹脂（５）を供給し硬化さ
せる。絶縁性樹脂（５）が硬化後、加圧具（７）をａ−
ａ’の位置で切断する事により、回路基板（３）にフリ
ップチップＩＣ（１）を実装するものである。In FIG. 4, (7) is a pressurizing tool that pressurizes the flip chip IC (1), and (1) to (6) are equivalent to those shown in FIG. Similar to the above embodiment, after positioning the flip-nap IC (1) on the circuit board (3) so that the solder projection electrode (2) and the circuit board electrode (4) are in contact with each other, the pressurizing tool (7) is used to Flip chip IC (
1) is pressed onto the circuit board (3). With the solder projection electrode (2) and the circuit board electrode (4) in pressure contact, the insulating resin (5) is supplied through the insulating resin supply pipe (6) and hardened. After the insulating resin (5) has hardened, press the pressure tool (7) a-
The flip chip IC (1) is mounted on the circuit board (3) by cutting at the position a'.
この実施例によればはんだ突起電極（２）に大きさのバ
ラツキが有っても、はんだ突起電極（２）はやわらかい
ため、加圧具（７）による加圧によってはんだ突起電極
が（２）の大きい部分がつぶれて、このバラツキを吸収
する。このため、安定した電気的接続が可能となる。さ
らに、絶縁性樹脂の収集力に加えて加圧具（７）による
加圧力がプラスされるため、回路基板電極（４）とフリ
ップチップＩＣ（１）のはんだ突起電極（２）の圧接力
が増加し、回路基板（３）とフリップチップＩＣ（１）
の導通抵抗を下げることができ、−Ｊｆｆｉ接続の信鎖
性が向上できる。さらに、他の実施例として、フリップ
チップＩＣ（１）を回路基板（３）上に位置決めし、次
に加圧具（７）でフリップチップＩＣ（１）の中央部を
加圧する。このはんだ突起？ｉｉ：Ｊｌｉｘ（２）と回
路基板電極（４）とを圧接状態で第５図に示すように、
絶縁性樹脂（５）が加圧具（７）に付着しないように、
絶縁性樹脂（５）をフリップチップ＋ｃ（１）の外周部
に供給し硬化させる。According to this embodiment, even if there is variation in the size of the solder protruding electrode (2), since the solder protruding electrode (2) is soft, the solder protruding electrode (2) is pressed by the pressure tool (7). The large part of the material collapses to absorb this variation. Therefore, stable electrical connection is possible. Furthermore, in addition to the collecting force of the insulating resin, the pressing force by the pressing tool (7) is added, so the pressing force between the circuit board electrode (4) and the solder protrusion electrode (2) of the flip chip IC (1) is increased. Increased circuit board (3) and flip chip IC (1)
The conduction resistance of -Jffi can be lowered, and the reliability of the -Jffi connection can be improved. Furthermore, as another example, the flip chip IC (1) is positioned on the circuit board (3), and then the center part of the flip chip IC (1) is pressurized with a pressurizing tool (7). This solder bump? ii: Jlix (2) and circuit board electrode (4) are pressed together as shown in FIG.
To prevent the insulating resin (5) from adhering to the pressure tool (7),
Insulating resin (5) is supplied to the outer periphery of flip chip +c (1) and cured.
硬化後、加圧具（７）を上昇させ、回路基板（３）とフ
リップチップＩＣ（１）の実装を行うことにより、加圧
具（７）を毎回切断する必要がなく、生産性を高めるこ
とができる。After curing, the pressure tool (7) is raised and the circuit board (3) and flip chip IC (1) are mounted, eliminating the need to cut the pressure tool (7) each time, increasing productivity. be able to.
なおまた、複数個の絶縁性樹脂供給管を使用して、回路
基板（３）にフリップチップＩＣ（１）を実装すること
ができる。例えば、実装する半導体素子に対応して樹脂
成分の異なる絶縁性樹脂を別の絶縁性樹脂供給管で供給
でき、半導体素子接続の信顛性を高めることができる。Furthermore, the flip chip IC (1) can be mounted on the circuit board (3) using a plurality of insulating resin supply pipes. For example, insulating resins having different resin components can be supplied using separate insulating resin supply pipes depending on the semiconductor elements to be mounted, thereby improving the reliability of semiconductor element connections.
なおさらに、半導体素子の大きさ等に応じ、絶縁性樹脂
の供給量を変える事により、ｋＪＡ緑性相性樹脂）の硬
化時の収縮力すなわち回路基板（３）と半導体素子（１
）の圧接力を半導体素子（１）に対応して最適化でき、
回路基板（３）と半導体素子（１）の高信頼の実装が得
られる。さらに、圧接界面のずれによって半導体素子に
加わる水平方向の応力緩和の効果も期待できる。Furthermore, by changing the supply amount of the insulating resin according to the size of the semiconductor element, etc., the shrinkage force during curing of the kJA green compatible resin, that is, the circuit board (3) and the semiconductor element (1
) can be optimized according to the semiconductor element (1),
Highly reliable mounting of the circuit board (3) and the semiconductor element (1) can be obtained. Furthermore, the effect of relieving stress in the horizontal direction applied to the semiconductor element due to the displacement of the press-contact interface can be expected.
また、他の実施例として半導体の裏面側、即ち電極が形
成された面を反対の面倒に、この半導体素子の裏面より
も面積の広い平板を接触させた状態で絶縁性樹脂（５）
を供給し、硬化すれば半導体素子（，１）と回路基板（
３）との間に作用する圧力が増加し、安定な接続が得ら
れる。また、この平板の面積を変えることにより、圧力
を調整することもできる。As another example, the insulating resin (5) is placed in contact with the back side of the semiconductor, that is, the side on which the electrodes are formed, and a flat plate having a larger area than the back side of the semiconductor element.
After supplying and curing, the semiconductor element (,1) and the circuit board (
3) The pressure acting between the two ends increases and a stable connection is obtained. Moreover, the pressure can also be adjusted by changing the area of this flat plate.
また、絶縁性樹脂（５）として熱硬化型で熱膨張係数が
正の値を有する樹脂を使用した場合について説明する。Further, a case will be described in which a thermosetting resin having a positive coefficient of thermal expansion is used as the insulating resin (5).
１５０℃で硬化した後常温まで冷却すると樹脂の冷却に
よる収縮により半導体（１）と回路基ｅ［（３）の間の
圧力は増加する。このようにすることにより１２０℃以
下程度までは半導体素子（１）と回路基板（３）との間
に電気的接続を安定に保持する圧力が加わるため、温度
サイクル試験においても極めて安定なｒＩＺ ＩＩ性の
高い接続が得られる。When the resin is cured at 150° C. and then cooled to room temperature, the pressure between the semiconductor (1) and the circuit board e[(3) increases due to shrinkage of the resin due to cooling. By doing this, pressure is applied to maintain a stable electrical connection between the semiconductor element (1) and the circuit board (3) up to about 120°C or below, making rIZ II extremely stable even in temperature cycle tests. You can get a high quality connection.
さらに、常温硬化型の樹脂でも、硬化時の半導体素子（
１）と回路基板（３）との間の圧力が十分得られれば、
高温時の接続部の安定性は高い。Furthermore, even with room-temperature curing resin, semiconductor elements (
If sufficient pressure is obtained between 1) and the circuit board (3),
The stability of the connection at high temperatures is high.
さらに、！！ｌ縁性相性樹脂）を半導体素子の電極（２
）と回路基板上の導体パターン（４）の圧接部分には存
在しないようにすることにより、圧接界面への樹脂（５
）の侵入などを防ぎ、更に安定で信幀性の高い電気的接
続が得られる。moreover,! ! 1-edge compatible resin) to the electrode (2) of the semiconductor element.
) and the conductor pattern (4) on the circuit board.
), and provides a more stable and reliable electrical connection.
また、半導体素子（１）としてはんだｅｓｌンプのフリ
ップチップＩＣの場合を主として述べてきたが、全バン
プでもよく、さらに回路基板（３）に突起電極を形成す
ればペアチップ（電極はアルミニウムパッド）でもよい
。さらに回路基板（３）として蒸着法により薄膜電極（
４）が形成されたガラス基板について実施例で詳細に述
べたが、めっきやスペック法によって成膜された基板、
厚膜導体（例えば銀パラジウムゴ体）が形成されたセラ
ミック基板、ガラスエポキシ基板等の回路基板について
も同様の効果を奏する。Furthermore, although we have mainly described the case of a flip-chip IC with solder ESL bumps as the semiconductor element (1), it may be all bumps, or even pair chips (electrodes are aluminum pads) if protruding electrodes are formed on the circuit board (3). good. Furthermore, as a circuit board (3), thin film electrodes (
Although the glass substrate on which 4) was formed was described in detail in the Examples, the substrate on which the film was formed by plating or speck method,
Similar effects can also be achieved with circuit boards such as ceramic boards and glass epoxy boards on which thick-film conductors (for example, silver-palladium rubber bodies) are formed.
以上述べたように、この発明によれば、電極が形成され
た半導体素子と導体パターンが形成された回路基板を、
導体パターンと電極とが接触するように位置合わせして
配置する工程、位置合わせされた半導体素子の一部また
は全体を被覆し、かつ回路基板の表面と接触するように
絶縁性樹脂を供給する工程、及び導体パターンと電極と
の接触部を圧接状態で供給された絶縁性樹脂を硬化する
工程を施し、半導体素子の電極と回路°）！Ｅ板の導体
パターンを電気的に接続するこよにより、耐熱温度の低
い回路素子や樹脂コーティング等を有する回路基板にも
適用できる。さらに、絶縁性樹脂が半導体素子の保護モ
ールドの役割もするため、信軌性、生産性が高く、かつ
低コストで半導体素子を回路基板に実装できる半導体装
方法が得られる効果がある。As described above, according to the present invention, a semiconductor element on which an electrode is formed and a circuit board on which a conductive pattern is formed,
The process of aligning and arranging the conductor pattern and the electrode so that they are in contact with each other, and the process of supplying an insulating resin so that it covers part or all of the aligned semiconductor element and makes contact with the surface of the circuit board. , and a process of curing the insulating resin supplied in a press-contact state at the contact area between the conductor pattern and the electrode, thereby forming the electrode and circuit of the semiconductor element (°)! By electrically connecting the conductor patterns of the E-board, the present invention can be applied to circuit boards having low heat-resistant temperature circuit elements, resin coatings, etc. Furthermore, since the insulating resin also serves as a protective mold for the semiconductor element, it is possible to obtain a semiconductor packaging method that has high reliability and productivity and can mount the semiconductor element on a circuit board at low cost.
第１図はこの発明の一実施例による半導体装方法に係り
、回路基板と半導体素子を位置合わせして配置した工程
の接続部周辺を示す側面図、第２図は同じく絶縁性樹脂
を供給した工程の接続部周辺を示す断面図、第３図はこ
の発明の一実施例によって得られた接続部と従来の方法
による接続部の温度に対する導通抵抗を比較して示す特
性図、第４図、第５図はそれぞれこの発明の他の実施例
に係る工程途中の接続部周辺を示す断面図、第６図は従
来の半導体装方法に係るリフロー装置を示す断面図であ
る。
（１）・・・ 半導体素子、（２）・・・ 電極、（３
）・・・回路基板、（４）・・・ 導体パターン、（５
）・・・ 絶縁性樹脂。
なお、図中、同一符号は同一、又は相当部分を示す。
代理人 大 岩 増 雄
第１図
第２図
ｊ ： ｌ！Ｊ路Ｊ、液、 ４：導体ハ放−ン
ｊ：絶縁゛庄樹脂
第３図
第４図
第５図
第６図
手続補正書（自発）
ａｌ ６＆ ９ｓ′９ａFIG. 1 is a side view showing the vicinity of the connection part in the process of aligning and arranging the circuit board and the semiconductor element, and FIG. 2 is a side view of the semiconductor packaging method according to an embodiment of the present invention, and FIG. 3 is a cross-sectional view showing the vicinity of the connection part in the process; FIG. 3 is a characteristic diagram showing a comparison of the conduction resistance with respect to temperature of the connection part obtained by an embodiment of the present invention and the connection part obtained by the conventional method; FIG. FIG. 5 is a cross-sectional view showing the vicinity of a connection part in the middle of a process according to another embodiment of the present invention, and FIG. 6 is a cross-sectional view showing a reflow apparatus according to a conventional semiconductor packaging method. (1)... Semiconductor element, (2)... Electrode, (3
)...Circuit board, (4)... Conductor pattern, (5
)... Insulating resin. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Agent Masuo Oiwa Figure 1 Figure 2 j: l! J path J, liquid, 4: Conductor ring J: Insulating resin Figure 3 Figure 4 Figure 5 Figure 6 Procedural amendment (voluntary) al 6 &9s'9a
Claims (6)
成された回路基板を、上記導体パターンと上記電極とが
接触するように位置合わせして配置する工程、上記位置
合わせされた半導体素子の一部または全体を被覆し、か
つ上記回路基板の表面と接触するように絶縁性樹脂を供
給する工程、及び上記導体パターンと上記電極との接触
部を圧接状態で、上記供給された絶縁性樹脂を硬化する
工程を施し、上記半導体素子の電極と上記回路基板の導
体パターンを電気的に接続することを特徴とする半導体
実装方法。(1) A step of aligning and arranging a semiconductor element on which an electrode is formed and a circuit board on which a conductor pattern is formed so that the conductor pattern and the electrode are in contact with each other; a step of supplying an insulating resin so as to cover a portion or the entire surface of the circuit board and contacting the surface of the circuit board; and a step of applying the supplied insulating resin to a contact portion of the conductor pattern and the electrode in a press-contact state. 1. A semiconductor mounting method, comprising performing a curing step to electrically connect electrodes of the semiconductor element and conductive patterns of the circuit board.
工程の後、上記半導体素子と上記回路基板間に加圧具を
用いて圧力を重畳した状態で、絶縁性樹脂を供給する工
程、及び上記供給した絶縁性樹脂を硬化させる工程を施
すようにしたことを特徴とする特許請求の範囲第１項記
載の半導体実装方法。(2) After the step of aligning and arranging the semiconductor element and the circuit board, supplying an insulating resin while applying pressure between the semiconductor element and the circuit board using a pressure tool; 2. The semiconductor mounting method according to claim 1, further comprising a step of curing the supplied insulating resin.
であることを特徴とする特許請求の範囲第１項記載また
は第２項記載の半導体実装方法。(3) The semiconductor mounting method according to claim 1 or 2, wherein the insulating resin is a resin that causes volumetric contraction during curing.
を有する樹脂であることを特徴とする特許請求の範囲第
１項または第２項記載の半導体実装方法。(4) The semiconductor mounting method according to claim 1 or 2, wherein the insulating resin is a thermosetting resin having a positive coefficient of thermal expansion.
徴とする特許請求の範囲第１項ないし第３項記載のいず
れかに記載の半導体実装方法。(5) The semiconductor mounting method according to any one of claims 1 to 3, wherein the insulating resin is a resin that hardens at room temperature.
りも面積の広い平板を接触させた状態で絶縁性樹脂を供
給する工程、及び上記供給した絶縁性樹脂を硬化させる
工程を施すようにしたことを特徴とする特許請求の範囲
第１項ないし第５項のいずれかに記載の半導体実装方法
。(6) A step of supplying an insulating resin to the surface opposite to the electrode formation surface of the semiconductor element with a flat plate having a larger area than this surface in contact with the surface, and a step of curing the supplied insulating resin. A semiconductor mounting method according to any one of claims 1 to 5, characterized in that:
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62072245A JPH0671026B2 (en) | 1987-03-25 | 1987-03-25 | Semiconductor mounting method |
| US07/363,710 US4942140A (en) | 1987-03-25 | 1989-06-09 | Method of packaging semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62072245A JPH0671026B2 (en) | 1987-03-25 | 1987-03-25 | Semiconductor mounting method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63237426A true JPS63237426A (en) | 1988-10-03 |
| JPH0671026B2 JPH0671026B2 (en) | 1994-09-07 |
Family
ID=13483715
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62072245A Expired - Lifetime JPH0671026B2 (en) | 1987-03-25 | 1987-03-25 | Semiconductor mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0671026B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02110949A (en) * | 1988-10-19 | 1990-04-24 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| US6197612B1 (en) | 1997-10-23 | 2001-03-06 | Nec Corporation | Semiconductor chip mounting apparatus capable of preventing connected portion between semiconductor chip and substrate from thermal stress and method thereof |
| WO2006123554A1 (en) * | 2005-05-17 | 2006-11-23 | Matsushita Electric Industrial Co., Ltd. | Flip-chip mounting body and flip-chip mounting method |
| JP2012089740A (en) * | 2010-10-21 | 2012-05-10 | Fujitsu Ltd | Manufacturing method and bonding method of semiconductor device |
| US10104772B2 (en) | 2014-08-19 | 2018-10-16 | International Business Machines Incorporated | Metallized particle interconnect with solder components |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62281360A (en) * | 1986-05-29 | 1987-12-07 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
-
1987
- 1987-03-25 JP JP62072245A patent/JPH0671026B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62281360A (en) * | 1986-05-29 | 1987-12-07 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02110949A (en) * | 1988-10-19 | 1990-04-24 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| US6197612B1 (en) | 1997-10-23 | 2001-03-06 | Nec Corporation | Semiconductor chip mounting apparatus capable of preventing connected portion between semiconductor chip and substrate from thermal stress and method thereof |
| WO2006123554A1 (en) * | 2005-05-17 | 2006-11-23 | Matsushita Electric Industrial Co., Ltd. | Flip-chip mounting body and flip-chip mounting method |
| JP2012089740A (en) * | 2010-10-21 | 2012-05-10 | Fujitsu Ltd | Manufacturing method and bonding method of semiconductor device |
| US10104772B2 (en) | 2014-08-19 | 2018-10-16 | International Business Machines Incorporated | Metallized particle interconnect with solder components |
| US10588219B2 (en) | 2014-08-19 | 2020-03-10 | International Business Machines Corporation | Metallized particle interconnect with solder components |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0671026B2 (en) | 1994-09-07 |
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