JPH02188936A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH02188936A JPH02188936A JP826389A JP826389A JPH02188936A JP H02188936 A JPH02188936 A JP H02188936A JP 826389 A JP826389 A JP 826389A JP 826389 A JP826389 A JP 826389A JP H02188936 A JPH02188936 A JP H02188936A
- Authority
- JP
- Japan
- Prior art keywords
- wiring pattern
- substrate
- conductive film
- conductive
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 239000002245 particle Substances 0.000 claims abstract description 18
- 239000011347 resin Substances 0.000 claims abstract description 17
- 229920005989 resin Polymers 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 15
- 238000002844 melting Methods 0.000 claims abstract description 12
- 230000008018 melting Effects 0.000 claims abstract description 12
- 238000010438 heat treatment Methods 0.000 claims abstract description 5
- 239000002184 metal Substances 0.000 abstract description 14
- 229910052751 metal Inorganic materials 0.000 abstract description 14
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 239000011521 glass Substances 0.000 description 4
- 238000009413 insulation Methods 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 239000012847 fine chemical Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012188 paraffin wax Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000001993 wax Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29199—Material of the matrix
- H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
Abstract
Description
【発明の詳細な説明】
【産業上の利用分野1
本発明は、半導体チップの接続端子と基板上に形成した
配線パターンとの接合において、配線パターンへ突起電
極を形成した半導体装置及びその製造方法に関する。Detailed Description of the Invention [Industrial Application Field 1] The present invention relates to a semiconductor device in which protruding electrodes are formed on a wiring pattern in bonding a connecting terminal of a semiconductor chip to a wiring pattern formed on a substrate, and a method for manufacturing the same. Regarding.
〔従来の技術]
従来、基板上に形成した配線パターンと半導体チップの
接続端子間へ突起電極を介し導通させる工程を持つ半導
体装置として、金属パッド上へ半田バンプを形成した後
、配線パターン上へフェイズダウンで半田付けを行い接
続を得る方式や、金属パッドに対応する配線パターン上
へ導電粒子を含んだ硬化性樹脂を印刷した後、配線パタ
ーンと金属パッドを位置合せせしめ、圧力を加える事に
より導電粒子を通じ導通を得た後、基板とICチップ間
に介在させた硬化性樹脂を硬化させる事により物理的な
固定を行う方式がある。[Prior Art] Conventionally, a semiconductor device has a process of creating electrical continuity between a wiring pattern formed on a substrate and a connecting terminal of a semiconductor chip through a protruding electrode. By soldering in a phase-down manner to obtain a connection, or by printing a hardening resin containing conductive particles onto the wiring pattern corresponding to the metal pad, aligning the wiring pattern and the metal pad, and applying pressure. There is a method of physically fixing the IC chip by curing a curable resin interposed between the substrate and the IC chip after establishing continuity through conductive particles.
r発明が解決しようとする課題1
しかしながら、半田バンブを用いる方式においてはバン
ブ形成する工程が複雑であり、工数が多くコスト高にな
るという開聞点を有する。また導電粒子を含んだ硬化性
樹脂を印刷する方式では、高精度な位置合せ技術が必要
であり、歩留りが上がりにくく、かつ配線パターン間、
配線ピッチが小さくなった場合5配線パターンの絶縁を
とるのか困難になると言う問題を持つ。Problem 1 to be Solved by the Invention However, the method using solder bumps has the disadvantage that the process of forming the bumps is complicated, requiring many man-hours and increasing costs. In addition, the method of printing curable resin containing conductive particles requires highly accurate positioning technology, making it difficult to increase yield and making it difficult to
There is a problem in that when the wiring pitch becomes small, it becomes difficult to insulate the five wiring patterns.
本発明は、このような問題点を解決するもので高精度な
位置合せ技術なしに、安価に金属パッドに対応した配線
パターン上へ導電粒子を含んだ硬化性樹脂を配線パター
ン間の絶縁をそこなう事なく配置する工程を含んだ半導
体装置を提供する事を目的とする。The present invention solves these problems by applying a curable resin containing conductive particles onto wiring patterns corresponding to metal pads at low cost and damaging the insulation between wiring patterns without using highly accurate positioning technology. It is an object of the present invention to provide a semiconductor device including a process of arranging it without any problems.
(課題を解決するための手段1
本発明による半導体装置は、基板上に形成した配線パタ
ーンと半導体チップの接続端子間へ突起電極を介し導通
させる工程を持つ半導体装置において、低温溶解IM脂
に導電粒子を分散させた導電性フィルムを配線パターン
を含む基板上へ配置した後、基板及び配線パターン上へ
熱を加える事により選択的に配線パターン上へ導電性フ
ィルムを転写し、突起電極を形成する工程を有する事を
特徴とする半導体装置。(Means for Solving the Problems 1) A semiconductor device according to the present invention is a semiconductor device having a step of providing electrical continuity between a wiring pattern formed on a substrate and a connection terminal of a semiconductor chip via a protruding electrode. After placing a conductive film with dispersed particles on a substrate containing a wiring pattern, heat is applied to the substrate and the wiring pattern to selectively transfer the conductive film onto the wiring pattern to form protruding electrodes. A semiconductor device characterized by having a process.
1作 用] 本発明の作用を図面に基づき詳細に説明する。For 1 work] The operation of the present invention will be explained in detail based on the drawings.
第1図は、本発明の基板の上面図であり、ガラス、エポ
キシで形成された基板■上に半導体チップに合せ配線パ
ターン2を形成する。このとき配線パターンは金属の様
な比熱の低い物質で形成するのが好ましい。FIG. 1 is a top view of a substrate according to the present invention, and a wiring pattern 2 is formed on a substrate (2) made of glass and epoxy to match a semiconductor chip. At this time, the wiring pattern is preferably formed of a material with low specific heat, such as metal.
第2図は本発明を工程順に示した図である。まず(a)
図の如く配線パターン2付き基板1へ導電粒子6を低温
融解樹脂5へ分散させ保護フィルム4上へ塗布した導電
フィルム3を載せ、上面もしくは下面より、加熱を行う
、すると、基板と配線パターンとの比熱もしくは反射率
の差により。FIG. 2 is a diagram showing the present invention in the order of steps. First (a)
As shown in the figure, a conductive film 3 made by dispersing conductive particles 6 in a low-temperature melting resin 5 and coating it on a protective film 4 is placed on a substrate 1 with a wiring pattern 2, and heating is performed from the upper or lower surface. Due to the difference in specific heat or reflectance.
基板と配線パターン間に温度差が生じる。加熱時間を最
適化する事により2図(b)の如く配線パターン上の導
電フィルムのみを融解させ突起電極8を形成する。A temperature difference occurs between the board and the wiring pattern. By optimizing the heating time, only the conductive film on the wiring pattern is melted to form the protruding electrodes 8 as shown in FIG. 2(b).
次に図(c)の如く半導体チップ9上の金属パッドIO
と突起電極との位置合せを行い加圧する事により金属パ
ッドと配線パターン間の接続を取る。Next, as shown in Figure (c), the metal pad IO on the semiconductor chip 9
A connection is made between the metal pad and the wiring pattern by aligning the pad and the protruding electrode and applying pressure.
〔実施例11
第1図において、厚さ1.1mmのガラス板を基板1と
し、配線パターン2として50Ω/12のITOを線幅
100μmピッチ200μmでパタニングした後ITO
上のみへニッケルを2000人の厚さに無電解メツキし
た。[Example 11 In Fig. 1, a glass plate with a thickness of 1.1 mm was used as the substrate 1, and ITO was patterned as the wiring pattern 2 with a line width of 100 μm and a pitch of 200 μm.
Electroless plating of nickel was applied to the top only to a thickness of 2000 mm.
次に低温融解樹脂5として使用する融点80℃のカルバ
ナワックス中に、平均粒径7μmの樹脂ボール(種水フ
ァインケミカルKK製、商品名ミクロパール)にニッケ
ルを厚さ1000人メツキした物を導電粒子6として5
0%wt分散させ保護フィルム4上へ塗布して作った導
電フィルム3を基板上へ配置した。Next, resin balls with an average particle size of 7 μm (manufactured by Tanezu Fine Chemicals KK, trade name: Micro Pearl) were plated with nickel to a thickness of 1000 to conductive, in carbana wax with a melting point of 80°C used as the low-temperature melting resin 5. 5 as particle 6
A conductive film 3 prepared by dispersing 0% wt and coating it on a protective film 4 was placed on a substrate.
次にガラス板下部より波長4μm出力100Wの遠赤外
線ヒーターを10cm離し8秒間照射したところ配線バ
クーン上の導電フィルムのみ低温融解樹脂が融解し、突
起電極8が形成できた。Next, when a far-infrared heater with a wavelength of 4 μm and an output of 100 W was irradiated from the bottom of the glass plate at a distance of 10 cm for 8 seconds, the low-temperature melting resin was melted only on the conductive film on the wiring bag, and the protruding electrodes 8 were formed.
次に半導体チップ9に対応する基板上へ紫外線硬化樹脂
を塗布し、金属パッドエ0と突起電極を位置合せして、
半導体チップ上より10kg/cTI+2の圧力を加え
る事により導電粒子を介し、金属パッドと配線パターン
の導通を得る事ができた。Next, apply ultraviolet curing resin onto the substrate corresponding to the semiconductor chip 9, align the metal pad 0 and the protruding electrode,
By applying a pressure of 10 kg/cTI+2 from above the semiconductor chip, it was possible to establish electrical continuity between the metal pad and the wiring pattern via the conductive particles.
さらにガラス板下部より3000mJの紫外線を明射す
る事により、紫外線硬化樹脂を硬化せしめ、半導体チッ
プの固定を行った。Furthermore, by irradiating ultraviolet rays of 3000 mJ from the bottom of the glass plate, the ultraviolet curing resin was cured and the semiconductor chip was fixed.
以上の半導体チップの実装を行う事により、高精度な位
置合せ技術なしに突起電極を形成し、かつ配線パターン
間の絶縁を保つ事ができた。By mounting the semiconductor chip as described above, it was possible to form protruding electrodes without the need for highly accurate alignment techniques, and to maintain insulation between wiring patterns.
〔実施例21
第1図において厚さ1.5mmのエポキシ基板を基板1
とし、35um厚の銅箔をパターニングした物を配線パ
ターン2とした。[Example 21 In FIG. 1, an epoxy substrate with a thickness of 1.5 mm is used as substrate 1.
Wiring pattern 2 was obtained by patterning a copper foil with a thickness of 35 um.
また低温融解樹脂5として融点60℃のパラフィンワッ
クスを、導電粒子6として粒径15μmのニッケル粒子
を用い低温融解樹脂中へ導電粒子を60%分散させ保護
フィルム4上へ塗布した物を導電フィルム3とした。Further, a conductive film 3 is obtained by dispersing 60% of the conductive particles in the low-temperature melting resin using paraffin wax with a melting point of 60° C. as the low-temperature melting resin 5 and using nickel particles with a particle size of 15 μm as the conductive particles 6. And so.
配線パターン上へ導電フィルムを配置し半導体チップに
大きさを合せた金属ブロックを70℃へ加熱し、導電フ
ィルム上より5kg/cm’の加重で7秒間押し当てた
ところ、銅とエポキシの比熱の差より、銅パターンのみ
60℃を越え、配線パターンの部分のみの低温融解樹脂
を融解せしめ、突起電極を形成する事ができた。A conductive film was placed on the wiring pattern, and a metal block sized to the semiconductor chip was heated to 70°C and pressed against the conductive film for 7 seconds at a load of 5 kg/cm'. Due to the difference, only the copper pattern was heated to over 60°C, and the low-temperature melting resin only in the wiring pattern was melted, making it possible to form a protruding electrode.
次に突起電極と金属パッドの位置合せを行い半導体チッ
プ上より2kgfの加重をバネで加える事により、突起
電極を介し金属パッドと配線パターンの導通なとり、か
つ半導体チップを固定する事ができた。Next, by aligning the protruding electrodes and the metal pads and applying a load of 2 kgf from above the semiconductor chip using a spring, it was possible to establish conduction between the metal pads and the wiring pattern via the protruding electrodes, and to fix the semiconductor chip.
以上の半導体チップの実装を行う事により実施例1と同
様の効果を得る事ができた。By mounting the semiconductor chip as described above, the same effects as in Example 1 could be obtained.
[発明の効果]
以上述べた様に、本発明によれば精密な位置合せを行う
事態(金属パッドに対応して配線パターン上へ突起電極
を形成する事ができた。[Effects of the Invention] As described above, according to the present invention, it was possible to perform precise alignment (protruding electrodes could be formed on wiring patterns in correspondence with metal pads).
また、配線パターン上導電フィルムのみを選択的に融解
させる事が可能なため、細密な配線パターンに対しても
絶縁性を損なう事なく突起電極を形成する事ができた。In addition, since it was possible to selectively melt only the conductive film on the wiring pattern, it was possible to form protruding electrodes even on minute wiring patterns without impairing insulation properties.
第1図は本発明における基板及び配線パターンの上面図
。
第2図(a)、(b)、(c)は、本発明の製造工程を
示した図。
基板
配線パターン
導電フィルム
保護フィルム
低温融解樹脂
導電粒子
加熱
突起電極
金属パッド
10・・・半導体チップ
以上
出願人 セイコーエプソン株式会社
代理人 弁理士 上 柳 雅 誉(他1名)第1図
第2図
(a’)FIG. 1 is a top view of the substrate and wiring pattern in the present invention. FIGS. 2(a), (b), and (c) are diagrams showing the manufacturing process of the present invention. Board wiring pattern Conductive film Protective film Low-temperature melting resin Conductive particles Heating protruding electrode Metal pad 10... Semiconductor chip and above Applicant Seiko Epson Corporation Representative Patent attorney Masaharu Kamiyanagi (and 1 other person) Figure 1 Figure 2 ( a')
Claims (2)
接続端子間へ突起電極を介し導通させる工程を有する半
導体装置の製造方法において、低温融解樹脂に導電粒子
を分散させた導電性フィルムを配線パターンが形成され
た基板上へ配置した後、基板及び配線パターンを加熱す
ることにより選択的に配線パターン上へ導電性フィルム
を転写し、突起電極を形成する工程を有することを特徴
とする半導体装置の製造方法。(1) In a method for manufacturing a semiconductor device that includes a step of creating electrical continuity between a wiring pattern formed on a substrate and a connecting terminal of a semiconductor chip through a protruding electrode, a conductive film made of conductive particles dispersed in a low-temperature melting resin is used to form a wiring pattern. A semiconductor device comprising the step of selectively transferring the conductive film onto the wiring pattern by heating the substrate and the wiring pattern after placing the conductive film on the substrate on which the wiring pattern is formed, thereby forming a protruding electrode. Production method.
パターン上に導電粒子が分散してなる導電性フィルムを
配設したことを特徴とする半導体装置。(2) A semiconductor device, characterized in that a conductive film in which conductive particles are dispersed is disposed on a wiring pattern by the method for manufacturing a semiconductor device according to claim 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP826389A JPH02188936A (en) | 1989-01-17 | 1989-01-17 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP826389A JPH02188936A (en) | 1989-01-17 | 1989-01-17 | Semiconductor device and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02188936A true JPH02188936A (en) | 1990-07-25 |
Family
ID=11688268
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP826389A Pending JPH02188936A (en) | 1989-01-17 | 1989-01-17 | Semiconductor device and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02188936A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6077725A (en) * | 1992-09-03 | 2000-06-20 | Lucent Technologies Inc | Method for assembling multichip modules |
-
1989
- 1989-01-17 JP JP826389A patent/JPH02188936A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6077725A (en) * | 1992-09-03 | 2000-06-20 | Lucent Technologies Inc | Method for assembling multichip modules |
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